BRIEF DESCRIPTION OF THE DRAWINGS
The structure and the technical means adopted by the present invention to achieve the above and other objects can be best understood by referring to the following detailed description of the preferred embodiments and the accompanying drawings, wherein:
FIG. 1 is a block diagram of a conventional interface transmission structure between a CPU and a memory unit;
FIG. 2 is a block diagram of an interface transmission structure between a central processor and at least one module according to one preferred embodiment of the present invention;
FIG. 3 is a schematic diagram of voltage amplitudes of first status messages according to the preferred embodiment of the present invention;
FIG. 4 is a schematic diagram of voltage amplitudes of second status messages according to the preferred embodiment of the present invention;
FIG. 5 is a code table of status messages according to the preferred embodiment of the present invention;
FIG. 6 is a flow chart of an interface transmission method of first data messages between modules according to one preferred embodiment of the present invention;
FIG. 7 is a flow chart of an interface transmission method of second data messages between modules according to one preferred embodiment of the present invention;
FIG. 8 is a flow chart of an interface transmission method of first data messages between modules according to another preferred embodiment of the present invention;
FIG. 9 is a flow chart of an interface transmission method of second data messages between modules according to another preferred embodiment of the present invention;
FIG. 10
a is a schematic diagram of a status message of “wake-up” according to the preferred embodiment of the present invention;
FIG. 10
b is a schematic diagram of a status message of “power-saving mode” according to the preferred embodiment of the present invention;
FIG. 10
c is a schematic diagram of a status message of “fault exists in second data message determined and received by central processor” according to the preferred embodiment of the present invention; and
FIG. 10
d is a schematic diagram of a status message of “fault exists in first data message determined and received by modules” according to the preferred embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Low Voltage Differential Signaling (LVDS) is a high-efficiency technology applied for transmitting data, which features a low voltage differential signal ranging from 250 mV to 450 mV with fast transition times to address high transmission speed from 100 Mbps to greater than 1 Gbps while providing a low voltage swing to minimize power dissipation. Furthermore, the LVDS technology can be applied to simple linear drivers and receiver physical layer devices as well as more complex interface communication chipsets. The LVDS technology can provide a narrow, high speed, low power LVDS Interface for channel link chipsets, wherein the multiplex and demultiplex transmission of the channel link chipsets would slow TTL (Transistor Logic) signal lines. These chipsets provide dramatic systems savings in cable and connector costs, as well as a reduction in the amount of physical space required for the connector footprint. Referring now to FIGS. 2, 3, and 4, an interface transmission structure between modules according to one preferred embodiment of the present invention is illustrated. As shown, an electronic device 1 is provided with a central processor 10 (CPU) installed therein, and the central processor 10 is formed with an LVDS module 100 therein, a first pin 11, and a second pin 12 thereon. The first pin 11 and the second pin 12 are electrically connected to the LVDS module 100 for transmitting low voltage differential signals. The LVDS module 100 is used to receive different voltage amplitudes and to set a plurality of different potential levels. Meanwhile, the first pin 11 and the second pin 12 respectively output a corresponding first output signal according to each of the potential levels, and the first output signal thereof can be combined into a plurality of command messages 41, a plurality of first data messages 42, and a plurality of first status messages 45. Additionally, the first pin 11 and the second pin 12 are electrically coupled to a third pin 21 and a fourth pin 22 of at least one external module 20, such as a flash memory, respectively, so that the third pin 21 and the fourth pin 22 can be used to receive the command messages 41, the first data messages 42, and the first status messages 45. Furthermore, at least one module 20 is also able to receive the different voltage amplitudes and to output a corresponding second output signal according to the potential levels via the third pin 21 and the fourth pin 22, respectively, and the second output signal thereof can be combined into a plurality of second data messages 51 and a plurality of second status messages 52 for being transmitted to the central processor 10, so as to substitute the conventional data lines 400, address lines 300, and control lines 500 as shown in FIG. 1, and expedite processing each message as described above.
Referring back to FIGS. 2, 3, and 4, the LVDS module 100 of the preferred embodiment of the present invention has a first potential level (not shown), a second potential level (not shown), a third potential level (not shown), and a fourth potential level (not shown) different from each other, wherein the fourth potential level is greater than the third potential level, the third potential level is greater than the second potential level, and the second potential level is greater than the first potential level. The central processor 10 respectively generates the corresponding first output signal according to variation of the second potential level and the third potential level via the first pin 11 and the second pin 12 so that the corresponding first output signal can be combined into the command messages 41 and the first data messages 42, as shown in FIG. 3. Moreover, the central processor 10 respectively generates the corresponding first output signal according to the first potential level and the fourth potential level so that the corresponding first output signal can be combined into the first status messages 45, as shown in FIG. 3. In another aspect, at least one module 20 respectively generates the corresponding second output signal according to variation of the second potential level and the third potential level via the third pin 21 and the fourth pin 22 so that the corresponding second output signal can be combined into the second data messages 51, as shown in FIG. 4. Moreover, at least one module 20 respectively generates the corresponding second output signal according to the first potential level and the fourth potential level so that the corresponding second output signal can be combined into the second status messages 52, as shown in FIG. 4.
Furthermore, in order to minimize power dissipation of the transmission between the central processor 10 and at least one module 20, the central processor 10 and at least one module 20 will be switched into a power-saving mode including a standby mode and an idle mode if being in an inaction status. Referring still to FIGS. 2, 3, and 4, the central processor 10 sends the first output signal according to the first potential level via the first pin 11, and sends the first output signal according to the first potential level via the second pin 12, so that the first output signals are combined into the first status messages 45 which represents to enter the power-saving mode. Moreover, at least one module 20 sends the second output signal according to the first potential level via the third pin 21, and sends the second output signal according to the first potential level via the fourth pin 22, so that the second output signals are combined into the second status messages 52 which represent power-saving mode. Thereby, the central processor 10 and at least one module 20 will enter the power-saving mode, and wait for being woken up. When the central processor 10 transmits messages to at least one module 20 in the power-saving mode, the central processor 10 must wake up at least one module 20 to transmit the command messages 41 and the first data messages 42. Thus, the central processor 10 sends the first output signal according to the fourth potential level via the first pin 11, and sends the first output signal according to the fourth potential level via the second pin 12, so that the first output signals are combined into the first status messages 45 which represents to wake up at least one module 20.
Referring back to FIGS. 2, 3, and 4, the command messages 41 and the first data messages 42 are provided with at least one first debugging unit 43 therein, respectively. At least one first debugging unit 43 is used to allow at least one module 20 to receive the corresponding command message 41 and the corresponding first data message 42 while detecting/checking if any fault exists in the command message 41 and the first data message 42. Therefore, when the module 20 determines that a fault exists in the first data message 42, the module 20 sends the second output signal according to the fourth potential level via the third pin 21, and sends the second output signal according to the first potential level via the fourth pin 22, so that the second output signals are combined into the second status messages 52 which represents that a fault exists in the first data messages 42 determined and received by the module 20. Contrarily, the second data messages 51 are provided with at least one second debugging unit 53 therein, respectively. At least one second debugging unit 53 is used to allow the central processor 10 to receive the corresponding second data message 51 while detecting/checking if any fault exists in the second data message 51. Therefore, when the central processor 10 determines that a fault exists in the second data message 51, the central processor 10 sends the first output signal according to the first potential level via the first pin 11, and sends the first output signal according to the fourth potential level via the second pin 12, so that the first output signals are combined into the first status messages 45 which represents that a fault exists in the second data messages 51 determined and received by the central processor 10.
Referring back to FIGS. 2, 3, and 4, in the preferred embodiment of the present invention, the first output signal sent by the first and second pins 11, 12 of the central processor 10 and the second output signal sent by the third and fourth pins 21, 22 of the module 20 are the first potential levels and the fourth potential levels having potential variations, respectively to generate four combinations as described below. If the first potential level is set on a low voltage status, it defines a code “zero (0)”. If the fourth potential level is set on a high voltage status, it defines a code “one (1)”. Therefore, the present invention defines a code table according to the four combinations, as shown in FIG. 5, so that the central processor 10 and the module 20 can transmit the first status messages 45 and the second status message 52 and communicate with each other.
Referring back to FIGS. 2, 3, and 4, an interface transmission method between modules according to one preferred embodiment of the present invention comprises the following steps of: installing a central processor 10 and at least one module 20 in an electronic device 1, wherein the central processor 10 has a first pin 11 and a second pin 12 therein respectively coupled to a third pin 21 and a fourth pin 22 of at least one module 20 by using LVDS technology; receiving different voltage amplitudes and respectively outputting a corresponding first output signal according to a plurality of different potential levels by the central processor 10; combining the first output signal thereof into a plurality of command messages 41, first data messages 42, and first status messages 45; receiving the different voltage amplitudes and respectively outputting a corresponding second output signal according to the different potential levels by at least one module at least one module 20; combining the second output signal thereof into a plurality of second data messages 51 and second status messages 52; when the central processor 10 decides to transmit one of the first data messages 42 to one of at least one module 20, there are several steps described more detailed as the following and shown in FIG. 6:
In step 101, the central processor 10 determines if the module 20 is set on a power-saving mode. If yes, go to step 102; if not, go to step 104;
In step 102, the central processor 10 sends a first status message 45 to the module 20 for waking up the module 20;
In step 103, the module 20 is woken up, and starts to wait for receiving a command message 41;
In step 104, the central processor 10 sends the command message 41 to the module 20 for transmitting the first data message 42 to the module 20;
In step 105, the module 20 receives command message 41, and starts to receive the first data message 42 from the central processor 10;
In step 106, the central processor 10 starts to transmit the first data message 42 to the module 20;
In step 107, the module 20 determines if the first data message 42 transmitted between the central processor 10 and the module 20 is received. If there was no fault go to step 108, otherwise go to step 105;
In step 108, the central processor 10 sends a first status message 45 of the power-saving mode to the module 20 while the module 20 sends a second status message 52 of the power-saving mode to the central processor 10; and
In step 109, the central processor 10 and the module 20 are switched into the power-saving mode.
When the central processor 10 decides to receive one of the second data messages 51 from at least one module 20, there are several steps described more detailed as the following and shown in FIG. 7:
In step 201, the central processor 10 determines if the module 20 is set on a power-saving mode. If yes, go to step 202; if not, go to step 204;
In step 202, the central processor 10 sends a first status message 45 to the module 20 for waking up the module 20;
In step 203, the module 20 is woken up, and starts to wait for receiving a command message 41;
In step 204, the central processor 10 sends the command message 41 to the module 20 for receiving the second data message 51 from the module 20;
In step 205, the module 20 receives the command message 41, and starts to transmit the second data message 51 to the central processor 10;
In step 206, the central processor 10 starts to receive the second data message 51 from the module 20;
In step 207, the central processor 10 determines if the second data message 51 transmitted between the module 20 and the central processor 10 is received and finished without any fault. If yes, go to step 208; if not, go to step 205;
In step 208, the central processor 10 sends a first status message 45 of the power-saving mode to the module 20 while the module 20 sends a second status message 52 of the power-saving mode to the central processor 10; and
In step 209, the central processor 10 and the module 20 are switched into power-saving mode.
Furthermore, the command messages 41 and the first data messages 42 are provided with at least one first debugging unit 43 therein for checking faults. Referring back to FIGS. 2, 3, and 4, at least one first debugging unit 43 is used to determine if any fault exists in the command messages 41 and the first data messages 42. When the module 20 determines if the transmission of the command messages 41 and the first data messages 42 between the central processor 10 and the module 20 has no fault, there are several steps described more detailed as the following and shown in FIG. 8:
In step 301, the module 20 determines if any fault exists in the received command message 41 and the received first data message 42 via at least one first debugging unit 43. If yes, go to step 302; if not, go to step 303;
In step 302, the module 20 sends a second status message 52 which represents that a fault exists in the first output signal determined and received by the module 20;
In step 303, the module 20 determines if the central processor 10 finishes outputting the command message 41 and the first data message 42. If yes, go to step 304; if not, go to step 305;
In step 304, the central processor 10 sends a first status message 45 of the power-saving mode to the module 20 while the module 20 sends a second status message 52 of the power-saving mode to the central processor 10; and
In step 305, the module 20 keeps receiving the first data message 42 from the central processor 10.
Additionally, the second data messages 51 are provided with at least one second debugging unit 53 therein for checking faults. Referring back to FIGS. 2, 3, and 4, at least one second debugging unit 53 is used to determine if any fault exists in the second data messages 51. When the central processor 10 determines if the transmission of the second data message 51 between the central processor 10 and the module 20 doesn't have any fault, there are several steps described more detailed as the following and shown in FIG. 9:
In step 401, the central processor 10 determines if any fault exists in the received second data message 51 via at least one second debugging unit 53. If yes, go to step 402; if not, go to step 403;
In step 402, the central processor 10 sends a first status message 45 to the module 20, the first status message 45 represents that a fault exists in the second output signal determined and received by the central processor 10;
In step 403, the central processor 10 determines if the module 20 finished transmitting the second data message 51. If yes, go to step 404, otherwise go to step 405;
In step 404, the central processor 10 sends a first status message 45 of the power-saving mode to the module 20 while the module 20 sends a second status message 52 of the power-saving mode to the central processor 10; and
In step 405, the central processor 10 keeps receiving the second data message 51 from the module 20.
Referring still to FIGS. 2, 3, and 4, in one preferred embodiment of the present invention, the central processor 10 (or the module 20) outputs the first output signal (or the second output signal) according to a first potential level, a second potential level, a third potential level, or a fourth potential level via the first pin 11 (or the third pin 21) and the second pin 12 (or the fourth pin 22). Meanwhile, the central processor 10 respectively sends the corresponding first output signal to the module 20 according to variation of the second potential level and the third potential level via the first pin 11 and the second pin 12 so that the corresponding first output signal can be combined into the command messages 41 and the first data messages 42, as shown in FIGS. 3 and 5. Similarly, the module 20 respectively sends the corresponding second output signal to the central processor 10 according to variation of the second potential level and the third potential level via the third pin 21 and the fourth pin 22 so that the corresponding second output signal can be combined into the second data messages 51, as shown in FIGS. 4 and 5.
Moreover, the central processor 10 (or the module 20) respectively sends the corresponding first output signal (or the corresponding second output signal) according to the first potential level and the fourth potential level via the first pin 11 (or the third pin 21) and the second pin 12 (or the fourth pin 22) so that the corresponding first output signal (or the corresponding second output signal) can be combined into the first status messages 45 (or the second status messages 52), as shown in FIGS. 3, 4, and 5. Referring to FIG. 10a, when the central processor 10 wants to send a first status message 45 to the module 20 for waking up the module 20, the central processor 10 respectively sends two of the first output signals to the module 20 according to the fourth potential level via the first pin 11 and the second pin 12. After this, the module 20 receives the two first output signals, and is woken up.
Referring to FIG. 10c, when the central processor 10 wants to send a first status message 45, which represents that a fault exists in the second data messages 51 determined and received by the central processor 10, to the module 20, the central processor 10 respectively sends two of the first output signals to the module 20 according to the first potential level and the fourth potential level via the first pin 11 and the second pin 12. After the module 20 receives the two first output signals, the module 20 re-transmits the second data message 51 to the central processor 10.
Referring to FIG. 10b, when the central processor 10 wants to send a first status message 45, which represents to enter the power-saving mode, to the module 20, the central processor 10 respectively sends two of the first output signals to the module 20 according to the first potential level via the first pin 11 and the second pin 12, so that the module 20 receives the first status message 45 which represents that the central processor 10 entered the power-saving status. In another aspect, referring to FIG. 10d, when the module 20 wants to send a second status message 52, which represents to enter the power-saving mode, to the central processor 10, the module 20 respectively sends two of the second output signals to the central processor 10 according to the first potential level via the third pin 21 and the fourth pin 22, so that the central processor 10 receives the second status message 52 which represents that the module 20 entered the power-saving status.
Furthermore, when the module 20 wants to send a second status message 52, which represents that a fault exists in the first data messages 42 determined and received by the module 20, to the central processor 10, the module 20 respectively sends two of the second output signals to the central processor 10 according to the fourth potential level and the first potential level via the third pin 21 and the fourth pin 22. After the central processor 10 receives the two second output signals, the central processor 10 re-transmits the first data message 42 to the module 20.
The present invention has been described with a preferred embodiment thereof and it is understood that many changes and modifications to the described embodiment can be carried out without departing from the scope and the spirit of the invention that is intended to be limited only by the appended claims.
Patent Application
20070260789
