Patent Application
20090019184
Electronic data processing systems, such as computer systems, typically include one or more memory devices for storing data. Memory interface circuits are typically employed to interface between a plurality of memory devices.
One embodiment provides an integrated circuit containing a memory interface circuit. The memory interface circuit includes a first interface channel configured to couple to at least one memory device and a second interface channel configured to couple to at least one memory device. The memory interface circuit includes a multiplexer configured to select between the first interface channel and the second interface channel.
The accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and together with the description serve to explain principles of embodiments. Other embodiments and many of the intended advantages of embodiments will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise.
It is to be understood that in the following detailed description any shown or described direct connection or coupling between two functional blocks, devices, components, or other physical or functional units could also be implemented by indirect connection or coupling.
In the following, embodiments are described with reference to the accompanying drawings. Embodiments relate to a method of interfacing a plurality of memory devices in a data processing system, a corresponding memory interface circuit, a corresponding memory buffer device, a corresponding memory controller, and a corresponding processor. The interfaced memory devices embodiments may be integrated circuits comprising one or more memory arrays. Integrated circuits comprising one or more memory arrays may implement present or future standards, including double data rate (DDR), DDR2, DDR3, etc. The memory devices may be dynamic random access memory (DRAM) type or DRAM chips. However, it is to be understood that the concepts described hereinafter could also be applied to other types of memory devices.
Each of the memory modules comprises a plurality of memory devices 110 (e.g., DRAM chips). The memory devices 110 of a memory module 100a, 100b, 100c, and 100d are coupled to the memory controller 200 via a memory buffer device 150 of the memory module. The memory buffer device 150 communicates with the memory controller 200 via a controller interface coupled to the high-speed interface of the memory controller 200 and communicates with the memory devices 110 of the memory module via a memory interface. The memory buffer device 150 may be configured to communicate with a further memory buffer device so as to connect a plurality of memory modules 100a, 100b, 100c, and 100d in a chain configuration. The memory buffer device may be implemented in an integrated circuit.
According to an embodiment, the memory modules 100a, 100b, 100c, and 100d may correspond to a dual inline memory module (DIMM) type. More specifically, the memory modules 100a, 100b, 100c, and 100d may each correspond to a fully-buffered DIMM (FB-DIMM) and the memory buffer device 150 may correspond to an advanced memory buffer (AMB). In other embodiments, other types of memory modules may be used.
According to an embodiment, the processor 250, the memory controller 200, each of the memory devices 110, and the memory buffer device 150 are each implemented on a corresponding semiconductor chip. Accordingly, the memory devices may also be referred to as memory integrated circuits. Also the processor, the memory controller, and the memory buffer device may be formed in a corresponding integrated circuit. The memory modules 100a, 100b, 100c, and 100d are formed by arranging a plurality of the memory devices 110 and the memory buffer device 150 on a printed circuit board. On the printed circuit board, a plurality of connection pins are formed to couple the memory module 100a, 100b, 100c, and 100d to the memory controller 200. In other embodiments, at least some of the above functions could be integrated on a single chip. For example, the processor and the memory controller could be integrated on a single chip.
Referring to
The CA-blocks 160 are employed for the transfer of command and address data. According to an embodiment, buffers are included in the CA-blocks 160 for transferring command signals, clock signals, and address signals to the connected memory devices 110.
The DQ8-blocks are each provided with a number of data transceivers for transferring data path or DQ signals via the memory interface and a number of transceivers for transferring data strobe signals, herein referred to as DQS/DQS# signals, via the memory interface. The memory interface of the illustrated embodiment is a bidirectional type with respect to the direction of data flow to and from a given memory device. In other embodiments the memory interface may be of a unidirectional type and different memory interfaces may be used for the different directions of data flow.
According to an embodiment, a plurality of memory devices 110 or multiple ranks of memories may be connected to a single DQ8-block 170. A multi-rank configuration may have multiple ranks of memories on a single memory module or on different memory modules. In such a multi-rank configuration embodiment, the connected components may not be used at the same time and the interface has to be scheduled in a way that there is no bus contention when switching from one to the other rank. The number of ranks is limited by the maximum tolerable capacitive load on the memory interface. An excessive capacitive load may be compensated by decreasing the speed of the memory interface.
Now referring to
The write section comprises a write buffer 171, such as write first-in first-out (W-FIFO), and a control logic 172. The write buffer 171 receives write data WD from the core logic (not illustrated in
Operation of a memory interface according to one embodiment is as follows. In an example write operation, the transmitters are controlled to send the write data stored in the write buffer 171 to the connected memory devices 110 via the transmitters TX. The transmitters TX drive the corresponding DQ signals and DQS/DQS# signals to the connected memory devices 110. In this operation, the core logic enables the transmitters at the right point of time, enables the correct memory rank, and properly skews the DQ signals and DQS/DQS# signals using the delay lines 174.
In an example read operation, the core logic enables the receivers RX at the right point in time, captures the read data in the read buffer 181, and sets the skewing of the DQS/DQS# signal with respect to the DQ signals via the delay line 184.
In the example embodiment of
As further illustrated in
In the read section, the switch 185 is coupled between the read buffer 181 and the first and second receivers RX for the DQ signals. In this way, either the interface terminals corresponding to the first group of DQ signals or the interface terminals corresponding to the second group of DQ signals can be selectively coupled to the read buffer 181. The switch 186 is coupled between the control terminal of the read buffer 181 and the third and fourth receivers RX for the DQS/DQS# signals. In this way, either the interface terminals corresponding to the first group of DQS/DQS# signals or the interface terminals corresponding to the second group of DQS/DQS# signals can be selectively coupled to the read buffer 181.
The multiplexer device (i.e., the switches 175, 176, 185, 186) is controlled by a channel select signal. In particular, the switches 175, 176 are controlled by a write channel select signal WCS, and the switches 185, 186 are controlled by a read channel select signal RCS. The first group of DQ signals and the first group of DQS/DQS# signals form a first interface channel, and the second group of DQ signals and the second group of DQS/DQS# signals form a second interface channel. The first interface channel and the second interface channel form physically distinct signal connections. The first interface channel and the second interface channel are typically formed with a substantially identical configuration, but different configurations are possible.
Accordingly, in the memory interface circuit, the DQ signals and the DQS/DQS# signals are internally multiplexed so as to widen the memory interface.
The memory interface includes a first interface channel comprising the first group of DQ signals and the first group of DQS/DQS# signals and a second interface channel comprising the second group of DQ signals and the second group of DQS/DQS# signals. As illustrated, each of the interface channels is connected to a corresponding group of interface terminals. From the outside of the device, the first interface channel and the second interface channel appear as independent memory interfaces.
In the example embodiment of
The above exemplary embodiment structure of the memory interface allows for increasing the width of the memory interface in a very efficient manner. In one embodiment, the number of connected memory devices may be increased without decreasing the data transfer rate via the memory interface. In one embodiment, only a limited number of interface components needs to be increased to achieve the increased interface width. This embodiment provides advantages with respect to power consumption and chip area requirements. Further, the timing of write and read operations may be improved. As compared to writing different memory ranks connected to a single interface channel, when performing write operations via different interface channels which are multiplexed as according to above described embodiments, it is no longer required to wait for a write command on one interface channel to be entirely finished before starting a write operation on the other interface channel. Rather, the change between one interface channel and the other interface channel can already start right after the last data transfer of the first write operation has been completed, which is the first point in time when the switches 175, 176 can be changed. For example, a preamble of the second write operation could already be transmitted on the second interface channel while on the first interface channel there is still traffic pertaining to the first write operation.
Similar advantages exist in example read operations according to embodiments. If there is a read operation on one memory channel, the read data of a read operation on the other memory channel can arrive significantly earlier than in the case of multiple memory devices connected via a single interface channel.
Further, according to embodiments it is possible that a read operation on one interface channel and a write operation on the other interface channel are carried out at the same time.
As compared to a memory interface without multiplexing of interface channels, the number of transmitters or receivers which are active at the same time is typically not increased for a given memory size. Accordingly, the width of the memory interface described may be increased in a very power-efficient manner according to embodiments.
In the above described embodiments, the memory buffer device 150 communicates with the memory controller 200 via the high-speed interface. According to other embodiments, the memory buffer device may communicate with other components which are located external with respect to the memory module.
According to an embodiment illustrated in
As compared to the data processing system of
In the foregoing, the memory interface was described to be implemented within the memory buffer device 150 of the memory modules 100a, 100b and 100c, 100d. In other embodiments, the memory interface may be implemented within other components of a data processing system so as to accomplish interfacing of memory devices.
In the data processing system embodiment of
Accordingly, the above described embodiments of a memory interface can be applied to a variety of electronic components. In particular, memory interface embodiments may be used within a memory buffer device of a memory module, within a memory controller, which may be implemented in a separate chip on a main board of a data processing system, or in a processor. Memory interface embodiments may also be used in an integrated circuit implementing functions of a larger system on a single chip. Such an integrated circuit embodiment could comprise an embedded processor and an embedded memory. However, memory interface embodiments are not limited to these applications and may be used in other components as well.
Further, the above described embodiments of a memory interface are configured to accomplish both write operations and read operations via two interface channels which are internally multiplexed within the circuit structure of the memory interface. In other embodiments, a larger number of interface channels may be used. Further, the above-described concepts may also be applied in a memory interface embodiments which is dedicated to read operations only or to write operations only. It is also possible to implement a memory interface embodiment in which the write section has multiplexed interface channels and the read section has a single interface channel or a memory interface in which the read section has multiplexed interface channels and the write section has a single interface channel. Further, multiplexing between the first interface channel and the second interface channel could also be implemented only for the data path signals or only for the data strobe signals.
Further, the above concepts may be applied in connection with a variety of memory devices, the above-mentioned DRAM devices being only one example thereof. Further, the above described embodiments could also be combined with each other, for example in a data processing system which comprises memory modules of both buffered type and unbuffered type.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
