INTERGRATING RECEIVER HAVING ADAPTIVE FEEDBACK EQUALIZER FUNCTION TO SIMULTANEOUSLY REMOVE INTER-SYMBOL INTERFERENCE AND HIGH FREQUENCY NOISES AND SYSTEM HAVING THE SAME

Abstract

Provided is an integrating receiver having an adaptive decision feedback equalizer function and a system having the same. The integrating receiver can simultaneously remove an inter-symbol interference (ISI) and high frequency noises in a high speed DRAM data transmission system. The integrating receiver reduces a probability of wrong decision of data in a state in which the ISI that exists in a channel is removed so as to increase a signal-to-noise ratio (SNR) of a receiver, so that a maximum operation speed increases even in an environment with heavy noises. There is also provided a method of obtaining an equalizer coefficient suitable for the integrating receiver and a method of obtaining a reference voltage by using an integrator in a single ended transmission method. In addition, in order to increase a decision feedback equalizer speed, a look-ahead method is used. In this method, flip flops with a high speed including multiplexers are used. Accordingly, the present invention can be applied to not only a DRAM interface system but also a serial communication between chips.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

FIG. 1 is a view for explaining a conventional multi drop channel method;

FIG. 2 is a view showing signal response characteristics in a multi drop channel method;

FIG. 3 is a view for explaining a decision feedback equalizer (DFE) that is used in a receiving terminal equalizer method;

FIG. 4 is a view for explaining a conventional integrating receiver circuit;

FIG. 5 is a block diagram of an integrating receiver circuit according to a first embodiment of the present invention;

FIG. 6 is a view for explaining a method of determining an equalizer coefficient applied to the integrating receiver circuit in FIG. 5;

FIG. 7 is a view showing a method of obtaining an error signal e[n] applied to the integrating receiver circuit in FIG. 5;

FIG. 8 is a circuit diagram for explaining an integrating receiver system having an adaptive DEF function according to a second embodiment of the present invention;

FIG. 9 is a view for explaining an entire circuit diagram of a receiver circuit according to a third embodiment of the present invention;

FIG. 10 is a circuit diagram showing a reference voltage generator in FIG. 9;

FIG. 11 is a view for explaining operations of the reference voltage generator in FIG. 10;

FIG. 12 is a view for explaining a decision feedback equalizing receiver having an integration function according to a fourth embodiment of the present invention;

FIG. 13 is a view showing an operation timing diagram of a receiver in FIG. 12;

FIG. 14 is a circuit diagram for explaining a 2-tap DFE integrator according to a fifth embodiment of the present invention;

FIG. 15 is a circuit diagram for explaining a comparator having a multiplexing function according to a sixth embodiment of the present invention;

FIG. 16 is a timing diagram for explaining operations of the comparator in FIG. 15 in relation to the operation timing diagram of the receiver in FIG. 12; and

FIG. 17 is a view showing a result of a simulation in the receiver in FIG. 12.

Claims

1. An integrating receiver comprising: a DFE (decision feedback equalizer); andan integrator performing an integration on an output of the DFE during a period to provide the integrated output to the DFE,wherein an ISI (inter-symbol interference) of a waveform equalized by the DFE is removed by using data values decided before a period and before two periods.

2. The integrating receiver of claim 1, wherein the DFE comprises: an adder which receives an input signal input to the integrating receiver and the data values from a feedback filter and add them to generate an output signal;a decider comparing an output voltage of the integrator with a predetermined reference voltage and producing a compared data; andthe feedback filter for multiplying the compared data decided before a period and before two periods by first and second equalizer coefficients, respectively, to generating the data values.

3. The integrating receiver of claim 2, wherein the first equalizer coefficient is an average value of ISI values between 1.5 T and 2.5 T,wherein the second equalizer coefficient is an average value of the ISI values between 2.5 T and 3.5 T, andwherein the T is a width of an input pulse input to the integrating receiver.

4. The integrating receiver of claim 2, wherein the integrating receiver represents an energy difference between the output signals of the DFE when a pattern of the input signal is 1111 and X011 as an error signal, and when a value of the error signal is 0, determines a1 by using a sign least mean-squared (LMS) error algorithm when the input signal is 1011, and determines a2 when the input signal is 0011.

5. An integrating receiver system comprising: an integrating receiver integrating input signal during a period and removing an ISI of the input signal by using data values decided before a period and before two period;an error detector generating an error signal decided by energy difference between output signal from the integrating receiver; andan LMS controller obtaining an equalizer coefficient of the integrating receiver based on the error signal and the data values the integrating receiver.

6. The integrating receiver system of claim 5, wherein the integrating receiver comprises: an adder receives the input signal and data values from a feedback filter and adds them;an integrator performing an integration on the output of the adder during a period;a decider comparing an output voltage of the integrator with a predetermined reference voltage to decide the compared voltage; andthe feedback filter delays the output signal of the decider 2 periods and multiplying the data values from the LMS controller to the one period delayed signal and two periods delayed signal, respectively, and adds the multiplied signals.

7. The integrating receiver system of claim 6, wherein, when the error signal has a value of 0, the error detector determines a1 by using a sign-sign LMS algorithm when the input signal is 1011, and determines a2 when the input signal is 0011.

8. The integrating receiver system of claim 6, wherein the integrating receiver system further comprises a reference voltage generator which receives a clock as an input signal in an initial system setting mode and generates a reference voltage having an intermediate voltage of the input signal.

9. The integrating receiver system of claim 8, wherein the reference voltage generator comprises: an integrator integrating the clock that is the input signal;a comparator comparing an output of the integrator with the reference voltage;an up/down counter controlling a value obtained by integrating the clock to have a value of 0 according to the decided value of the comparator;a digital-analog converter converting a digital output value of the up/down counter into a current value; anda resistance with which the current value of the digital-analog converter is applied generates the reference voltage.

10. A receiver comprising: DFEs having a look-ahead integration function; andflip-flops connected to the DFEs, respectively,wherein each of the DFEs having the integration function receives an input signal during a ¼ time of a data frequency and receives data values decided before a period and before two period, andwherein each of the DFEs comprises:a first DFE integrator that is operated when the data value decided before a period is 0;a second DFE integrator that is operated when the data value decided before a period is 1; anda comparator that selects one from outputs of the first and second DFE integrators according to the data value decided before a period.

11. The receiver of claim 10, wherein each of the first and second DFE integrators comprises: a precharge unit for precharging outputs of the first and second DFE integrators as a power source voltage in response to a first clock signal;a capacitor connected to the outputs of the first and second DFE integrators; anda differential comparator which integrates input signals during a ¼ time of the data frequency in response to a second clock signal according to the values decided before a period and before two periods and stores them in the capacitor.

12. The receiver of claim 10, wherein the comparator comprises: 2-to-1 multiplex with a differential type for selecting one from the outputs of the first and second DFE integrators in response to the selected signal;a flip flop for fine amplifying the output of the multiplex; andan inverter connected to the output of the flip flop.