Patent Application
20190313413
The present disclosure is generally related to mobile communications and, more particularly, to interlace design for New Radio (NR) unlicensed spectrum (NR-U) operation.
Unless otherwise indicated herein, approaches described in this section are not prior art to the claims listed below and are not admitted as prior art by inclusion in this section.
For an NR communication system operating at 5 GHz unlicensed band, the European Telecommunications Standards Institute (ETSI) regulation requires a maximum power spectral density (PSD) level of 10 dbm/MHz and an occupied channel bandwidth (OCB) of at least 80% (and up to 100%) of the nominal channel bandwidth. In Long-Term Evolution (LTE) enhanced Licensed Assisted Access (eLAA), block interlaced frequency-division multiple access (B-IFDMA) is introduced for uplink (UL) transmission in order to comply with the ETSI requirements for both OCB and maximum PSD level, while at the same time maintaining a transmit (TX) signal power level that can support a desired cell coverage.
The following summary is illustrative only and is not intended to be limiting in any way. That is, the following summary is provided to introduce concepts, highlights, benefits and advantages of the novel and non-obvious techniques described herein. Select implementations are further described below in the detailed description. Thus, the following summary is not intended to identify essential features of the claimed subject matter, nor is it intended for use in determining the scope of the claimed subject matter.
In one aspect, a method may involve a processor of an apparatus assigning a plurality of resources to a plurality of interlaces such that, when the plurality of resources cannot be evenly distributed among all the plurality of interlaces, one or more remaining resources of the plurality of resources are assigned to one or more interlaces of the plurality of interlaces. The method may also involve the processor performing an UL transmission to a wireless network in an NR-U using the plurality of resources with B-IFDMA.
In one aspect, an apparatus may include a transceiver and a processor coupled to the transceiver. During operation, the transceiver may wirelessly communicate with a wireless network. During operation, the processor may perform operations including: (a) assigning a plurality of resources to a plurality of interlaces such that, when the plurality of resources cannot be evenly distributed among all the plurality of interlaces, one or more remaining resources of the plurality of resources are assigned to one or more interlaces of the plurality of interlaces; and (b) performing, via the transceiver, an UL transmission to the wireless network in an NR-U using the plurality of resources with B-IFDMA.
It is noteworthy that, although description provided herein may be in the context of certain radio access technologies, networks and network topologies such as 5G NR, the proposed concepts, schemes and any variation(s)/derivative(s) thereof may be implemented in, for and by other types of radio access technologies, networks and network topologies such as, for example and without limitation, Long-Term Evolution (LTE), LTE-Advanced, LTE-Advanced Pro, and Internet-of-Things (IoT). Thus, the scope of the present disclosure is not limited to the examples described herein.
The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of the present disclosure. The drawings illustrate implementations of the disclosure and, together with the description, serve to explain the principles of the disclosure. It is appreciable that the drawings are not necessarily in scale as some components may be shown to be out of proportion than the size in actual implementation to clearly illustrate the concept of the present disclosure.
Detailed embodiments and implementations of the claimed subject matters are disclosed herein. However, it shall be understood that the disclosed embodiments and implementations are merely illustrative of the claimed subject matters which may be embodied in various forms. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments and implementations set forth herein. Rather, these exemplary embodiments and implementations are provided so that description of the present disclosure is thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art. In the description below, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments and implementations.
Referring to part (B) of
Mathematically, B-IFDMA mapping under the current eLAA B-IFDMA design can be expressed as follows:
S(n)={M(Nl+n)+m|0≤m<M, 0≤l<floor(NRB/N)}
Under a proposed scheme in accordance with the present disclosure, a new B-IFDMA mapping may be utilized such that all available RBs may be used to construct interlaces. Moreover, under the proposed scheme, it may be guaranteed that each interlace would meet the OCB requirements. Referring to part (C) of
Mathematically, B-IFDMA mapping under the proposed scheme may be expressed as follows:
s
1(n)={M(Nl+n)+m|0≤m<M, 0≤l≤(NRB−n−1)/N}
Under the proposed scheme, B-IFDMA design criteria for compliance with the OCB requirement may be expressed as follows:
Here, Δf denotes subcarrier spacing, and B denotes a nominal channel bandwidth. Under the proposed scheme, in view of the OCB requirement, Bo needs to be greater than γ(e.g., γ=0.8, with γ representative of OCB).
Under the proposed scheme, there may be some design criteria for N. For instance, the value of M may be chosen first (e.g., M=12 for RB-based interlace design) and Bo(N) may be plotted for N=1 to (12×NRB/M), then the maximum value of N may be determined such that Bo(N)>γ.
Under the proposed scheme, there may be some design criteria for M. For instance, the value of N may be chosen first (e.g., N=10 for ten interlaces) and Bo(M) may be plotted for M in a range of interest, then the maximum value of M may be determined such that Bo(M)>γ.
Thus, under the proposed scheme, with respect to resource mapping in B-IFDMA design, remaining resources may be assigned to a subset of all interlaces via a predefined or dynamic configuration when available resources cannot be evenly distributed among all interlaces. With respect to the design criteria for OCB compliance, a close form formula may be provided for OCB computation. Additionally, based on the formula, OCB may be evaluated as a function of various design parameters so as to select proper values for the design parameters to satisfy the OCB requirement.
Each of apparatus 210 and apparatus 220 may be a part of an electronic apparatus, which may be a network apparatus or a UE (e.g., UE 110), such as a portable or mobile apparatus, a wearable apparatus, a wireless communication apparatus or a computing apparatus. For instance, each of apparatus 210 and apparatus 220 may be implemented in a smartphone, a smart watch, a personal digital assistant, a digital camera, or a computing equipment such as a tablet computer, a laptop computer or a notebook computer. Each of apparatus 210 and apparatus 220 may also be a part of a machine type apparatus, which may be an IoT apparatus such as an immobile or a stationary apparatus, a home apparatus, a wire communication apparatus or a computing apparatus. For instance, each of apparatus 210 and apparatus 220 may be implemented in a smart thermostat, a smart fridge, a smart door lock, a wireless speaker or a home control center. When implemented in or as a network apparatus, apparatus 210 and/or apparatus 220 may be implemented in a base station (e.g., base station 125), such as an eNB in an LTE, LTE-Advanced or LTE-Advanced Pro network or in a gNB or TRP in a 5G network, an NR network or an IoT network.
In some implementations, each of apparatus 210 and apparatus 220 may be implemented in the form of one or more integrated-circuit (IC) chips such as, for example and without limitation, one or more single-core processors, one or more multi-core processors, or one or more complex-instruction-set-computing (CISC) processors. In the various schemes described above, each of apparatus 210 and apparatus 220 may be implemented in or as a network apparatus or a UE. Each of apparatus 210 and apparatus 220 may include at least some of those components shown in
In one aspect, each of processor 212 and processor 222 may be implemented in the form of one or more single-core processors, one or more multi-core processors, or one or more CISC processors. That is, even though a singular term “a processor” is used herein to refer to processor 212 and processor 222, each of processor 212 and processor 222 may include multiple processors in some implementations and a single processor in other implementations in accordance with the present disclosure. In another aspect, each of processor 212 and processor 222 may be implemented in the form of hardware (and, optionally, firmware) with electronic components including, for example and without limitation, one or more transistors, one or more diodes, one or more capacitors, one or more resistors, one or more inductors, one or more memristors and/or one or more varactors that are configured and arranged to achieve specific purposes in accordance with the present disclosure. In other words, in at least some implementations, each of processor 212 and processor 222 is a special-purpose machine specifically designed, arranged and configured to perform specific tasks including those pertaining to interlace design for NR-U operation in accordance with various implementations of the present disclosure.
In some implementations, apparatus 210 may also include a transceiver 216 coupled to processor 212. Transceiver 216 may be capable of wirelessly transmitting and receiving data. In some implementations, apparatus 220 may also include a transceiver 226 coupled to processor 222. Transceiver 226 may include a transceiver capable of wirelessly transmitting and receiving data.
In some implementations, apparatus 210 may further include a memory 214 coupled to processor 212 and capable of being accessed by processor 212 and storing data therein. In some implementations, apparatus 220 may further include a memory 224 coupled to processor 222 and capable of being accessed by processor 222 and storing data therein. Each of memory 214 and memory 224 may include a type of random-access memory (RAM) such as dynamic RAM (DRAM), static RAM (SRAM), thyristor RAM (T-RAM) and/or zero-capacitor RAM (Z-RAM). Alternatively, or additionally, each of memory 214 and memory 224 may include a type of read-only memory (ROM) such as mask ROM, programmable ROM (PROM), erasable programmable ROM (EPROM) and/or electrically erasable programmable ROM (EEPROM). Alternatively, or additionally, each of memory 214 and memory 224 may include a type of non-volatile random-access memory (NVRAM) such as flash memory, solid-state memory, ferroelectric RAM (FeRAM), magnetoresistive RAM (MRAM) and/or phase-change memory.
Each of apparatus 210 and apparatus 220 may be a communication entity capable of communicating with each other using various proposed schemes in accordance with the present disclosure. For illustrative purposes and without limitation, a description of capabilities of apparatus 210, as a UE, and apparatus 220, as a base station of a serving cell of a wireless network (e.g., 5G/NR mobile network), is provided below. It is noteworthy that, although the example implementations described below are provided in the context of a UE, the same may be implemented in and performed by a base station. Thus, although the following description of example implementations pertains to apparatus 210 as a UE (e.g., UE 110), the same is also applicable to apparatus 220 as a network node or base station such as a gNB, TRP or eNodeB (e.g., base station 125) of a wireless network (e.g., wireless network 120) such as a 5G NR mobile network.
Under a proposed scheme with respect to interlace design for NR-U operation in accordance with the present disclosure, processor 212 of apparatus 210 may assign a plurality of resources to a plurality of interlaces such that, when the plurality of resources cannot be evenly distributed among all the plurality of interlaces, one or more remaining resources of the plurality of resources are assigned to one or more interlaces of the plurality of interlaces. Moreover, processor 212 may perform, via transceiver 216, an UL transmission to a wireless network via apparatus 220 in an NR-U using the plurality of resources with B-IFDMA.
In some implementations, in assigning, processor 212 may assign according to a predefined configuration.
In some implementations, in assigning, processor 212 may perform some operations. For instance, processor 212 may dynamically receive a configuration from the wireless network via apparatus 220. Additionally, processor 212 may assign the plurality of resources to the plurality of interlaces according to the configuration received from the wireless network.
In some implementations, in assigning the plurality of resources to the plurality of interlaces, processor 212 may assign the plurality of resources to the plurality of interlaces to satisfy an occupied channel bandwidth (Bo) requirement such that:
Here, Δf may denote a subcarrier spacing, B may denote a nominal channel bandwidth, M may denote a number of subcarriers per block, N may denote a number of interlaces per symbol, and NRB may denote a total number of resource blocks (RBs) per symbol.
In some implementations, in assigning the plurality of resources to the plurality of interlaces, processor 212 may perform some operations. For instance, processor 212 may select a value for M. Additionally, processor 212 may plot Bo(N) for N=1 to (12×NRB/M). Moreover, processor 212 may determine a maximum value of N such that B0(N)>γ. In some implementations, γ=0.8.
In some implementations, in assigning the plurality of resources to the plurality of interlaces, processor 212 may perform some operations. For instance, processor 212 may select a value for N. Moreover, processor 212 may plot Bo(M) for M in a range of interest. Furthermore, processor 212 may determine a maximum value of M such that Bo(M)>γ. In some implementations, γ=0.8.
In some implementations, in performing the UL transmission to the wireless network in the NR-U, processor 212 may perform the UL transmission to the wireless network in the NR-U with an OCB of at least 80%.
In some implementations, in performing the UL transmission to the wireless network in the NR-U, processor 212 may perform the UL transmission to the wireless network in the NR-U with a maximum PSD level no more than 10 dbm/MHz.
At 310, process 300 may involve processor 212 of apparatus 210 assigning a plurality of resources to a plurality of interlaces such that, when the plurality of resources cannot be evenly distributed among all the plurality of interlaces, one or more remaining resources of the plurality of resources are assigned to one or more interlaces of the plurality of interlaces. Process 300 may proceed from 310 to 320.
At 320, process 300 may involve processor 212 performing, via transceiver 216, an UL transmission to a wireless network via apparatus 220 in an NR-U using the plurality of resources with B-IFDMA.
In some implementations, in assigning, process 300 may involve processor 212 assigning according to a predefined configuration.
In some implementations, in assigning, process 300 may involve processor 212 performing some operations. For instance, process 300 may involve processor 212 dynamically receiving a configuration from the wireless network via apparatus 220. Additionally, process 300 may involve processor 212 assigning the plurality of resources to the plurality of interlaces according to the configuration received from the wireless network.
In some implementations, in assigning the plurality of resources to the plurality of interlaces, process 300 may involve processor 212 assigning the plurality of resources to the plurality of interlaces to satisfy an occupied channel bandwidth (Bo) requirement such that:
Here, Δf may denote a subcarrier spacing, B may denote a nominal channel bandwidth, M may denote a number of subcarriers per block, N may denote a number of interlaces per symbol, and NRB may denote a total number of resource blocks (RBs) per symbol.
In some implementations, in assigning the plurality of resources to the plurality of interlaces, process 300 may involve processor 212 performing some operations. For instance, process 300 may involve processor 212 selecting a value for M. Additionally, process 300 may involve processor 212 plotting Bo(N) for N=1 to (12×NRB/M). Moreover, process 300 may involve processor 212 determining a maximum value of N such that Bo(N)>γ. In some implementations, γ=0.8.
In some implementations, in assigning the plurality of resources to the plurality of interlaces, process 300 may involve processor 212 performing some operations. For instance, process 300 may involve processor 212 selecting a value for N. Moreover, process 300 may involve processor 212 plotting Bo(M) for M in a range of interest. Furthermore, process 300 may involve processor 212 determining a maximum value of M such that Bo(M)>γ. In some implementations, γ=0.8.
In some implementations, in performing the UL transmission to the wireless network in the NR-U, process 300 may involve processor 212 performing the UL transmission to the wireless network in the NR-U with an OCB of at least 80%.
In some implementations, in performing the UL transmission to the wireless network in the NR-U, process 300 may involve processor 212 performing the UL transmission to the wireless network in the NR-U with a maximum PSD level no more than 10 dbm/MHz.
The herein-described subject matter sometimes illustrates different components contained within, or connected with, different other components. It is to be understood that such depicted architectures are merely examples, and that in fact many other architectures can be implemented which achieve the same functionality. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being “operably connected”, or “operably coupled”, to each other to achieve the desired functionality, and any two components capable of being so associated can also be viewed as being “operably couplable”, to each other to achieve the desired functionality. Specific examples of operably couplable include but are not limited to physically mateable and/or physically interacting components and/or wirelessly interactable and/or wirelessly interacting components and/or logically interacting and/or logically interactable components.
Further, with respect to the use of substantially any plural and/or singular terms herein, those having skill in the art can translate from the plural to the singular and/or from the singular to the plural as is appropriate to the context and/or application. The various singular/plural permutations may be expressly set forth herein for sake of clarity.
Moreover, it will be understood by those skilled in the art that, in general, terms used herein, and especially in the appended claims, e.g., bodies of the appended claims, are generally intended as “open” terms, e.g., the term “including” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “having at least,” the term “includes” should be interpreted as “includes but is not limited to,” etc. It will be further understood by those within the art that if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases “at least one” and “one or more” to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim recitation to implementations containing only one such recitation, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an,” e.g., “a” and/or “an” should be interpreted to mean “at least one” or “one or more;” the same holds true for the use of definite articles used to introduce claim recitations. In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number, e.g., the bare recitation of “two recitations,” without other modifiers, means at least two recitations, or two or more recitations. Furthermore, in those instances where a convention analogous to “at least one of A, B, and C, etc.” is used, in general such a construction is intended in the sense one having skill in the art would understand the convention, e.g., “a system having at least one of A, B, and C” would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc. In those instances where a convention analogous to “at least one of A, B, or C, etc.” is used, in general such a construction is intended in the sense one having skill in the art would understand the convention, e.g., “a system having at least one of A, B, or C” would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc. It will be further understood by those within the art that virtually any disjunctive word and/or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both terms. For example, the phrase “A or B” will be understood to include the possibilities of “A” or “B” or “A and B.”
From the foregoing, it will be appreciated that various implementations of the present disclosure have been described herein for purposes of illustration, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various implementations disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the following claims.
The present disclosure claims the priority benefit of U.S. Provisional Patent Application No. 62/654,282, filed on 6 Apr. 2018, the content of which is herein incorporated by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 62654282 | Apr 2018 | US |
