Internal power supply circuit

Abstract

An internal power supply circuit, comprising a plurality of charge accumulators, a first power supply terminal, a second power supply terminal, a first switch for connecting the plurality of charge accumulators in parallel to each other in a first state, and a second switch for connecting the plurality of charge accumulators in series with each other in a second state, the charge accumulators connected between the first power supply terminal and the second power supply terminal at either the first state or the second state, and the first state and the second state set repeatedly to raise or lower a voltage between the first power supply terminal and the second power supply terminal.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a power supply circuit. More particularly, the present invention relates to a booster circuit generating a voltage higher than an external power supply voltage by raising the voltage from the external power supply voltage or a down converter or other DC (direct current)-DC converter generating a voltage lower than the external power supply voltage by lowering the voltage from the external power supply voltage.

2. Description of the Related Art

In recent years, the practice in EEPROMs, flash memories, and other read only memories which can be electrically rewritten has been to supply only a single low power supply voltage from the outside, generate inside the chip an internal voltage higher than the voltage supplied from the outside, and write data into the memory by the high voltage inside the chip.

However, the voltage of the external power supply is being reduced as a general trend and the boosting efficiency decreases with the lower external voltage. Therefore, it has not been possible to generate an internal boosted voltage having a sufficient power.

On the other hand, the external power supply used is usually a 5 V single power supply, but it has become necessary to operate semiconductor devices at a lower internal voltage due to the desire to deal with the deterioration of the voltage resistance of semiconductor devices accompanying higher integration and the desire to reduce the power consumption.

However, the loss caused by the operation of a power supply circuit in the chip is large and obstructs the reduction of the power consumption.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a power supply circuit able to decrease the number of charge pumping circuits used for obtaining a desired high voltage by increasing the efficiency of raising or lowering the voltage and to give a stable output voltage with a low power loss.

According to one aspect of the present invention, there is provided an internal power supply circuit comprising a plurality of charge accumulating means, a first power supply terminal, a second power supply terminal, a first switching means for connecting the plurality of charge accumulating means in parallel to each other in a first state, and a second switching means for connecting the plurality of charge accumulating means in series with each other in a second state, and a control means for energizing the first switching means or the second switching means in response to the first state or the second state to connect the plurality of charge accumulating means between the first power supply terminal and the second power supply terminal, and for deenergizing the first switching means or the second switching means in response to the first state or the second state to disconnect the plurality of charge accumulating means between the first power supply terminal and the second power supply terminal, the control means repeating the energizing and the deenergizing.

Preferably, the charge accumulating means are constituted by capacitors. First switching means is constituted by a third switching means and a fourth switching means. A partial booster circuit is may include a capacitor connected between a first node and a second node, the third switching means connected between the first node and the first power supply terminal, and the fourth switching means connected between the second node and the second power supply terminal. A plurality of the partial booster circuits are provided. The second switching means holds in a non-conductive state the first node of a front partial booster circuit and the second node of a rear partial booster circuit as a first state and holds them in a conductive state as a second state. The first switching means (comprised of the third switching means and the fourth switching means) is held in the conductive state and the second switching means is held in a non-conductive state in the first state; and the first switching (means comprised of the third switching means and the fourth switching means) is held in the non-conductive state and the second switching means is held in a conductive state in the second state so as to raise the voltage between the first power supply terminal and the second power supply terminal.

The internal power supply circuit of the present invention further comprises: a biasing means connected to the second node of the initial stage partial booster circuit for holding the second node at a constant potential: and a rectifying means connected between the first node of the final stage partial booster circuit and a boosted voltage output terminal.

Preferably, the biasing means is constituted by a switching means set in the conductive state when the first switching means comprised of the third and fourth switching means is non-conductive.

Preferably, the first power supply terminal is a positive power supply terminal and the second power supply terminal is a negative power supply terminal, the constant potential is the potential of the first power supply terminal, the biasing means is a rectification element connected so that a direction from the first power supply toward the second node of the initial stage partial booster circuit becomes a forward direction, and the rectification element is connected so that a direction from the first node of the final stage partial booster circuit toward the output terminal becomes the forward direction and supplies the positive boosted voltage to the output terminal.

Alternatively, the first power supply terminal may be a negative power supply terminal and the second power supply terminal may be a positive power supply terminal, the constant potential is the potential of the second power supply terminal, the biasing means is a rectification element connected so that a direction from the second node of the first stage partial booster circuit toward the first power supply terminal becomes the forward direction, and the rectification element is connected so that a direction from the output terminal to the first node of the final stage partial booster circuit becomes the forward direction and supplies the negative boosted voltage to the output terminal.

Preferably, the third switching means is constituted by a first conductivity type insulation gate type field effect transistor with a gate electrode connected to an input terminal of a first clock, with one diffusion layer connected to the first power supply, and with another diffusion layer connected to the first node of the partial booster circuit. The fourth switching means is constituted by a first conductivity type insulation gate type field effect transistor with a gate electrode connected to an input terminal of a second clock, with one diffusion layer connected to the second power supply, and with another diffusion layer connected to the second node of the partial booster circuit. The second switching means is constituted by a second conductivity type insulation gate type field effect transistor with a gate electrode connected to the input terminal of a third clock.

Preferably, the biasing means is constituted by a second conductivity type insulation gate type field effect transistor with a gate electrode connected to the input terminal of a third clock.

Preferably, an amplitude of the first clock is set larger than a potential difference between the first power supply terminal and the second power supply terminal.

Preferably, the first power supply terminal is a positive power supply terminal and the first conductivity type insulation gate type field effect transistor is an n-channel type transistor and is held at a higher level than the first power supply terminal voltage in a high level section of the first clock.

Alternatively, the first power supply is a negative power supply terminal and the first conductivity type insulation gate type field effect transistor is a p-channel type transistor and is held at a lower level than the second power supply terminal voltage in a low level section of the first clock.

Preferably, the second conductivity type insulation gate type field effect transistor constituting the second switching means is formed in an independent well.

Preferably, the biasing means is a second conductivity type insulation gate type field effect transistor formed in the same well as that for the second conductivity type insulator gate type field effect transistors constituting part of the peripheral logic circuit.

According to a second aspect of the present invention, there is provided an internal power supply circuit comprising a first power supply terminal, a second power supply terminal, a first node, a second node, a capacitor connected between the first node and the second node, a first switching means connected between the first node and the first power supply terminal, a second switching means connected between the second node and the second power supply terminal, a biasing means connected to the second node and biasing the node at a constant potential, and a rectifying means connected between the first node and the boosted voltage output terminal, the first and second switching means being repeatedly set in the conductive state and the non-conductive state to be overlapped thereby to output a boosted voltage to an output terminal.

Preferably, the biasing means is a rectification element connected so that a direction from the first power supply toward the second node becomes a forward direction, and the rectifying means is connected so that a direction from the first node toward the boosted voltage output terminal becomes the forward direction.

Preferably, the biasing means is a rectification element connected so that a direction from the second node toward the first power supply becomes a forward direction, and the rectifying means is connected so that a direction from the boosted voltage output terminal toward the first node becomes the forward direction.

Preferably, the charge accumulating means are constituted by capacitors. The capacitors are connected in series between the first and second power supply terminals and then are charged in the second state. The capacitors are connected in parallel between the second power supply terminal and a down voltage output terminal in the first state to thereby obtain a voltage between the first and second power supply terminal.

Preferably, further there is provided a switching means connecting to an external power supply between the voltage of the first power supply terminal and the voltage of the second power supply terminal, having at least one sub-power supply of a potential lower than the external power supply, and operationally connecting the external power supply and the sub-power supply and of a means for sequentially switching the connection and nonconnection state from the switching means connected to the external power supply to cause charging and discharging of the capacitors.

Preferably further there is provided a means for sequentially switching the connection and nonconnection state from the switching means connected to the sub-power supply to cause charging and discharging of the capacitors.

Preferably further there is provided at least two arrangements of a plurality of capacitors which are switched between the serial connection and parallel connection based on a clock signal and clock signals having inverse phases are supplied to the above at least two arrangements.

Preferably, the capacitors are composed of ferroelectric capacitors, high dielectric capacitors, MIM (metal-insulator-metal) configuration capacitors, DRAM trench and stack capacitors, planar capacitors, external capacitors, or MIS (metal-insulator-semiconductor) gate capacitors.

According to the present invention, by setting the first and second switching means in the conductive state and setting the third switching means in the nonconductive state, the capacitance element of each booster stage is charged to the differential voltage level between the first power supply and the second power supply. Then the first and second switching means are changed over to the nonconductive state and the third switching means is changed over to the conductive state, whereby the charged capacitance elements are connected in series between the constant potential and the output terminal of the power supply circuit and a positive or negative boosted voltage is output to the output terminal of the power supply circuit.

For this reason, the loss of the boosted voltage becomes only the voltage drop of the rectification element connected between the final stage and the output terminal, the reduction of the boosting efficiency accompanying the rise of the threshold voltage due to the substrate biasing effect can be avoided, and a reduction of the number of the booster stages for obtaining a desired high voltage and a shortening of the rising time of the boosted voltage can be achieved.

Further, according to the present invention, the value of the external power supply voltage is detected by a detecting circuit and the number of connections of the plurality of capacitance elements is switched in accordance with this detected voltage.

Then, the number of the capacitance elements set in accordance with the detected voltage are connected in series between the external power supply and the reference power supply and next connected in parallel and, at the same time, the connection and nonconnection states sequentially switched from the switching means connected to the external power supply to perform charging and discharging. Thus an output voltage of a value between the external power supply voltage and the reference power supply voltage is obtained.

Also, the switching between the serial connection and parallel connection of the capacitance elements is carried out based on the clock signal. Further, two systems of the plurality of capacitance elements are respectively driven by clock signals having inverse phases to each other. By this, the ripple accompanying the load current can be lowered.

Also, the capacitance element is comprised by an element having a high relative dielectric constant such as a ferroelectric capacitance, whereby the power loss is reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects and features of the present invention will become more apparent from the following description of the preferred embodiments made with reference to the drawings, in which:

FIG. 1 is a circuit diagram of an example of an inner power supply circuit;

FIG. 2 is a circuit diagram of a first embodiment of an inner power supply circuit according to the present invention;

FIG. 3 is a circuit diagram of the configuration of a booster stage of the first embodiment shown in FIG. 2;

FIGS. 4A to 4J are timing charts of the power supply circuit of the first embodiment shown in FIG. 2;

FIG. 5 is a circuit diagram of an example of a clock generating circuit supplying a clock signal to the power supply circuit of the first embodiment shown in FIG. 2;

FIG. 6 is a circuit diagram of a boosting clock generator used in FIG. 5;

FIGS. 7A to 7H are timing charts of an operation of the clock generating circuit shown in FIG. 5;

FIG. 8 is a circuit diagram of a second embodiment of the power supply circuit according to the present invention;

FIG. 9 is a circuit diagram of the configuration of the booster stage of a second embodiment shown in FIG. 8;

FIGS. 10A to 10J are timing charts of the power supply circuit of the second embodiment shown in FIG. 8;

FIG. 11 is a circuit diagram of a boosting clock generator used in FIG. 8;

FIGS. 12A to 12E are timing charts of an operation of the clock generating circuit shown in FIG. 8;

FIG. 13 is a circuit diagram of a fundamental configuration of a series regulator as a down converter used as an internal low voltage power supply circuit;

FIG. 14 is a circuit diagram of an example of the configuration of a capacitor switching type down converter;

FIG. 15 is a circuit diagram of a third embodiment of the down converter according to the present invention;

FIGS. 16A to 16J are timing charts of an operation of the third embodiment shown in FIG. 15;

FIG. 17 is a circuit diagram of an example of the configuration of a power supply circuit for 0.25 V.sub.CC according to the present invention; and

FIG. 18 is a circuit diagram of a fourth embodiment of a down converter according to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Erasing or writing an electrically erasable and programmable read only memory such as an EEPROM or flash memory requires a voltage higher than the supplied voltage. Therefore, various power supply circuits have been devised. FIG. 1 is a circuit diagram of a representative example of a conventional power supply circuit constituted by a booster circuit.

Note that, in FIG. 1, M1 to M4 are n-channel type MOS transistors, and C.sub.L is a load capacitor.

As illustrated, the power supply circuit of FIG. 1 is constituted by connecting a plurality of stages of partial circuits (booster stages) each comprising one capacitor, for example, C2, and one nMOS transistor, for example, M2, in series.

One of the electrodes of each of the capacitors C2, C3, C4 constituting a booster stage are connected to a common connecting point of the gate electrodes and drain diffusion layers of the nMOS transistors M2, M3, M4. The other electrodes of the capacitors C2, C3, C4 are alternately connected to either of supply lines of the clocks .phi.1 and .phi.2. The common connecting point of the gate electrodes and drain diffusion layers of the diode-connected n-channel type MOS transistors constituting the booster stages is connected to the source diffusion layer of the n-channel type MOS transistor of the booster stage of the front stage, while the source diffusion layer is connected to the common connecting point of the gate electrodes and the drain diffusion layers of the diode-connected n-channel type MOS transistors of the next stage.

Further, the order of connection of the clocks .phi.1 and .phi.2 is one where the odd number stages of the booster stages are connected to the clock .phi.1 and the even number stages are connected to the clock .phi.2.

The above power supply circuit constituted in this way attracts the charges from a semiconductor substrate on which a power supply voltage V.sub.CC and the present circuit are formed giving the clocks .phi.1 and .phi.2 by inverse phases and supplies a boosted voltage V.sub.OUT to an output terminal T.sub.OUT.

In the above-described power supply circuit, a large number of stages of the diode-connected transistors are needed for obtaining a desired high voltage since a forward direction voltage drop corresponding to the threshold voltage V.sub.TN of the nMOS transistor is caused. Particularly, the nearer to the output terminal T.sub.OUT of the power supply circuit, the larger the reverse direction potential difference between the source and the substrate, so the larger the substrate biasing effect and the more the threshold voltage V.sub.TN of the transistor rises. Therefore, there is a disadvantage that the boosting efficiency is conspicuously lowered even if the number of stages is increased.

Preferred embodiments of the present invention will now be explained in further detail with reference to the drawings.

FIG. 2 is a circuit diagram of a first embodiment of the power supply circuit according to the present invention.

In FIG. 2, CLK.sub.1, CLK.sub.2, and CLK.sub.3 denote clock signals, T.sub.CLK1, T.sub.CLK2, and T.sub.CLK3 denote clock signal input terminals, PT.sub.1 denotes a p-channel type (pMOS) transistor serving as a biasing means, PT.sub.2 and PT.sub.3 denote pMOS transistors serving as the third switching means, PT.sub.L denotes diode-connected pMOS transistor, NU.sub.1, NU.sub.2, and NU.sub.3 denote n-channel MOS (nMOS) transistors serving as the first switching means, NL.sub.1, NL.sub.2, and NL.sub.3 denote nMOS transistors serving as the second switching means, K.sub.1, K.sub.2, K.sub.3, L.sub.1, L.sub.2, and L.sub.3 denote nodes of the booster stages, C.sub.1, C.sub.2, and C.sub.3 denote capacitance elements (capacitors) for boosting, C.sub.L denotes a parasitic capacitance of the load, and T.sub.OUT denotes an output terminal of the boosted voltage V.sub.OUT.

Note that the power supply circuit shown in FIG. 2 is constituted by the booster stages shown in FIG. 3.

Here, an explanation will be given of the configuration assuming that the booster stage shown in FIG. 3 is a booster stage of the i-th stage. As illustrated, the booster stage of i-th stage is constituted by a capacitor C.sub.i, nodes K.sub.i and L.sub.i, and nMOS transistors NU.sub.i and NL.sub.i.

The capacitor C.sub.i is connected between the node K.sub.i and the node L.sub.i.

The gate electrode of the nMOS transistor NU.sub.i, is connected to the input terminal of the clock signal CLK.sub.1, one diffusion layer is connected to the supply line of the power supply voltage V.sub.hd CC, and the other diffusion layer is connected to the node L.sub.i.

The gate electrode of the nMOS transistor NL.sub.i is connected to the input terminal of the clock signal CLK.sub.2, one diffusion layer is connected to the node K.sub.i, and the other diffusion layer is connected to the ground line.

The power supply circuit shown in FIG. 2 is configured with three stages of the booster stages shown in FIG. 3 connected in series.

As illustrated, the node K.sub.1 of the booster stage of first stage is connected via the pMOS transistor PT.sub.1 to the supply line of the power supply voltage V.sub.CC. Namely, the source electrode of the pMOS transistor PT.sub.1 is connected to the supply line of the power supply voltage V.sub.CC, and the drain electrode is connected to the node K.sub.1. The gate electrode of the pMOS transistor PT.sub.1 is connected to the input terminal T.sub.CLK3 of the clock signal CLK.sub.3.

The node L.sub.1 of the booster stage of the first stage is connected via the pMOS transistor PT.sub.2 to the node K.sub.2 of the booster stage of the second stage. Namely, the source electrode of the pMOS transistor PT.sub.2 is connected to the node L.sub.1 of the booster stage of the first stage, and the drain electrode is connected to the node K.sub.2 of the booster stage of the second stage.

The gate electrode of the pMOS transistor PT.sub.2 is connected to the input terminal T.sub.CLK3 of the clock signal CLK.sub.3.

The node L.sub.2 of the booster stage of the second stage is connected via the pMOS transistor PT.sub.3 to the node K.sub.3 of the booster stage of the third stage. Namely, the source electrode of the pMOS transistor PT.sub.3 is connected to the node L.sub.2 of the booster stage of the second stage, and the drain electrode is connected to the node K.sub.3 of the booster stage of the third stage.

The gate electrode of the pMOS transistor PT.sub.3 is connected to the input terminal T.sub.CLK3 of the clock signal CLK.sub.3.

The node L.sub.3 of the booster stage of the third stage is connected via the pMOS transistor PT.sub.L to the output terminal T.sub.OUT of the power supply circuit. Namely, the source electrode of the pMOS transistor PT.sub.L is connected to the node L.sub.3 of the booster stage of the third stage, and the drain electrode is connected to the output terminal T.sub.OUT of the power supply circuit.

The gate electrode of the pMOS transistor PT.sub.L is connected to the output terminal T.sub.OUT commonly with the drain electrode. Namely, the pMOS transistors PT.sub.L are diode-connected.

Further, the output terminal T.sub.OUT is grounded via the load capacitor C.sub.L.

Note that, in the power supply circuit shown in FIG. 2, the pMOS transistor PT.sub.1 serving as the biasing means is for example formed in the same well as that of the other transistors constituting the peripheral circuits of the power supply circuit. pMOS transistors PT.sub.2 and PT.sub.3 are formed in each independent well as the third switching means.

Below, an explanation will be made of the boosting operation of the power supply circuit having the above configuration referring to the timing chart of FIGS. 4A to 4J.

At the time of the boosting operation, a clock signal CLK.sub.1 is supplied to the gate electrodes of the nMOS transistors NU.sub.1, NU.sub.2, and NU.sub.3 constituting the booster stages. As shown in FIG. 4A, the high level of the clock signal CLK.sub.1 is held at a higher level than the power supply voltage V.sub.CC, for example, a potential of (V.sub.CC +V.sub.TN). Note that, here, V.sub.TN is a threshold voltage of the nMOS transistors NU.sub.1, NU.sub.2, and NU.sub.3.

For this reason, when the clock signal CLK.sub.1 is held at a high level, a voltage higher than the power supply voltage V.sub.CC, for example, a voltage of (V.sub.CC +V.sub.TN). is supplied to the gate electrodes of the nMOS transistors NU.sub.1, NU.sub.2, and NU.sub.3 constituting the booster stages. The drain electrodes of these transistors are held at a potential of the same level as that of the power supply voltage V.sub.CC.

The clock signal CLK.sub.2 supplied to the gate electrodes of the nMOS transistors NL.sub.1, NL.sub.2, and NL.sub.3 constituting the booster stages is held at a high level and low level in synchronization with the clock signal CLK.sub.1. Note that, the high level of the clock signal CLK.sub.2 is held at for example the power supply voltage V.sub.CC level.

When both of the clock signal CLK.sub.1 and clock signal CLK.sub.2 are held at the high level, all of the nMOS transistors NU.sub.1, NU.sub.2, and NU.sub.3 and NL.sub.1, NL.sub.2, and NL.sub.3 constituting the booster stages are set in the conductive state, and the clock signal CLK.sub.3 supplied to the gate electrodes of the pMOS transistors PT.sub.1, PT.sub.2, and PT.sub.3 connected between the booster stages is held at a high level, for example, the power supply voltage V.sub.CC level, therefore all of these pMOS transistors PT.sub.1, PT.sub.2, and PT.sub.3 are held in the nonconductive state.

Due to this, during the period from a time t.sub.0 to a time t.sub.1 shown in FIGS. 4A and 4B, the clock signal CLK.sub.1 and the clock signal CLK.sub.2 are held at a high level, and the capacitors C.sub.1, C.sub.2 and C.sub.3 existing in the booster stages are charged to for example the power supply voltage V.sub.CC level.

At the time t.sub.1, both of the clock signal CLK.sub.1 and clock signal CLK.sub.2 are switched to the low level, therefore the nMOS transistors NU.sub.1, NU.sub.2, and NU.sub.3 and NL.sub.1, NL.sub.2, and NL.sub.3 constituting the booster stages are set in the nonconductive state at the time t.sub.2.

Next, at the time t.sub.2, the clock signal CLK.sub.3 is switched from the high level to the low level, for example, the ground potential GND. In accordance with this, all of the pMOS transistors PT.sub.1, PT.sub.2, and PT.sub.3 are switched to the conductive state.

Due to this, the capacitors C.sub.1, C.sub.2, and C.sub.3 all charged to the power supply voltages V.sub.CC level are connected in series between the node K.sub.1 of the first stage and the output terminal T.sub.OUT of the power supply circuit, and a voltage obtained by multiplying the power supply voltage by (number of booster stages +1) is obtained at one end of the capacitor of the final stage.

Here, when the number of the booster stages of the power supply circuit is defined as n and the threshold voltage of the pMOS transistors PT.sub.L diode-connected between the node L.sub.n of the booster stage of the final stage and the output terminal T.sub.OUT is defined as V.sub.TP, the boosted voltage V.sub.OUT obtained by the power supply circuit

V.sub.OUT =(n+1).times.V.sub.CC -V.sub.TP (1)

As shown in FIGS. 4D to 4J, after the pMOS transistors PT.sub.1, PT.sub.2, and PT.sub.3 are all switched to the conductive state, the node K.sub.1 of the booster stage of the first stage is held at the power supply voltage V.sub.CC level, and the node L.sub.1 is held at the 2 V.sub.CC level.

The node K.sub.2 of the second stage is held at 2 V.sub.CC in the same way as the node L.sub.1 of the first stage, and the node L.sub.2 of the second stage is held at 3 V.sub.CC.

The node K.sub.3 of the third stage is held at 3 V.sub.CC in the same way as the node L.sub.2 of the second stage, and the node L.sub.3 of the third stage is held at 4 V.sub.CC,

The pMOS transistors PT.sub.L are diode-connected. The connection is made so that the direction from the node L.sub.3 of the third stage toward the output terminal T.sub.OUT becomes the forward direction, therefore the voltage of the node L.sub.3 is output to the output terminal T.sub.OUT. By this, the capacitor C.sub.L is charged, and a boosted voltage V.sub.OUT of substantially 4 V.sub.CC is output to the output terminal T.sub.OUT .

FIG. 5 is a circuit diagram of a clock generating circuit showing an example of the circuit for generating the clock signals CLK.sub.1, CLK.sub.2, and CLK.sub.3 shown in FIG. 2.

As illustrated, the clock generating circuit of the present example is constituted by RS flip-flops RFF.sub.1, RFF.sub.2, RFF.sub.3, RFF.sub.4, RFF.sub.5, and RFF.sub.6, a clock generator 10, and delay circuits DLY.sub.1 and DLY.sub.2.

An example of the configuration of the clock generator 10 is shown in FIG. 6.

As illustrated, the clock generator 10 is constituted by the nMOS transistors NA, NB, NC, and ND and a capacitor C.sub.CK.

One diffusion layer of the nMOS transistor NB is connected to the supply line of the power supply voltage V.sub.CC, the other diffusion layer is connected to the node ND.sub.1, and the gate electrode is connected to the input terminal of the clock signal B.

One diffusion layer of the nMOS transistor NA is connected to the node ND.sub.1, the other diffusion layer is grounded, and the gate electrode is connected to the input terminal of the clock signal A.

One diffusion layer of the nMOS transistor ND is connected to the supply line of the power supply voltage V.sub.CC, the other diffusion layer is connected to the node ND.sub.2, and the gate electrode is connected to the input terminal of the clock signal D.

One diffusion layer of the nMOS transistor NC is connected to the node ND.sub.2, the other diffusion layer is grounded, and the gate electrode is connected to the input terminal of the clock signal C.

A capacitor C.sub.CK is connected between the node ND.sub.1 and the node ND.sub.2, and the node ND.sub.2 is connected to the output terminal T.sub.1 of the clock signal CLK.sub.1.

At the time of the boosting operation, the clock signals A, B, C, and D shown in FIGS. 7A to 7D are input to the clock generator 10.

Upon receipt of this, the clock generator 10 generates a clock signal CLK.sub.1 held at a higher level than that of the power supply voltage V.sub.CC at the time of a high level.

As shown in FIG. 5, the set signal input terminal S of the RS flip-flop RFF.sub.1 is connected to the inverted output terminal of the RS flip-flop RFF.sub.5, and a reset signal input terminal R is connected to the inverted output terminal of the RS flip-flop RFF.sub.2.

The output terminal of the RS flip-flop RFF.sub.1 is connected to the set signal input terminal S of the RS flip-flop RFF.sub.2, and the inverted output terminal is connected to the reset signal input terminal R of the RS flip-flop RFF.sub.6.

Further, the inverted output signal of the RS flip-flop RFF.sub.1 is output as the clock signal C to the clock generator 10.

The reset signal input terminal R of the RS flip-flop RFF.sub.2 is connected to the inverted output terminal of the RS flip-flop RFF.sub.3, and the output terminal is connected to the set signal input terminal S of the RS flip-flop RFF.sub.3.

Further, the output signal of the RS flip-flop RFF.sub.2 is supplied to the clock generator 10 as the clock signal D.

The reset signal input terminal R of the RS flip-flop RFF.sub.3 is connected to the inverted output terminal of the RS flip-flop RFF.sub.4, and the output terminal is connected to the set signal input terminal S of the RS flip-flop RFF.sub.4.

Further, the inverted output signal of the RS flip-flop RFF.sub.3 is supplied to the clock generator 10 as the clock signal A.

The reset signal input terminal R of the RS flip-flop RFF.sub.4 is connected to the inverted output terminal of the RS flip-flop RFF.sub.5, and the output terminal is connected to the set signal input terminal S of the RS flip-flop RFF.sub.5 via the delay circuit DLY.sub.1.

Further, the output signal of the RS flip-flop RFF.sub.4 is supplied to the clock generator 10 as the clock signal B.

The reset signal input terminal R of the RS flip-flop RFF.sub.5 is connected to the output terminal of the RS flip-flop RFF.sub.6, and the inverted output terminal is connected to the output terminal T.sub.2 of the clock signal CLK.sub.2.

The reset signal input terminal R of the RS flip-flop RFF.sub.6 is connected to the inverted output terminal of the RS flip-flop RFF.sub.1, the set signal input terminal S is connected to the output terminal of the delay circuit DLY.sub.2, and the input terminal of the delay circuit DLY.sub.2 is connected to the inverted output terminal of the RS flip-flop RFF.sub.6.

The output terminal of the RS flip-flop RFF.sub.6 is connected to the output terminal T.sub.3 of the clock signal CLK.sub.3.

Below, referring to the timing chart shown in FIGS. 7A to 7H, the operation of the clock generating circuit having the above configuration will be explained.

The clock generating circuit shown in FIG. 5 generates the clock signals A, B, C, and D shown in FIGS. 7A to 7H and the clock signals CLK.sub.1, CLK.sub.2, and CLK.sub.3.

Note that, the clock signals A, B, C, and D are clock signals alternately taking a high level, for example, the power supply voltage V.sub.CC level, and a low level, for example, the ground potential GND level.

Similarly, the clock signals CLK.sub.2 and CLK.sub.3 are clock signals alternately taking a high level, for example, the power supply voltage V.sub.CC level, and a low level, for example, the ground potential GND level.

The clock signals A, B, C, and D are input to the clock generator 10. The clock generator 10 generates a clock signal CLK.sub.1 which is held at a level of more than the power supply voltage V.sub.CC at the time of the high level and is held at, for example, the ground potential GND level at the time of the low level.

As shown in FIG. 6, when both of the clock signal D and the clock signal A are held at the high level and both of the clock signal B and the clock signal C are held at the low level, the nMOS transistors NA and ND are held in the conductive state, and the nMOS transistors NB and NC are held in the nonconductive state.

By this, the node ND.sub.1 is held at the ground potential GND level, and the node ND.sub.2 side is held at a voltage reduced from the power supply voltage V.sub.CC by exactly the threshold voltage V.sub.TN of the nMOS transistor ND, therefore the capacitor C.sub.CK is charged to (V.sub.CC -V.sub.TN)

Further, at this time, the voltage of (V.sub.CC -V.sub.TN) level is output to the output terminal T.sub.1 of the clock signal CLK.sub.1.

Then, at the time t.sub.0 shown in FIGS. 7A to 7H, the clock signal B is switched from the low level to the high level. Also, at this time, both of the clock A and clock C are held at the low level, and the nMOS transistors NA and NC are set in the nonconductive state.

In accordance with this, the nMOS transistor NB is switched to the conductive state, and the node ND.sub.1 is held at a voltage reduced from the power supply voltage V.sub.CC by exactly the threshold voltage V.sub.TN of the nMOS transistor NB, that is, (V.sub.CC -V.sub.TN). By this, the node ND.sub.2 is held at 2(V.sub.CC -V.sub.TN) At this time, as shown in FIG. 7F, the voltage of the output terminal T.sub.1 of the clock signal CLK.sub.1 rises by one stage and becomes 2(V.sub.CC -V.sub.TN), that is, is held at a higher level than that of the power supply voltage V.sub.CC.

Subsequently, at the time t.sub.0 ', the clock signal B is switched from the high level to the low level, and the clock signal A is switched from the low level to the high level in accordance with this. Further, in accordance with this, the clock signal C is switched to the high level, and the clock signal D is switched to the low level.

For this reason, at the time t.sub.1, the potentials of the nodes ND.sub.1 and ND.sub.2 are switched to the ground potential, and the output terminal T.sub.1 of the clock signal CLK.sub.1 is held at the ground potential. Then, at the time t.sub.2, the clock signal CLK.sub.3 is switched from the high level to the low level.

At the time t.sub.3, the clock signal CLK.sub.2 and the clock signal CLK.sub.3 are switched from the low level to the high level. In accordance with this, the clock signal C is switched to the low level and the clock signal D is switched to the high level, therefore, the capacitor C.sub.CK is charged to (V.sub.CC -V.sub.TN) again.

In this way, the clock generating circuit shown in FIG. 5 generates the clock signal CLK.sub.1 which is held at 2(V.sub.CC -V.sub.TN) level at the time of the high level and held at the ground potential at the time of the low level and the clock signal CLK.sub.2 and the clock signal CLK.sub.3 which are held at the power supply voltage V.sub.CC level at the time of the high level and held at the ground potential at the time of the low level and supplies them to the power supply circuit shown in FIG. 2.

As explained above, according to the present embodiment, the clock signal CLK.sub.1 held at a higher level than the power supply voltage V.sub.CC at the time of the high level is supplied to the gate electrodes of the nMOS transistors NU.sub.1, NU.sub.2, and NU.sub.3 constituting the booster stages, the clock signal CLK.sub.2 is supplied to the gate electrodes of the nMOS transistors NL.sub.1, NL.sub.2, and NL.sub.3, the clock signal CLK.sub.3 is supplied to the gate electrodes of the pMOS transistors PT.sub.1, PT.sub.2, and PT.sub.3 connected between the booster stages, the clock signals CLK.sub.1 and CLK.sub.3 are held at the high level, and the capacitors C.sub.1, C.sub.2, and C.sub.3 of the booster stages are charged to the power supply voltage V.sub.CC level, then the clock signals CLK.sub.1 and CLK.sub.2 are switched to the low level, the clock signal CLK.sub.3 is switched to the high level, and the boosted voltage V.sub.OUT is supplied to the output terminal T.sub.OUT of the power supply circuit, therefore there is no loss of the boosted voltage due to the substrate biasing effect at the time of boosting, the number of stages necessary for obtaining the desired high voltage can be decreased, the output current per chip area can be made larger, and the rising time can be shortened.

FIG. 8 is a circuit diagram of a second embodiment of the power supply circuit according to the present invention.

As illustrated, FIG. 8 is a circuit diagram of the power supply circuit showing an example of the negative booster circuit for generating a negative boosted voltage compared with the power supply voltage V.sub.CC. The power supply circuit can be used for biasing for example a structure of a semiconductor circuit such as a dynamic random access memory.

In FIG. 8, CLK.sub.B2 and CLK.sub.B3 are inverted signals of the clock signals CLK.sub.2 and CLK.sub.3 shown in FIG. 1, and CLK.sub.B1 is a clock signal which is held at the power supply voltage V.sub.CC level at the time of the high level in synchronization with the clock signal CLK.sub.B2 and held at a level lower than the ground potential GND, that is, a negative potential at the time of the low level.

T.sub.CLKB1, T.sub.CLKB2, and T.sub.CLKB3 denote input terminals of the clock signals CLK.sub.B1, CLK.sub.B2, and CLK.sub.B3, NT.sub.1 denotes an nMOS transistor serving as the biasing means, NT.sub.2 and NT.sub.3 denote nMOS transistors serving as the third switching means, NT.sub.L denotes diode-connected nMOS transistor, PL.sub.1, PL.sub.2, and PL.sub.3 denote pMOS transistors serving as the first switching means, PU.sub.1, PU.sub.2, and PU.sub.3 denote pMOS transistors serving as the second switching means, KB.sub.1, KB.sub.2, KB.sub.3, LB.sub.1, LB.sub.2, and LB.sub.3 denote nodes of booster stages, C.sub.1, C.sub.2, and C.sub.3 denote capacitors for boosting, C.sub.L denotes a parasitic capacitance of the load, and T.sub.OUTB denotes an output terminal of the negative boosted voltage V.sub.OUTB.

As illustrated, the power supply circuit of the present example was constituted by three booster stages constituted by pMOS transistors PU.sub.1, PU.sub.2, PU.sub.3, PL.sub.1, PL.sub.2, and PL.sub.3 and capacitors C.sub.1, C.sub.2, and C.sub.3.

Here, an explanation will be made of the configuration of the i-th stage of the booster stage constituted by the pMOS transistors PU.sub.i and PL.sub.i and the capacitor C.sub.i referring to FIG. 9 without losing generality.

As shown in FIG. 9, the gate electrode of the pMOS transistor PU.sub.i is connected to the input terminal of the clock signal CLK.sub.B2, the source electrode is connected to the supply line of the power supply voltage V.sub.CC, and the drain electrode is connected to the node KB.sub.i of the booster stage.

The gate electrode of the pMOS transistor PL.sub.i is connected to the input terminal of the clock signal CLK.sub.B1, the source electrode is connected to the node LB.sub.i. and the drain electrode is grounded.

One electrode of the capacitor C.sub.i is connected to the node KB.sub.i, and the other electrode is connected to the node LB.sub.i.

FIGS. 10A to 10J are waveform diagrams of the clock signals CLK.sub.B1, CLK .sub.B2, and CLK.sub.B3, the voltages of the boosting nodes KB.sub.1, LB.sub.1, KB.sub.2, LB.sub.2, KB.sub.3, and LB.sub.3, and the output voltage V.sub.OUTB.

As shown in FIGS. 10A and 10C, the clock signal CLK.sub.B1 and the clock signal CLK.sub.B2 are synchronous. The clock signal CLK.sub.B1 is held at the power supply voltage V.sub.CC level at the time of the high level and is held at the level lower than the ground potential GND, that is, a negative potential, at the time of the low level. The clock signal CLK.sub.B2 is held at the power supply voltage V.sub.CC level at the time of the high level and is held at the ground potential GND level at the time of the low level.

Below, an explanation will be made of the operation of the negative booster circuit of the present invention referring to the waveform diagram shown in FIGS. 10A to 10J.

As shown in FIG. 10A, at the time t.sub.0, the clock signals CLK.sub.B1 and CLK.sub.B2 are switched from the high level to the low level. The clock signal CLK.sub.B1 is held at the negative potential and the clock signal CLK.sub.B2 is held at the ground potential GND level.

During the period where the clock signal CLK.sub.B1 and the clock signal CLK.sub.B2 are held at the low level, the pMOS transistors PU.sub.1, PU.sub.2, and PU.sub.3 and the pMOS transistors PL.sub.1, PL.sub.2, and PL.sub.3 are held in the conductive state, and the capacitors C.sub.1, C.sub.2, and C.sub.3 are charged.

For this reason, at the booster stages, the nodes LB.sub.1, LB.sub.2, and LB.sub.3 are held at the ground potential GND level, the nodes KB.sub.1, KB.sub.2, and KB.sub.3 are held at the power supply voltage V.sub.CC level, and the capacitors C.sub.1, C.sub.2, and C.sub.3 are charged to the power supply voltage V.sub.CC level.

At the time t.sub.1, the clock signals CLK.sub.B1 and CLK.sub.B2 are switched from the low level to the high level, and the pMOS transistors PU.sub.1, PU.sub.2, and PU.sub.3 and the pMOS transistors PL.sub.1, PL.sub.2, and PL.sub.3 are switched to the nonconductive state.

Further, at the time t.sub.2, the clock signal CLK.sub.B3 is switched from the low level to the high level, and the nMOS transistors NT.sub.1, NT.sub.2, and NT.sub.3 are switched to the conductive state in accordance with this.

According to this, at the booster stage of initial stage, the node KB.sub.1 is held at the ground potential GND level, and the node LB.sub.1 is held at the -V.sub.CC level.

In the booster stage of the second stage, the node KB.sub.2 is held at the -V.sub.CC level in the same way as the node LB.sub.1, and the node KB.sub.2 is held at the -2 V.sub.CC level.

In the booster stage of the third stage, the node KB.sub.3 is held at the -2 V.sub.CC level in the same way as the node LB.sub.2, and the node KB.sub.3 is held at the -3 V.sub.CC level.

The potential of the node LB.sub.3 is output to the output terminal T.sub.OUTB via the diode-connected nMOS transistors NT.sub.L. Here, when defining the threshold voltage of the nMOS transistor NT.sub.L as V.sub.TN, the negative boosted voltage V.sub.OUTB output to the output terminal T.sub.OUTB becomes -(3 V.sub.CC -V.sub.TN).

In general, the boosted voltage V.sub.OUTB obtaining by the negative booster circuit constituted by n number of stages of booster stages is found by the following equation:

V.sub.OUTB =-(n.times.V.sub.CC -V.sub.TN) (2)

In this way, the voltage loss of the boosted voltage V.sub.OUTB obtained by the negative booster circuit shown in FIG. 8 is only the voltage drop in the diode-connected between the final stage and the output terminal T.sub.OUTB, and an improvement of the efficiency of the power supply circuit can be achieved.

Note that, in the negative booster circuit of the present embodiment, in the same way as the positive booster circuit shown in FIG. 2, the nMOS transistor NT.sub.1 is formed in the same well as that for the other transistors constituting the peripheral circuit of for example the negative booster circuit, and nMOS transistors NT.sub.2 and NT.sub.3 are formed individually in independent wells.

FIG. 11 is a circuit diagram of an example of the generator 10a of the clock signal CLK.sub.B1 in the second embodiment.

As illustrated, the clock generator 10a is constituted by the nMOS transistors NA.sub.B, NB.sub.B, NC.sub.B, and ND.sub.B and the capacitor C.sub.CK.

One diffusion layer of the nMOS transistor NB.sub.B is connected to the supply line of the power supply voltage V.sub.CC, the other diffusion layer is connected to the node ND.sub.1, and the gate electrode is connected to the input terminal of the clock signal B.sub.B.

One diffusion layer of the nMOS transistor NA.sub.B is connected to the node ND.sub.1, the other diffusion layer is grounded, and the gate electrode is connected to the input terminal of the clock signal A.sub.B.

One diffusion layer of the nMOS transistor ND.sub.B is connected to the supply line of the power supply voltage V.sub.CC, the other diffusion layer is connected to the node ND.sub.2, and the gate electrode is connected to the input terminal of the clock signal D.sub.B.

One diffusion layer of the nMOS transistor NC.sub.B is connected to the node ND.sub.2, the other diffusion layer is grounded, and the gate electrode is connected to the input terminal of the clock signal C.sub.B.

A capacitor C.sub.CK is connected between the node ND.sub.1 and the node ND.sub.2 and the node ND.sub.2 is connected to the output terminal T.sub.B1 of the clock signal CLK.sub.B1.

At the time of the boosting operation, the clock signals A.sub.B, B.sub.B, C.sub.B, and D.sub.B shown in FIGS. 12A to 12D are input to the clock generator 10a.

Upon receipt of these clock signals, the clock generator 10a generates a clock signal CLK.sub.B1 which is held at the power supply voltage V.sub.CC at the time of the high level and is held at a lower level than the ground potential GND at the time of the low level.

Below, an explanation will be made of the operation of the generator 10a of the clock signal CLK.sub.B1 shown in FIG. 11 referring to the waveform diagram of the clock signals A.sub.B, B.sub.B, C.sub.B, and D.sub.B and the clock signal CLK.sub.B1 shown in FIGS. 12A to 12E.

As shown in FIGS. 12A to 12D, at the time t.sub.0 ', the clock signals B.sub.B and C.sub.B are switched to the high level, for example, the power supply voltage V.sub.CC level. Note that, at this time, both of the clock signals A.sub.B and D.sub.B are held at the low level, for example, the ground potential GND.

In accordance with this, in the clock generator 10a, the nMOS transistors NA.sub.B and ND.sub.B are set in the nonconductive state, and both of the nMOS transistors NB.sub.B and NC.sub.B are set in the conductive state.

For this reason, the capacitor C.sub.CK is charged, and the node ND.sub.1 is held at a voltage which becomes lower than the power supply voltage V.sub.CC by exactly the threshold voltage V.sub.TN of the nMOS transistor NB.sub.B, that is, (V.sub.CC -V.sub.TN).

Then, at the time t.sub.0, the clock signals B.sub.B and C.sub.B are switched to the low level, and the clock signal A.sub.B is raised to the high level, for example, the power supply voltage V.sub.CC level. Note that, at this time, the clock signal D.sub.B is held at the low level as it is.

In accordance with this, both of the nMOS transistors NB.sub.B and NC.sub.B are switched to the nonconductive state, and the nMOS transistor NA.sub.B is switched to the conductive state. Further, the nMOS transistor ND.sub.B is held in the nonconductive state as it is. For this reason, the node ND.sub.1 is held at the ground potential GND, and the node ND.sub.2 is held at the negative potential, for example -(V.sub.CC -V.sub.TN).

Subsequently, at the time t.sub.1, the clock signal A.sub.B is switched to the low level, and the clock signal D.sub.B is raised to the high level, for example, the power supply voltage V.sub.CC. In accordance with this, the nMOS transistor NA.sub.B is switched to the nonconductive state, and the nMOS transistor ND.sub.B is switched to the conductive state.

Note that, at this time, the clock signals B.sub.B and C.sub.B are held at the low level, and both of the nMOS transistors NB.sub.B and NC.sub.B are held in the nonconductive state, therefore the node ND.sub.2 is held at the power supply voltage V.sub.CC level.

Then, at the time t.sub.4, the clock signal D.sub.B is switched to the low level, and both of the clock signals B.sub.B and C.sub.B are raised to the high level, therefore both of the nMOS transistors NB.sub.B and NC.sub.B are set in the conductive state, and the capacitor C.sub.CK is charged and the node ND.sub.1 is held at the (V.sub.CC -V.sub.TN) level.

The above operation is repeatedly carried out, therefore the clock generatory 10a shown in FIG. 11 generates a clock signal CLK.sub.B1 which is held at a level lower than the ground potential GND during the low level section and is held at the power supply voltage V.sub.CC level in the high level section and outputs the same from the output terminal T.sub.B1. Then, this clock signal CLK.sub.B1 is supplied to the negative booster circuit shown in FIG. 8, and the negative boosted voltage V.sub.OUTB is generated.

As explained above, according to the present embodiment, the clock signal CLK.sub.B2 is applied to the gate electrodes of the pMOS transistors PU.sub.1, PU.sub.2, and PU.sub.3 constituting the booster stages, the clock signal CLK.sub.B1 which is held at the power supply voltage V.sub.CC level at the time of the high level and is held at the negative potential at the time of the low level is supplied to the gate electrodes of the pMOS transistors PL.sub.1, PL.sub.2, and PL.sub.3, the clock signal CLK.sub.B3 is supplied to the gate electrodes of the nMOS transistors NT.sub.1, NT.sub.2, and NT.sub.3 connected between the booster stages, the clock signals CLK.sub.B1 and CLK.sub.B2 are held at the low level, and the capacitors C.sub.1, C.sub.2, and C.sub.3 of the booster stages are charged to the power supply voltage V.sub.CC level, then the clock signals CLK.sub.B1 and CLK.sub.B2 are switched to the high level, the clock signal CLK.sub.B3 is switched to the high level, and the negative boosted voltage V.sub.OUTB is output to the output terminal T.sub.OUTB, therefore there is no loss of the boosted voltage due to the substrate biasing effect at the time of boosting, the number of stages necessary for obtaining the desired high voltage can be decreased, the output current per chip area can be made larger, and the rising time can be shortened.

Also, in recent years, there have been growing demands for a low voltage (for example V.sub.CC /m) source independent from the power supply voltage V.sub.CC inside an LSI, for example, for a small amplitude transfer between chips and inside a chip.

As this type of inner low voltage supply, a series regulator as shown in FIG. 13 is generally used.

This series regulator is constituted by, as shown in FIG. 13, an operational amplifier 11 with an inverted input (-) connected to the supply line of a constant voltage V.sub.L, and a pMOS transistor 12 with a gate connected to the output of the operational amplifier 11, with a source connected to the supply line of the power supply voltage V.sub.CC, and with a drain connected to a noninverted input (+) of the operational amplifier 1 and supplies a low voltage V.sub.L from a node N.sub.1 to a circuit block 13.

When considering the power loss of the series regulator, there is a loss P.sub.LS due to the pMOS transistor 12 indicated by the following equation:

P.sub.LS =(V.sub.CC -V.sub.L).multidot.i.sub.L (3)

Then, when V.sub.L <(V.sub.CC /2), the loss becomes 50 percent or more, which becomes a major obstacle to reduction of the power consumption of the LSI.

Particularly, where a lithium ion battery is used as the V.sub.CC external power supply, the fluctuation of the V.sub.CC is large and there arises a problem of the power loss thereof.

Therefore, a DC--DC converter which does not use an MOS transistor as a driver and is constituted only by capacitance elements and switches and with which a desired low voltage power supply potential can be obtained has been proposed.

FIG. 14 is a circuit diagram of an example of the configuration of this DC--DC converter.

As shown in FIG. 14, this DC--DC converter 20 is constituted by switch circuits 21 to 23 and capacitors 31 to 33. Note that, the switch circuits 21 to 23 are constituted by for example MOS type transistors. Also, as the capacitors 31 and 32, those having the same capacitance are used.

An operational contact a of the switch circuit 21 is connected to the supply line of the power supply voltage V.sub.CC, an operational contact b is connected to an output node ND.sub.OUT, and a fixed contact c is connected to one electrode of the capacitor 31.

The operational contact a of the switch circuit 22 is connected to the operational contact a of the switch circuit 23, the operational contact b is grounded, and the fixed contact c is connected to the other electrode of the capacitor 31.

The operational contact b of the switch circuit 23 is connected to the output node ND.sub.OUT, and the fixed contact c is connected to one electrode of the capacitor 32. Then, the other electrode of the capacitor 32 is grounded.

Also, the capacitor 33 is a stabilizing capacitor which is connected between the output node ND.sub.OUT and the ground line for suppressing the voltage drop of the output node ND.sub.OUT by a load current I.sub.L and stabilizing the same. Note that, it is not necessary to provide this stabilizing capacitor 33 where the parasitic capacitance of the output power supply line is large.

The switch circuits 21, 22, and 23 connect their fixed contacts c to the operational contact a when the clock signal .phi. is at the V.sub.CC level (high level) and connect their fixed contacts c to the operational contact b when the clock signal .phi. is at the ground level (low level).

In such a configuration, when the clock signal .phi. is at a high level, two capacitors 31 and 32 are connected in series between the supply line of the power supply voltage V.sub.CC and the ground line to charge the capacitors 31 and 32.

When the clock signal .phi. is at a low level, two capacitors 31 and 32 are connected in parallel to discharge the same.

Next, since the capacitors 31 and 32 are constituted by elements having the same capacitance, due to the above charge and discharge function, the output voltage Va appearing at the output node ND.sub.OUT becomes V.sub.CC /2, which is supplied to a circuit block 40 operating at this low voltage V.sub.CC /2.

In the down converter shown in FIG. 14, when the nodes ND1 and ND2 are discharged from the power supply voltage V.sub.CC and 0.5 V.sub.CC to 0.5 V.sub.CC and 0 V, respectively, a power Pd indicated by the following equation is consumed:

Pd=(1/2).multidot.(Cs1+Cs2).multidot.(V.sub.CC /2).sup.2 .multidot.(1/.tau.)(4)

Here, Cs1 and Cs2 are parasitic capacitances of the nodes ND1 and ND2.

Similarly, at the time of charging as well, the same amount of power is consumed and, as a result, a power P indicated by the following equation is consumed in total:

P=(1/4).multidot.(Cs1+Cs2).multidot.(V.sub.CC /.tau.).sup.2(5)

With the power consumption shown by equation (5), however, the demand for reduction of the power consumption of the LSI is not sufficiently satisfied, thus realization of a DC--DC converter with which a stable output voltage can be obtained with a further lower power loss has been desired.

FIG. 15 is a circuit diagram of a third embodiment of the DC--DC converter according to the present invention. Also, FIGS. 16A to 16J are timing charts of the circuit of FIG. 15.

As shown in FIG. 15, this DC--DC converter 20a is constituted by switch circuits 21a to 23a, capacitors 31a, 32a, and 33a, an external power supply 50 of the power supply voltage V.sub.CC, a power supply 60 for 0.25 V.sub.CC, and a timing generating circuit 70 generating the clock signals .phi.1 to .phi.7 at a timing shown in FIGS. 16A to 16F.

In the switch circuit 21a, fixed contacts c1 and c2 of two on-off switches 111 and 112 are connected in parallel to one electrode of the capacitor 31a, the operational contact a1 of the switch 111 is connected to the external power supply 50, and the operational contact a2 of the switch 112 is connected to the output node ND.sub.OUT.

Then, the switch 111 is controlled on or off by the clock signal .phi.1, and the switch 112 is controlled on or off by the clock signal .phi.5.

More specifically, the switches 111 and 112 become the on state when the clock signal is at a high level and become the off state when it is at a low level. These on and off controls are complementarily carried out.

In the switch circuit 22a, the fixed contacts c1, c2, and c3 of the three on-off switches 121, 122, and 123 are connected in parallel to the other electrode of the capacitor 31a, and the operational contact a1 of the switch 121 is connected to the operational contact a1 of the switch 131 of the switch circuit 23a. The operational contact a2 of the switch 122 is connected to the power supply 60 for 0.25 V.sub.CC, and the operational contact a3 of the switch 123 is grounded.

Then, the switch 121 is controlled on or off by the clock signal .phi.2, the switch 122 is controlled on or off by the clock signal .phi.6, and the switch 123 is controlled on or off by the clock signal .phi.7.

More specifically, the switches 121, 122, and 123 become the on state when the clock signal is at a high level and become the off state when it is at a low level. The on-off control of these switches 121, 122, and 123 is sequentially carried out.

In the switch circuit 23a, the fixed contacts c1 and c2 of the two on-off switches 131 and 132 are connected in parallel to one electrode of the capacitor 32a, and the operational contact a2 of the switch 132 is connected to the output node ND.sub.OUT.

Then, the switch 131 is controlled on or off by the clock signal .phi.3, and the switch 112 is controlled on or off by the clock signal .phi.4.

More specifically, the switches 131 and 132 become the ON state when the clock signal is at a high level and become the off state when it is at a low level. These on and off controls are complementarily carried out.

Also, the other electrode of the capacitor 32a is grounded.

Note that, the switch circuits 21a to 23a are constituted by for example MOS system transistors.

Also, a stabilizing capacitor 33a for suppressing the voltage drop of the output node ND.sub.OUT by the load current I.sub.L is connected between the output node ND.sub.OUT and the ground line.

Note that, it is not necessary to provide this stabilizing capacitor 33a when the parasitic capacitance of the output power supply line is large.

Also, as the capacitors 31a and 32a, those having the same capacitance are used.

FIG. 17 is a circuit diagram of an example of the configuration of the power supply 60 for 0.25 V.sub.CC.

This 0.25 V.sub.CC use power supply 60 is constituted by switch circuits 511 to 517 and capacitors 521 to 525 as shown in FIG. 17. Note that, the switch circuits 511 to 517 are constituted by for example MOS system transistors. Also, as the capacitors 521 to 524, those having the same capacitance are used.

The operational contact a of the switch circuit 511 is connected to the supply line of the power supply voltage V.sub.CC, the operational contact b is connected to the output node ND.sub.OUT, and the fixed contact c is connected to one electrode of the capacitor 521.

The operational contact a of the switch circuit 512 is connected to the operational contact a of the switch circuit 513, the operational contact b is grounded, and the fixed contact c is connected to the other electrode of the capacitor 521.

The operational contact b of the switch circuit 513 is connected to the output node ND.sub.OUT, and the fixed contact c is connected to one electrode of the capacitor 522.

The operational contact a of the switch circuit 514 is connected to the operational contact a of the switch circuit 515, the operational contact b is grounded, and the fixed contact c is connected to the other electrode of the capacitor 522.

The operational contact b of the switch circuit 515 is connected to the output node ND.sub.OUT, and the fixed contact c is connected to one electrode of the capacitor 523.

The operational contact a of the switch circuit 516 is connected to the operational contact a of the switch circuit 517, the operational contact b is connected to the output node ND.sub.OUT, and the fixed contact c is connected to one electrode of the capacitor 524.

Further, the other electrode of the capacitor 524 is grounded.

Further, the capacitor 525 is a stabilizing capacitor which is connected between the output node ND.sub.OUT and the ground line for suppressing the voltage drop of the output node ND.sub.OUT by a load current I.sub.L and stabilizing the same. Note that, it is not necessary to provide this stabilizing capacitor 525 when the parasitic capacitance of the output power supply line is large.

The switch circuits 511 to 517 connect their fixed contacts c to the operational contact a when the clock signal .phi..sub.50 is at the V.sub.CC level (high level) and connect their fixed contacts c to the operational contact b when the clock signal .phi..sub.50 is at the ground level (low level).

In the power supply 60 having such a configuration, when the clock signal .phi..sub.50 is at a high level, the four capacitors 521, 522, 523, and 524 are connected in series between the supply line of the power supply voltage V.sub.CC and the ground line and the capacitors 521 to 524 are charged.

When the clock signal .phi..sub.50 is at a low level, the four capacitors 421 to 424 are connected in parallel so the discharging is carried out.

The capacitors 521 to 524 are constituted by ones having the same capacitance, therefore, due to the above charge and discharge function, the output voltage Va appearing at the output node ND.sub.OUT becomes V.sub.CC /4=0.25 V.sub.CC which is supplied to the operational contact a2 of the switch 122 of the switch circuit 12a in the circuit of FIG. 15.

The timing generating circuit 70 first sets the clock signals .phi.1 to .phi.3 at a high level as shown in FIG. 16, holds the switches 111, 121, and 131 in the on state, connects two capacitors 31a and 32a in series between the external power supply 50 and the ground line, and makes them perform the charging with respect to the capacitors 31a and 32a.

Subsequently, at a time t1, the clock signals .phi.1 to .phi.3 are switched to the low level, the clock signals .phi.4 and .phi.6 are set at a high level, the node ND2 is connected to the 0.25 V.sub.CC use power supply 60, and the charges of the capacitor 31a on the side connected to the node ND2 are discharged to the power supply 50.

Then, at a time t2 after an elapse of a predetermined time, the clock signal .phi.6 is switched to the low level, the clock signal .phi.7 is set at a high level, the node ND2 is connected to the ground line, and the capacitor 31a is discharged so that the node ND1 exhibits 0.5 V.sub.CC and node ND.sub.2 exhibits 0 V.

Next, at a time t3, the clock signal .phi.5 is set at a high level, the node ND1 is connected to the output node ND.sub.OUT, and 0.5 V.sub.CC (V.sub.CC /2) is supplied to the output node ND.sub.OUT.

Further, at a time t4, the clock signals .phi.5 and .phi.7 are switched to the low level, the clock signal .phi.6 is set at a high level, the node ND2 is connected to 0.25 V.sub.CC use power supply 60, and the capacitor 31a is charged so that the potential of the node ND1 changes from 0.5 V.sub.CC to 0.75 V.sub.CC and the potential of the node ND2 changes from 0 V to 0.25.

Next, at a time t5, the clock signal .phi.6 is switched to the low level, the clock signal .phi.1 is set at a high level, the node ND1 is connected to the external power supply 50, and the capacitor 31a is charged so that the potential of the node ND1 becomes V.sub.CC and the potential of the node ND2 becomes 0.5 V.sub.CC.

Next, the operation by the above configuration will be explained by referring to the timing chart of FIG. 16.

First, the clock signals .phi.1, .phi.2, and .phi.3 among the clock signals .phi.1 to .phi.7 are set at a high level at the timing generating circuit 70, and the clock signal .phi.1 is supplied to the switch 111 of the switch circuit 21a, the clock signal .phi.2 is supplied to the switch 121 of the switch circuit 22a, and the clock signal .phi.3 is supplied to the switch circuit 131, respectively.

By this, the switches 111, 121, and 131 become the on state, the two capacitors 31a and 32a are connected in series between the external power supply 50 and the ground line, and the capacitors 31a and 32a are charged.

Next, at a time t1, the clock signals .phi.1 to .phi.3 are switched to the low level at the timing generating circuit 70, the clock signals .phi.4 and .phi.6 are set at a high level, the clock signal .phi.4 is supplied to the switch 132 of the switch circuit 23a, and the clock signal .phi.6 is supplied to the switch 122 of the switch circuit 22a, respectively.

By this, the switches 111, 121, and 131 become the off state, the switches 132 and 122 become the on state, and the supply of V.sub.CC /2 to the capacitor 33a and the circuit block 40 is started.

Along with the switch 122 becoming the on state, the node ND2 is connected to the 0.25 V.sub.CC use power supply 60, and the charges of the capacitor 31a on the side connected to the node ND2 are discharged to the power supply 60. Here, via the switch 122, a charge of 0.25 V.sub.CC (Cs1+Cs2) flows into the power supply 50. The level of the node ND1 at this time is 0.75 V.sub.CC.

In this case, at the switch 122, the power consumption shown by the following equation occurs.

P.sub.111 =(1/2).multidot.(Cs1=Cs2).sup.2 .multidot.(V.sub.CC /4).sup.2 .multidot.(1/.tau.) (6)

Here, Cs1 and Cs2 are parasitic capacitances of the nodes ND1 and ND2. The relationship with respect to the capacitance C.sub.21 of the capacitor 31a is set as C.sub.21 >>Cs1, Cs2.

Next, at a time t2, the clock signal .phi.6 is switched to the low level at the timing generating circuit 70, the clock signal .phi.7 is set at a high level, and the clock signal .phi.7 is supplied to the switch 123 of the switch circuit 22a.

By this, the switch 122 becomes the off state, and the switch 123 becomes the on state.

Along with the change of the switch 123 to the on state, the node ND2 is connected to the ground line. As a result, the capacitor 31a is discharged so that the node ND1 exhibits 0.5 V.sub.CC and the node ND2 exhibits 0 V.

In this case, at the switch 123, a power equivalent to the power indicated by the above equation (6) is consumed.

Then, at a time t3, the clock signal .phi.5 is set at a high level at the timing generating circuit 70 and is supplied to the switch 112 of the switch circuit 21a.

By this, the switch 112 becomes the off state, and 0.5 V.sub.CC (V.sub.CC /2) is supplied to the output node ND.sub.OUT.

Also, at a time t4, the clock signals .phi.5 and .phi.7 are switched to the low level at the timing generating circuit 70, the clock signal .phi.6 is set at a high level, and the clock signal .phi.6 is supplied to the switch 122 of the switch circuit 22a.

By this, the switches 122 and 123 become the off state, and the switch 122 becomes the on state.

Along with the change of the switch 122 to the on state, the node ND2 is connected to the 0.25 V.sub.CC use power supply 60. As a result, the capacitor 31a is charged so that the potential of the node ND1 changes from 0.5 V.sub.CC to 0.75 V.sub.CC, and the potential of the node ND2 changes from 0 V to 0.25 V.sub.CC.

In this case, at the switch 122, a power equivalent to the power indicated by the above equation (6) is consumed.

Here, charges of 0.25 V.sub.CC (Cs1+Cs2) flow out the power supply 60 via the switch 122. In this way, at the 0.25 V.sub.CC use power supply 60, an inflow and outflow of 0.25 V.sub.CC (Cs1+Cs2) occur by the charging and discharging, and the charges are recycled. For this reason, the frequency of the clock signal .phi..sub.50 for the power supply 50 may be low, and there is almost no power loss due to the circuit of FIG. 15.

Next, at a time t5, the clock signal .phi.6 is switched to the low level at the timing generating circuit 70, the clock signal .phi.1 is set at a high level, and the clock signal .phi.1 is supplied to the switch 111 of the switch circuit 21a.

By this, the switch 122 becomes the off state, and the switch 111 becomes the on state.

Along with the switch 111 becoming the on state, the node ND1 is connected to the external power supply 40. As a result, the capacitor 31a is charged so that the potential of the node ND1 becomes V.sub.CC and the potential of the node ND2 becomes 0.5 V.sub.CC.

In this case, at the switch 111, a power equivalent to the power indicated by the above equation (6) is consumed.

The power PT consumed by a series of discharging and charging operations is given by the following equation: ##EQU1##

This power consumption is 1/2 of the power consumption P=(1/4).multidot.(Cs1+Cs2).multidot.(V.sub.CC /.tau.).sup.2 of the conventional circuit.

As explained above, according to the first embodiment, in a DC--DC converter wherein two capacitors 31a and 32a are connected in series between the external power supply and the reference power supply (ground) to be charged and are connected in parallel to give an output voltage Va of a value between the external power supply voltage and the reference power supply voltage by the clock signals .phi.1 to .phi.3, provision is made of a power supply 50 for potential lower than the external power supply 50 and the ground voltage source and provision is made of switches 121, 122, and 123 respectively operationally connecting the external power supply 50 and the power supply 60 for low potential with the capacitors 31a and a circuit 60 for sequentially switching the connection and nonconnection state from the switch side connected to the external power supply to charge and discharge the capacitors 31a and sequentially switching the connection and nonconnection state from the switch side connected to the ground voltage source side to discharge the capacitors 31a and thereby perform a heat insulating charging, therefore there is the advantage that a low voltage source with which a stable output voltage Va can be obtained with a low power loss can be realized.

Note that, in the present embodiment, a so-called two-step charging method was used, but by adopting an n number step charging method in which the number of switches of the switch circuit 22a is further increased to n, the power loss can be reduced to 1/n of that of the conventional method.

Note that, needless to say the number of connections of the capacitors is not limited to that of the present example, and a variety of modifications are possible.

Also, the switch circuit can be constituted by for example a transmission gate of the CMOS type, but desirably a p-channel MOS transistor and n-channel MOS transistor are selected and used corresponding to the transmission potential.

Also, so as to reduce the power loss, as the capacitor, desirably use is made of an external capacitance, high dielectric capacitance, MIM (metal-insulator-metal) configuration capacitance, DRAM trench or stack capacitance, planar capacitance, ferroelectric capacitance, or the like.

Particularly, a ferroelectric such as PZT has a relative dielectric constant larger than SiO.sub.2 by two figures or more, and the parasitic capacitance can be sufficiently reduced.

FIG. 18 is a circuit diagram of a fourth embodiment of the DC--DC converter according to the present invention.

The difference of the present first embodiment from the above third embodiment resides in that the switch circuits and capacitor columns of the system A and system B are connected in parallel, and they are respectively driven by the clock signals .phi.1 to .phi.7 and .phi.1 to .phi.7 having inverse phases to each other (deviated by .tau./2 phase).

Note that, the fundamental operation of the circuit per se is similar to that of the third embodiment, and therefore an explanation thereof is omitted here.

In such a configuration, in the circuit of the system A, when for example the nodes ND1A and ND2A are discharged to the 0.25 V.sub.CC use power supply 60a via the switch 122A from V.sub.CC and 0.5 V.sub.CC to 0.75 V.sub.CC and 0.25 V.sub.CC, respectively, in the circuit of the system B, the charging operation is conversely carried out only by the same charge amount, therefore the both are cancelled. Accordingly, the supply of the charges from the 0.25 V.sub.CC use power supply 60a is 0, and there is an advantage that the 0.25 V.sub.CC use power supply 60a becomes very stable.

The ripple of the output node ND.sub.OUT accompanied with the load current I.sub.L can be lowered.

Many widely different embodiments of the present invention may be constructed without departing from the spirit and scope of the present invention. It should be understood that the present invention is not restricted to the specific embodiments described above.

Claims

1. An internal power supply circuit, comprising;

a plurality of charge accumulating means,

an input power supply terminal,

a boasted voltage output terminal,

a first switching means for connecting the plurality of charge accumulating means in parallel to each other in a first state,

a second switching means for connecting the plurality of charge accumulating means in series with each other in a second state,

wherein the first switching means comprises a third switching means and a fourth switching means, said third switching means connecting said charge accumulating means to a voltage supply line, and said fourth switching means connecting said charge accumulating means to ground; and

a control means for energizing the first switching means or the second switching means in response to the first state or the second state to connect the plurality of charge accumulating means between the first power supply terminal and the second power supply terminal, and for deenergizing the first switching means or the second switching means in response to the first state or the second state to disconnect the plurality of charge accumulating means between the first power supply terminal and the second power supply terminal, the control means repeating the energizing and the deenergizing,

a plurality of partial booster circuits each comprising one of said charge accumulating means connected between a first node and a second node,

wherein the second switching means holds in a non-conductive state the first node of a first partial booster circuit and the second node of a rear partial booster circuit in the first state and in a conductive state in the second state;

further wherein the third switching means and the fourth switching means are held in the conductive state and the second switching means is held in a non-conductive state in the first state; and

further wherein the first switching means comprised of the third switching means and the fourth switching means is held in the non-conductive state and the second switching means is held in a conductive state in the second state so as to raise the voltage between the input terminal and the output terminal.

2. An internal power supply circuit according to claim 1, wherein

the charge accumulating means are constituted by capacitors.

3. An internal power supply circuit according to claim 1, further comprising;

a biasing means connected to the second node of the initial stage partial booster circuit for holding the second node at a constant potential and

a rectifying means connected between the first node of the final stage partial booster circuit and a boosted voltage output terminal.

4. An internal power supply circuit according to claim 3, wherein the biasing means is constituted by a switching means set in the conductive state when the first switching means comprised of the third and fourth switching means is non-conductive.

5. An internal power supply circuit according to claim 3, wherein:

the first power supply terminal is a positive power supply terminal and the second power supply terminal is a negative power supply terminal,

the constant potential is the potential of the first power supply terminal,

the biasing means is a rectification element connected so that a direction from the first power supply toward the second node of the initial stage partial booster circuit becomes a forward direction, and

the rectification element is connected so that a direction from the first node of the final stage partial booster circuit toward the output terminal becomes the forward direction and supplies the positive boosted voltage to the output terminal.

6. An internal power supply circuit according to claim 3, wherein:

the first power supply terminal is a negative power supply terminal and the second power supply terminal is a positive power supply terminal,

the constant potential is the potential of the second power supply terminal,

the biasing means is a rectification element connected so that a direction from the second node of the first stage partial booster circuit toward the first power supply terminal becomes the forward direction, and

the rectification element is connected so that a direction from the output terminal to the first node of the final stage partial booster circuit becomes the forward direction and supplies the negative boosted voltage to the output terminal.

7. An internal power supply circuit according to claim 3, wherein;

the third switching means is constituted by a first conductivity type insulation gate type field effect transistor with a gate electrode connected to an input terminal of a first clock, with one diffusion layer connected to the first power supply, and with another diffusion layer connected to the first node of the partial booster circuit;

the fourth switching means is constituted by a first conductivity type insulation gate type field effect transistor with a gate electrode connected to an input terminal of a second clock, with one diffusion layer connected to the second power supply, and with another diffusion layer connected to the second node of the partial booster circuit; and

the second switching means is constituted by a second conductivity type insulation gate type field effect transistor with a gate electrode connected to the input terminal of a third clock.

8. An internal power supply circuit according to claim 3, wherein

the biasing means is constituted by a second conductivity type insulation gate type field effect transistor with a gate electrode connected to the input terminal of a third clock.

9. An internal power supply circuit according to claim 7, wherein an amplitude of the first clock is set larger than a potential difference between the first power supply terminal and the second power supply terminal.

10. An internal power supply circuit according to claim 7, wherein the first power supply terminal is a positive power supply terminal and the first conductivity type insulation gate type field effect transistor is an n-channel type transistor and is held at a higher level than the first power supply terminal voltage in a high level section of the first clock.

11. An internal power supply circuit according to claim 7, wherein the first power supply is a negative power supply terminal and the first conductivity type insulation gate type field effect transistor is a p-channel type transistor and is held at a lower level than the second power supply terminal voltage in a low level section of the first clock.

12. An internal power supply circuit according to claim 7, wherein the second conductivity type insulation gate type field effect transistor constituting the second switching means is formed in an independent well.

13. An internal power supply circuit according to claim 8, wherein the biasing means is a second conductivity type insulation gate type field effect transistor formed in the same well as that for the second conductivity type insulator gate type field effect transistors constituting part of the peripheral logic circuit.

14. An internal power supply circuit according to claim 1, wherein

the charge accumulating means are constituted by capacitors;

the capacitors are connected in series between the first and second power supply terminals and then are charged in the second state; and

the capacitors are connected in parallel between the second power supply terminal and a down voltage output terminal in the first state to thereby obtain a voltage between the first and second power supply terminal.

15. An internal power supply circuit according to claim 14, further comprising;

a switching means connecting to an external power supply between the voltage of the first power supply terminal and the voltage of the second power supply terminal, having at least one sub-power supply of a potential lower than the external power supply, and operationally connects the external power supply and the sub-power supply and

a means for sequentially switching the connection and nonconnection state from the switching means connected to the external power supply to cause charging and discharging of the capacitors.

16. An internal power supply circuit according to claim 15, further comprising a means for sequentially switching the connection and nonconnection state from the switching means connected to the sub-power supply to cause charging and discharging of the capacitors.

17. An internal power supply circuit according to claim 15, wherein

at least two arrangements of a plurality of capacitors which are switched between the serial connection and parallel connection based on a clock signal and

clock signals having inverse phases are supplied to the above at least two arrangements.

18. An internal power supply circuit according to claim 14, wherein the capacitors are composed of capacitors selected from ferroelectric capacitors, high dielectric capacitors, MIM (metal-insulator-metal) configuration capacitors, DRAM trench and stack capacitors, planar capacitors, external capacitors, and MIS (metal-insulator-semiconductor) gate capacitors.

19. An internal power supply circuit for boosting voltage comprising:

a plurality of charge storing devices;

a first plurality of transistors connected alternately and in series with said plurality of charge storing devices, wherein said series begins with a first transistor of said first plurality of transistors and ends with a last transistor of said first plurality of transistors;

a second plurality of transistors each of which is connected between a voltage supply line and a connection point between one of said plurality of charge storing devices and one of said first plurality of transistors; and

a third plurality of transistors each of which is connected between ground and a connection point between one of said plurality of charge storing devices and one of said first plurality of transistors;

wherein a gate of each of said first plurality of transistors, excluding said last transistor, is connected to a first clock line supplying a first clock signal;

further wherein a gate of each of said second plurality of transistors is connected to a second clock line supplying a second clock signal, different from said first clock signal; and

further wherein a gate of each of said third plurality of transistors is connected to a third clock line supplying a third clock signal, different from said second clock signal.

20. An internal power supply circuit according to claim 19, wherein said last transistor has a drain connected to an output terminal and a gate which is connected to said drain and to ground through a parasitic capacitance.

21. An internal power supply circuit according to claim 19, further comprising a clock circuit for generating said first, second and third clock signals, said clock circuit comprises a clock generator which comprises:

a first pair of transistors connected in series between ground and a voltage source line;

a second pair of transistors connected in series between ground and said voltage source line;

a capacitor connected between a first point and a second point, said first point being between said first pair of transistors and said second point being between said second pair of transistors; and

a clock output terminal connected to said second point, wherein said first clock signal is output to said clock output terminal.

22. An internal power supply circuit according to claim 21, wherein said first clock signal has a voltage amplitude greater than a voltage of said voltage source line.

23. An internal power supply circuit according to claim 21, wherein said clock circuit further comprises a plurality of flip-flops, wherein a first of said flip-flops has a set terminal which receives said second clock signal and an inverted output terminal which is connected to a gate of a first of said second pair of transistors.

24. An internal power supply circuit according to claim 23, wherein said first flip-flop has an output terminal which is connected to a set terminal of a second of said flip-flops, wherein said second flip-flop has a output terminal which is connected to a gate of a second of said second pair of transistors.

25. An internal power supply circuit according to claim 24, wherein said output terminal of said second flip-flop is connected to a set terminal of a third of said flip-flops, wherein said third flip-flop has an inverted output terminal which is connected to a first of said first pair of transistors.

26. An internal power supply circuit according to claim 24, wherein said second flip-flop has an inverted output terminal which is connected to a reset terminal of said first flip-flop.

27. An internal power supply circuit according to claim 25, wherein said inverted output terminal of said third flip-flop is connected to a reset terminal of said second flip-flop.

28. An internal power supply circuit according to claim 25, wherein said third flip-flop has an output terminal which is connected to a set terminal of a fourth of said flip-flops, said fourth flip-flop having an output terminal is connected to a second of said first pair of transistors.

29. An internal power supply circuit according to claim 28, wherein said output of said fourth flip-flop is connected through a delay element to a set terminal of a fifth of said flip-flops; said fifth flip-flop having an inverted output terminal which outputs said second clock signal.

30. An internal power supply circuit according to claim 29, wherein said inverted output terminal of said first flip-flop is connected to a reset terminal of a sixth of said flip-flops, said sixth flip-flop having an output terminal which outputs said third clock signal and an inverted output terminal which is connected through a delay element to a set terminal of said flip-flop.

31. An internal power supply circuit according to claim 30, wherein said output terminal of said sixth flip-flop is connected to a reset terminal of said fifth flip-flop.

32. An internal power supply circuit according to claim 19, wherein said first plurality of transistors are p-type transistors, and said second and third pluralities of transistors are n-type transistors.

33. An internal power supply circuit according to claim 19, wherein said first plurality of transistors are n-type transistors, and said second and third pluralities of transistors are p-type transistors.

34. An internal power supply circuit according to claim 19, wherein said charge storing devices are capacitors.

35. An internal power supply circuit according to claim 19, further comprising a power supply input terminal connected to a source of said first transistor.

36. An internal power supply circuit, according to claim 19, wherein:

the second plurality of transistors, when turned ON, connect the plurality of charge storing devices in parallel to said voltage supply line, and

the first plurality of transistors, when turned ON, connect the plurality of charge storing devices in series with each other.

37. An internal power supply circuit according to claim 19, wherein:

when said first plurality of transistors are turned ON and said second plurality of transistors are turned OFF, said first transistor acts as a biasing means for holding a connection node between said first transistor and one of said charge storing devices at a constant potential, and

said last transistor acts as a rectifying means connected between said series and a boosted voltage output terminal.

38. An internal power supply circuit according to claim 19, wherein said plurality of charge storing devices equals three charge storing devices.