Internal power voltage generating circuit in semiconductor memory device

Abstract

A method and circuit are disclosed for generating an internal power voltage in a semiconductor memory device. The method includes receiving an external power voltage in an internal power voltage generating circuit and activating a power-up signal during a first period in the applied external power voltage rising to a desired level, powering-up the internal power voltage in relation to the external power voltage during the first period, and continuing the power-up of the internal power voltage during a second period following the first period, the second period extending beyond the deactivation of the power-up signal until receipt of an active command signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit block diagram illustrating a voltage generation and supply in a conventional semiconductor memory device;

FIG. 2 is a graph comparing a rising slope of an internal power voltage generated at FIG. 1 with a rising slope of an external power voltage;

FIG. 3 is a graph illustrating a power-up slope reinforcement of the internal power voltage circuit according to a conventional semiconductor memory device;

FIG. 4 is a block diagram illustrating an internal power voltage generator according to an embodiment of the invention;

FIG. 5 is a block diagram illustrating an array internal power voltage generator according to a modified embodiment of the invention;

FIG. 6 is a block diagram illustrating a high voltage generator according to an extended embodiment of the invention;

FIG. 7 is a block diagram illustrating an operation control signal generating part adapted to generate an operation control signal to be applied to FIGS. 4 to 6;

FIG. 8 is a timing diagram illustrating an operation control signal generation related to FIG. 7;

FIG. 9 is a schematic diagram illustrating a power-up slope of the internal power voltage generated by an operation in FIG. 4.

FIG. 10 is a circuit diagram illustrating an active internal power voltage generator according to an embodiment of the invention;

FIG. 11 is a circuit block diagram illustrating a power-up slope reinforcement of the internal power voltage according to an embodiment of the invention; and

FIG. 12 is an operation timing diagram illustrating a signal generation related to FIG. 11.

Claims

1. An internal power voltage generating circuit comprising: an active control signal generating circuit adapted to select between an internal power voltage and an active command signal to generate an active control signal; andan internal power voltage generator adapted to power-up the internal power voltage in relation to an applied external power voltage during both first and second periods, the first period ending with deactivation of an applied power-up signal and the second period following the first period and ending with receipt of the active command signal.

2. The internal power voltage generating circuit of claim 1, wherein deactivation of the power-up signal is defined by transition of the power-up signal or its inverse from high to low.

3. The internal power voltage generating circuit of claim 1, wherein the active control signal generating circuit comprises a multiplexer gated by a selecting signal.

4. The internal power voltage generating circuit of claim 1, wherein the active command signal is an all bank pre-charge command signal.

5. The internal power voltage generating circuit of claim 3, wherein the active command signal is an all bank pre-charge command signal.

6. The internal power voltage generating circuit of claim 3, wherein the selecting signal is a PRE_MASTERD signal defined in relation to the power-up signal and the active command signal.

7. The internal power voltage generating circuit of claim 6, wherein the active command signal is an all bank pre-charge command signal.

8. The internal power voltage generator as claimed in claim 3 comprises a current mirror circuit comprising: a P type MOS transistor P1 receiving the external power supply and a P type MOS transistor P2, wherein the gates of P1 and P2 are commonly connected;an N type MOS transistor N1 gated by a target reference voltage and an N type MOS transistor N2, wherein the sources of N1 and N2 are commonly connected to the drain of an N type MOS transistor N3, wherein N3 is gated by the active control signal and the gate of N2 is connected to an output pad at which the internal power voltage is apparent;a P type MOS transistor P3 connected between the drains of N1 and N2 and a P type MOS transistor P4 gated by a voltage apparent at the drain of N1 and having a drain connected to the output pad at which the internal power voltage is apparent.

9. A power-up reinforcement circuit comprising: an oscillator adapted to generate an auto refresh enable pulse signal in relation to an applied power-up signal and a selecting signal; anda multiplexer adapted to generate an output pulse signal in relation to the selecting signal acting as a gating signal and the auto refresh enable pulse signal received from the oscillator;wherein the selecting signal is defined in relation to the power-up signal and an active command signal.

10. The power-up reinforcement circuit of claim 9, wherein the active command signal is an all bank pre-charge command signal.

11. A method of driving an internal voltage in a memory device, comprising: applying an auto refresh signal having an activation period that begins in relation to a transition of a power-up signal defining a voltage boosting period for an internal voltage and ends in relation to a transition of a selecting signal.

12. The method of claim 11, wherein the selecting signal is defined in relation to a received all bank precharge command.

13. A method of generating an internal power voltage in a semiconductor memory device, comprising: receiving an external power voltage in an internal power voltage generating circuit and activating a power-up signal during a first period in the applied external power voltage rising to a desired level;powering-up the internal power voltage in relation to the external power voltage during the first period; and,continuing the power-up of the internal power voltage during a second period following the first period, the second period extending beyond the deactivation of the power-up signal until receipt of an active command signal.

14. The method of claim 13, wherein the active command signal is an all bank pre-charge command signal.