Patent Application
20090067518
The present invention relates to an interpolator. More particularly, the present invention relates to an interpolation method and to the related device that is cost-effectively implemented in hardware using digital circuits of minimal complexity.
The method according to the invention is particularly suitable for the interpolation of fixed point signals, namely sampled signals whose values are represented using finite precision arithmetic.
Interpolation techniques are used in a number of technical fields. For example, interpolation techniques are used in digital receivers for channel estimation purposes. In fact, in many wireless or wired transmission systems the channel estimation is performed by means of training sequences, known to the receiver, that are multiplexed with the user data.
Training sequences are typically transmitted only in a part of the transmission frame. The remaining part of the frame is used for the transmission of user data or control information so that it is not possible to estimate the channel characteristics continuously over the whole frame. In order to estimate the channel characteristics in the parts of the frame where the user or control data are transmitted, some kind of interpolation is required.
In the following, as an example of technical application of an interpolation technique, reference is made to an interpolation method for the channel estimation in wireless communication systems that exploit multi-carrier transmission using the OFDM (Orthogonal Frequency Division Multiplexing) technique and multiple transmit/receive antennas (e.g. MIMO or Multiple Input Multiple Output). MIMO refers to the adoption of multiple antennas at both the transmitter and the receiver in order to create multiple spatial channels. These multiple spatial channels are used in parallel to transmit independent data streams and thus increase the transmission data rate or throughput.
OFDM is a modulation technique that distributes the data over a large number of subcarriers that are spaced apart at precise frequencies. The subcarrier frequency spacing is selected so that each subcarrier is orthogonal with respect to the others. In particular, orthogonality is achieved by selecting the subcarrier frequency spacing equal to the reciprocal of the useful symbol period. The benefits of OFDM are high spectral efficiency, resiliency to RF interference and multi-path propagation. OFDM is chosen over a single-carrier solution due to its lower complexity compared to time domain equalizers for high delay spread channels or high data rate systems. The OFDM modulation/demodulation can be efficiently implemented in the digital domain by using Fast Fourier Transforms (FFTs) at both the transmitter and the receiver.
In an OFDM system, the channel estimation is usually performed by sending training (or pilot) symbols on subcarriers known at the receiver. The insertion of the pilot sub-carriers can be described considering a two dimensional (2D) time-frequency grid, as shown in
The pilot symbols are overhead, and should be as few in number as possible in order to maximize the transmission rate of data symbols. Since the channel response can vary with time and with frequency, the pilot symbols can be scattered amongst the data symbols in order to provide a reliable estimation of the channel response over time and frequency. The set of subcarrier frequencies and OFDM symbols at which pilot symbols are inserted is referred to as a pilot pattern. With reference to
The pilot pattern can be inserted in various ways: for example, pilot symbols 10 can be distributed in the frequency domain by using part of or all the subcarriers of an OFDM symbol. Such a pilot pattern, denoted as TDM (Time Division Multiplexing) pattern and an example of which is represented in
A complementary pattern, denoted as FDM (Frequency Division Multiplexing) pattern and an example of which is represented in
In order to make a practical example of application of the interpolation method according to the invention, it is considered in the following a radio transmission scheme that is currently under study for the Long Term Evolution (LTE) of the UMTS Terrestrial Radio Access (UTRA). Said radio transmission scheme is described in detail in the technical report “3GPP TR 25.814”, in November 2005 (V 1.0.1, release 7) and available at the Internet website http://www.3gpp.org. It is clear that this is only one possible example of application of the invention and that other examples may be conceived.
The evolution of the UTRA radio interface, denoted with the acronym E-UTRA and also known as Super-3G system, is going to be designed to support mobile speeds of up to 120 km/h. In addition, the E-UTRA must be able to support higher user speeds of up to 350 km/h with reduced performance. The OFDM technique is one of the multiple access techniques considered for the application in downlink of E-UTRA. The downlink transmission scheme is based on conventional OFDM using a cyclic prefix, with a sub-carrier spacing Δf=15 kHz and a cyclic-prefix (CP) duration TCP=4.7/16.7 μs (short/long CP).
The E-UTRA air interface supports both frequency division duplex (FDD) and time division duplex (TDD) modes of operation. The sub-carrier spacing Δf is constant, regardless of the transmission bandwidth. To allow for operation in differently sized spectrum allocations, the transmission bandwidth is instead varied by changing the number of OFDM sub-carriers. The transmission bandwidth can be equal to 1.25, 2.5, 5, 10, 15, and 20 MHz, to which corresponds a number of OFDM occupied subcarriers equal to 76, 151, 301, 601, 901 and 1201 respectively.
The radio frame has a time duration of 10 ms and is divided into 20 equally sized sub-frames, which implies a sub-frame duration Tsub-frame=0.5 ms. Each sub-frame is composed by 7 or 6 OFDM symbols, depending on the used CP duration (short/long CP).
In each sub-frame is inserted a suitable number of pilot symbols that can be used for downlink channel estimation, downlink channel quality measurement, cell search and initial acquisition. The use of an adjustable pilot density in order to adapt to different channel properties (time/frequency selectivity) is also under study.
Basically, two pilot patterns are analyzed: TDM pilot pattern and scattered pilot pattern. An example of the TDM pilot pattern structure is shown in
An example of the scattered pilot pattern for E-UTRA is shown in
The TDM and scattered pilot patterns, respectively shown in
The E-UTRA radio interface is also intended to support multiple transmit/receive antennas. The baseline antenna configuration for MIMO is two transmit antennas at the cell site and two receive antennas at the user equipment. The possibility for higher-order downlink MIMO (more than two TX/RX antennas) is also under study. In order to support advanced antenna solutions such as MIMO, beam-forming and so on, multiple orthogonal pilot patterns are required to distinguish at the user. equipment receiver the different TX antennas, the different beams, etc. In such a case the computation of the channel coefficients becomes even more complex, thus requiring very fast and flexible interpolation circuits.
Given a certain pilot pattern, the estimation of the channel response in correspondence of the data symbols is performed by interpolation in the frequency and time domain. Considering that a wireless communication system, such the E-UTRA system, based on MIMO and OFDM is expected to provide high throughputs in the order of hundred of Mbit/s, and that the number of interpolated values varies as a function of the selected pilot pattern, it becomes important to define a flexible interpolation method which can be implemented with a simple and fast hardware circuit.
In general, linear interpolation is a mathematical operation for estimating values that lie between two known values or points. Given two known points A and B with cartesian coordinates A=(xA,yA) and B=(xB,yB), the ordinate yP of an interpolated point with abscissa xP is calculated with the well known formula for the linear interpolation:
The application of the equation (1) requires the execution of one multiplication and one division for each interpolated point and thus, due to the complexity of these operations from a circuital point of view, some form of simplification or approximation of the equation (1) is normally derived. The exact application of the equation (1) makes not feasible the implementation of a digital interpolation unit based on conventional logic circuitry, like the logic elements available in programmable logic devices (e.g. FPGA). In fact, the equation (1) requires the execution of floating point operations that can be only performed by a Digital Signal Processor (DSP), which often includes a floating point unit. However, the DSP approach has several drawbacks such as the bottleneck represented by the data transfer to the DSP and the high computation time of the interpolated values. On the other hand, the floating point computation ensures the maximum precision in the calculation of the interpolated values.
Interpolation methods are known in the art.
U.S. Pat. No. 5,886,911 describes a fast calculation method and its hardware apparatus for the linear interpolation. The linear interpolation method adopts a concept of a bisection method The position where the target point I is located is gradually approached by dividing the interval between the two known points X and Y in a number of segments equal to 2″ (i.e. a power of two).
U.S. Patent Application No. 2002/0152248 describes the implementation of a linear interpolator that is based on a multi-bit approach. The interpolation circuit proposed uses multi-bit values to eliminate the use of multipliers, making use of multiplexers and bit shift operations.
The Applicant has observed that the interpolation methods proposed in the art are not completely satisfactory.
For example, in respect of U.S. Pat. No. 5,886,911, the Applicant has observed that the number of interpolated points is not selectable by the user, but is constrained to take only certain values which are equal to 2n−1 where n is an integer number.
In respect of U.S. Patent Application No. 2002/0152248, the Applicant has remarked that the number of interpolated points is a fixed parameter that must be defined before the logical synthesis of the interpolation circuit.
The interpolation methods described in U.S. Pat. No. 5,886,911 and in U.S. Patent Application No. 2002/0152248 are therefore not suitable for channel estimation in communication systems, since in such an estimation the number of interpolated points should be dynamically varied in accordance with the selected pilot pattern.
The Applicant has tackled the problem of providing an interpolation method which can be cost-effectively implemented in hardware and which allows to vary flexibly the number of interpolated points without requiring any modification in the device implementing such a method.
It is therefore a first object of the present invention to provide a linear interpolation method wherein the number of interpolated points can be varied at any time without any effort.
According to the invention, the number of interpolated values is a run time parameter of the circuit and therefore, when for instance estimating channels in communication systems, it can be adapted to the selected pilot pattern, to the number of OFDM sub-carriers and in general to the propagation channel characteristics.
It is a second object of the present invention to provide a very simple and fast interpolation circuit that can be implemented with conventional logic circuitry, such as the basic logic elements that are available in programmable logic devices (e.g. FPGA).
The method according to the invention is particularly suitable to be used for estimating channels in communication systems, as it can be implemented with a limited number of logic gates using fast logic programmable devices, such as FPGA.
Moreover, the method according to the invention is particularly suitable for applications where it is required an interpolation between two values with a very short computation time.
It is a third object of the present invention to provide an interpolation method that can be cost-effectively implemented in hardware.
According to the invention, the function interpolating between two known values is a function formed by a plurality of contiguous steps, wherein the width and the height of the steps are calculated by shifting right by a predetermined number of bits the values of the distances on the abscissa and ordinate axis of the two known points. The predetermined number of bits depends on a resolution parameter representing the resolution according to which the width and the height of the steps are represented.
The method according to the invention further allows to define the resolution according to which the interpolated points are generated.
The method according to the invention is particularly suitable for channel estimation in communication systems, but it can also be more generally applied to a sampled signal, wherein the independent values represent a discrete spatial, time or frequency index and the dependent variables represent values of the sampled signal.
The device for implementing the method according to the invention comprises a limited number of logic gates which perform very simple operations, like for instance additions and right shifting.
Further features and advantages of the present invention will be made clearer by the following detailed description of some examples thereof, provided purely by way of example and without restrictive intent.
The detailed description will refer to the following Figures, wherein:
a, 2b and 2c respectively show an example of a TDM (Time Division Multiplexing) pilot pattern, of a FDM (Frequency Division Multiplexing) pilot pattern and of a scattered pilot pattern;
a and 3b respectively show an example of a TDM pilot pattern and of a scattered pattern in a sub-frame of an E-UTRA communication system;
In the method according to the invention, it is considered the interpolation between two known points A and B with cartesian co-ordinates A=(xA,yA) and B=(xB,yB) respectively. The values xA, xB, yA, yB are fixed point numbers, represented using a two's complement notation. The abscissas of the two known points represent the independent variable of the function that must be interpolated. The ordinates of the two known points represent the value of such function. For example in case of a sampled signal, the abscissa represents the discrete time index while the ordinate represents the value of the signal (e.g. the voltage) quantized over a suitable number of bits. More in particular, the abscissa may represents a discrete time or frequency index and the ordinate a transmission channel coefficient of a communication system.
The method according to the invention and the related interpolation device 1, shown in
Δx=xB−xA=N+1 (2)
As it will be clarified in the following, the value of N is an input parameter that can be varied depending on the desired resolution that is required in the interpolation process. The parameter N can be advantageously varied run-time without any change in the proposed interpolation method and device.
The first step of the proposed method consists in the calculation of the difference between the abscissas and the ordinates of the two known points A and B. By denoting these differences with Δx and Δy respectively and taking into account the relation (2), it is possible to write:
Δx=xB−xA=N+1 (3)
Δy=yB−yA (4)
The values of Δx and Δy are stored in two shift registers indicated with Rxand Ry respectively. The basic idea behind the proposed method consists in dividing the interval Δx and the interval Δy in a certain number K of sub-intervals. In the general case one of these sub-intervals has on the abscissa a shorter length with respect to the other K−1 sub-intervals. An example of division of the two segments Δx and Δy in sub-intervals is shown in
As shown in
The lengths δx and δy of the sub-intervals shown in
δx=Δx>>L (5)
δy=Δy>>L (6)
where the operator >> represents the right shift operation.
It can be noticed that the ratio m=Δy/Δx is the angular coefficient of the straight line that joins the two known points A and B. The ratio {tilde over (m)}=δy/δx between the two values obtained after the right shift operation provides an approximation of the angular coefficient. This approximation derives from the numerical truncation of the two values Δy and Δx when performing the right shift operation. The numerical truncation does not occur only when the two values Δy and Δx, expressed in binary notation, have both L zeros in the LSB (Least Significant Bit) positions. In such a particular case the values of m=Δy/Δx and {tilde over (m)}=δy/δx are equal and there is no approximation of the angular coefficient.
The value of L is chosen in order to have a non zero value for the sub-interval lengths δx and δy. Imposing the condition that the smaller between δx and δy must be represented with a minimum resolution of NBIT bits, the value of L can be calculated as follows:
L=min(MSBΔx,MSBΔy)+1−NBIT (7)
where the function min(.) takes the minimum of the two arguments, and MSBΔx, MSBΔy denote the most significant bit position of Δx (which is always a positive number) and of the absolute value of Δy respectively:
Δx→MSBΔx |Δy|→MSBΔy (8)
If the value calculated with the equation (7) is zero or negative, it means that no right shift has to be performed because one of the two values Δx or Δy is already represented with a number of bits equal or smaller than NBIT. A typical value of the parameter NBIT, that the simulations show to be optimal for the precision of the interpolation process, is an integer number between 2 and 4.
The last step of the interpolation algorithm is the generation of the ordinates of the interpolated points. The ordinates of the interpolated points are generated according to an interpolation function where the ordinate is kept constant for a certain number of points (hold phase) and then varied (variational phase). In particular, the ordinate of the interpolated points is kept constant for a group of δx consecutive points (hold step) and then varied of δy (variational step). Thus, the first set of δx points, including the known point A, has a constant ordinate equal to yA. The second set of δx consecutive points has an ordinate equal to yA+δy, the third set of δx consecutive points has an ordinate equal to yA+2·δy and so on. The generation of the interpolation function is repeated until N interpolated points are calculated. In other words, a hold phase and a variational phase, or vice versa, are alternated until all N interpolated points have been calculated. The variational step δy may be an incremental step or a decremental step, depending on the ordinates yA,yB of the points A,B to be interpolated.
The output signal y(x) of the interpolator can then be expressed with the following formula
where 1≦x≦N is the index of the interpolated point. In particular x=1 for the first interpolated on the right of the known point A and x=N for the last interpolated point that precedes the known point B. The mathematical operator └.┘ in the equation (9) provides the integer number less or equal than the argument
As an alternative embodiment, the first set of δx points may not include the known point A, and have an ordinate equal to yA+C, where C is a constant which can be positive or negative. Consequently the second set of δx consecutive points has an ordinate equal to yA+C+δy, and so on.
The flow chart of the proposed interpolation method is given in
More in particular, at step 100 the algorithm requires to input as data the Cartesian ordinates of two known points A e B, that is to say yA and yB. Moreover, there are further required the parameter NBIT, which represents the resolution according to which the smaller between δx and δy must be represented and the parameter N which represents the number of desired interpolated values.
At step 102, the differences Δx and Δy are computed according to the formulae (3) and (4).
At step 104, the most significant bit (MSB) position of the values representing Δx and Δy is calculated.
At step 106, the parameter L representing the numbers of positions according to which the two values Δx and Δy must be right-shifted according to formula (7) is computed.
At step 108, the lengths of the hold step δx and of the variational step δy are calculated according to right-shift operations (5) and (6).
At step 110, interpolated values are computed according to formula (9). Such a computation is repeated (step 112) until N interpolated points have been calculated; when the last point has been calculated, the procedure stops (step 114). This may happen during a hold phase.
With reference to
The interpolating device 1 receives as input the parameters yA, yB and N+1, which corresponds to the difference Δx, and provides as output the interpolation function y(x) which allows to calculate the N interpolated values between two known points A and B.
The interpolating device 1 comprises:
The second module 16 comprises, in turn, a first sub-module 14 for calculating the predetermined number of bits L and a second sub-module 17 for right shifting the distances Δx and Δy by said predetermined number of bits L.
The first module 20 comprises a subtractor 3 for calculating the difference Δy between yB and yA and a first block 5, which calculates the absolute value of said difference Δy.
The first sub-module 14 of the second module 16 comprises a second block 7 and a third block 9, which respectively calculate the most significant bit positions of N+1 and |Δy|, respectively referred to as MSBΔx and MSBΔy, and a fourth block 11, which calculates the minimum value between MSBΔx and MSBΔy, and the result of such a calculation is added to the value 1−NBIT in an adder 13 for providing the parameter L.
The second sub-module 17 of the second module 16 comprises two shift registers Rx and Ry, where the values Δx and Δy are stored, and where it is performed a right shift operation consisting in right shifting by L positions said values Δx and Δy.
The outputs δx and δy of the two registers Rx and Ry are inputted to a function generator 19 together with the input parameters yA and N. The output of the function generator 19 is the output function y(x).
With reference to
The output signal y(x) starts assuming the initial value yA, which is loaded in the register Rout at the beginning of the interpolation process. The output signal y(x) is kept constant for a group of δx consecutive points (hold step) and then is varied of δy (variation step). The increment is controlled by the enabling signal ENABLE provided by the counter 21. The generation of the function y(x) is then executed until N interpolated points are generated.
In order to better clarify the method of the invention two examples of application are hereinafter provided and represented in
Input Data Of The Interpolation Algorithm
First Step: Calculation of the Interval Lengths Δx and Δy
Δx=xB−xA=12−0=12 =11002
Δy=yB−yA=18−10=8=10002
Second Step: Calculation of L
L=min(MSBΔx,MSBΔy)+1−NBIT=min(3,3)+1−2=2
Third Step: Calculation of δx and δy
δx=Δx>>L=11002>>2=112=3
δy=Δy>>L=10002>>2=102=2
Fourth Step: Generation of the Interpolation Function. The ordinate of the interpolated points is kept constant for a group of δx consecutive points (hold step) and then varied of δy (variation step). The process starts from the known point A and is repeated iteratively until N interpolated points between A and B are generated. In this case all the steps of the interpolation function have the same length and each step is composed of δx=3 points with the same ordinate. It can be noticed that in this example there is no approximation in the calculation of the angular coefficient of the straight line that joins the known points A and B, so that m=Δy/Δx={tilde over (m)}=δy/δx=2/3. The generation of the interpolation function and the corresponding signal y(x) at the output of the interpolator device 1 is shown in
Input Data of the Interpolation Algorithm
First step: Calculation of the Interval Lengths Δx and Δy
Δx=xB−xA=11−0=11=10112
Δy=yB−yA=28−5=23=101112
Second step: Calculation of L
L=min(MSBΔx,MSBΔy)+1−NBIT=min(3,4)+1−2=2
Third step: Calculation of δx and δy
δx=Δx>>L=10112>>2=102=2
δy=Δy>>L=101112>>2=1012=5
Fourth Step: Generation of the Interpolation Function. The ordinate of the interpolated points is kept constant for a group of δx consecutive points (hold step) and then varied of δy (variational step). The process starts from the known point A and is repeated iteratively until N interpolated points between A and B are generated. In this example the last step of the interpolation function has a different length because it is composed of only one interpolated value, compared to the other steps that are composed of δx=2 points. It may be noticed that in this example the value of {tilde over (m)}=δy/δx=2.5 is an approximation in excess of the angular coefficient m=Δy/Δx=2.09 of the straight line that joins the know points A and B. This approximation reflects to the last interpolated point 18 that has an ordinate greater that the ordinate of the known point B. The generation of the interpolation function and the corresponding signal y(x) at the output of the interpolation device 1 is shown in
It is clear from the above detailed examples that the logic operations to be performed for implementing the method according to the invention (right-shifting, additions, calculation of most significant bit and so on) are very easy and fast to calculate. Moreover, these operations may be well performed by logic circuits of minimal complexity. In addition, the method is so conceived that the number of interpolated points between two known points may be varied every time that the interpolation method must be performed. This feature is very important when using the method according to the invention for channel estimation in communication systems, as pilot patterns may flexibly vary according to the transmission scheme adopted and therefore also the number of interpolated points may vary accordingly.
Although the method and apparatus of the present invention has been illustrated and described with regard to presently preferred embodiments thereof, it will be understood that numerous modifications and substitutions may be made to the embodiments described, and that numerous other embodiments of the invention may be implemented without departing from the spirit and scope of the invention as defined in the following claims.
For instance, the method according to the invention may also be applied to sampled signals, wherein the independent values represent a discrete spatial, time or frequency index and said dependent variables represent values of a sampled signal. For instance, in a computer graphics application, the abscissa of the points to be interpolated may represent the pixel position on the screen, while the ordinate may represent the colour level quantized on a suitable number of bits.
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/EP2005/014066 | 12/28/2005 | WO | 00 | 7/23/2008 |
