One or more embodiments of the subject matter described herein relate generally to connectors that electrically couple two or more other connectors or devices, and more specifically, to an interposer connector assembly.
The ongoing trend toward smaller, lighter, and higher performance electrical components and higher density electrical circuits has led to the development of surface mount technology in the design of printed circuit boards and electronic packages. Surface mountable packaging allows for the connection of a package, such as a computer processor, to pads on the surface of the circuit board rather than by contacts or pins soldered in plated holes going through the circuit board. Surface mount technology may allow for an increased component density on a circuit board, thereby saving space on the circuit board.
One form of surface mount technology includes interposer connectors. Interposer connectors may include a dielectric substrate with conductive contacts on both sides of the substrate. Conductive vias, or holes that are lined with a conductive material, extend through the substrate to electrically couple the contacts on opposite sides of the substrate. The contacts on each side of the substrate engage conductive members or terminals of different electronic packages, such as a processor and a circuit board, to electrically couple the electronic packages with each other.
The increasing demand for higher density electrical connections between the interposer connectors and the electronic packages to which the connectors mate has resulted in the contacts, conductive pads, and vias of the interposer connectors being placed relatively close together. Additionally, the differential electrical impedance characteristics of the conductive pathways that extend through the interposer connectors between the contacts are relatively low. As a result, the rate at which the interposer connectors communicate data may be limited. For example, the low differential impedance of the conductive pathways may result in significant noise and interference being induced by one conductive pathway on nearby conductive pathways.
A need exists for an interposer connector that reduces the noise and/or interference between conductive pathways in the connector while permitting relatively high data rates to be communicated through the connector.
In one embodiment, an interposer connector assembly is provided. The interposer connector assembly includes a substrate, conductive pads, and contacts. The substrate has opposite first and second sides with a conductive via extending through the substrate. The conductive pads are mounted to the first and second sides of the substrate and electrically coupled with each other by the via. The contacts are electrically joined with the conductive pads on the first and second sides of the substrate. The contacts protrude from the substrate to outer ends that are configured to engage conductive members of electronic packages that mate with the first and second sides of the substrate. A differential electrical impedance characteristic of a conductive pathway extending from the outer end of one of the contacts to the outer end of another one of the contacts is at least 65 Ohms.
In another embodiment, another interposer connector assembly is provided. The interposer connector assembly includes a substrate, conductive pads, and contacts. The substrate has opposite first and second sides with a conductive via extending through the substrate. The conductive pads are mounted to the first and second sides of the substrate and electrically coupled with each other by the via. The contacts are electrically joined with the conductive pads on the first and second sides of the substrate. The contacts protrude from the substrate to outer ends that are configured to engage conductive members of electronic packages that mate with the first and second sides of the substrate. The via of the substrate has an inside diameter dimension of 0.3 millimeters or less.
In another embodiment, another interposer connector assembly is provided. The interposer connector assembly includes a substrate, conductive pads, and contacts. The substrate has opposite first and second sides with a conductive via extending through the substrate. The conductive pads are mounted to the first and second sides of the substrate and electrically coupled with each other by the via. The contacts are electrically joined with the conductive pads on the first and second sides of the substrate. The contacts protrude from the substrate to outer ends that are configured to engage conductive members of electronic packages that mate with the first and second sides of the substrate. The contacts are elongated from fixation ends mounted to the conductive pads to the outer ends. The conductive pads protrude beyond the fixation ends by less than 0.2 millimeters along the first and second sides of the substrate.
In the illustrated embodiment, the interposer connector assembly 102 is a board-to-board interconnect system that electrically joins electronic packages 104, 106, such as circuit boards. The interposer connector assembly 102 may be mounted to the second electronic package 106. A housing 108 is used to position the interposer connector assembly 102 with respect to the first and second electronic packages 104, 106. The housing 108 may completely surround the perimeter of the interposer connector assembly 102, or alternatively, may have separate components provided at predetermined portions of the interposer connector assembly 102, as shown in
The interposer connector assembly 102 includes a dielectric substrate 118 having opposite sides 120, 122. The substrate 118 may include or be formed from a material having a relatively low dielectric constant. For example, the substrate 118 may be formed from FR-4 material having a dielectric constant of approximately 4.0. Alternatively, the substrate 118 may include or be formed from a material having a lower dielectric constant. By way of example only, the substrate 118 may be formed from Nelco-13SI material having a dielectric constant of approximately 3.2. Using a substrate 118 with a lower dielectric constant may increase a differential electrical impedance characteristic of conductive pathways that extend through the substrate 118. Conductive contacts 110 are coupled to the sides 120, 122 and arranged in a contact array 112 on each side 120, 122. The contacts 110 may be elongated conductive bodies that extend from the sides 120, 122 as cantilevered beams. The first electronic package 104 has a mating surface 114 that includes conductive members 220 (shown in
In accordance with one or more embodiments described herein, relative dimensions of and spacing between conductive components, such as the vias 204, conductive pads 210, 212, and the contacts 110 are varied to reduce differential electrical impedance characteristics of the interposer connector assembly 102. For example, the conductive components may be spaced farther apart and the size of the conductive components may be reduced to increase the differential electrical impedance characteristics of conductive pathways that include and extend through coupled pairs of the contacts 110 and conductive pads 210, 212, and the associated vias 204. Increasing the differential electrical impedance characteristics may reduce the noise and/or interference that are induced on one or more conductive pathways by a nearby conductive pathway when relatively high data rates are communicated.
The substrate 118 of the interposer connector assembly 102 includes the conductive pads 210, 212 formed on the opposite sides 120, 122 of the substrate 118. The conductive pads 210, 212 may be metal or metal alloys, such as copper (Cu) or copper alloys, that are deposited on the sides 120, 122 and then selectively etched. In the illustrated embodiment, the vias 204 are electrically joined with the conductive pads 210, 212 so that the vias 204 provide conductive pathways between the conductive pads 210, 212.
Dielectric layers 206, 208 are disposed outside of the conductive pads 210, 212. For example, dielectric layers 206, 208 may be deposited onto the pads 210, 212 such that the conductive pads 210, 212 are located between the dielectric layers 206, 208 and the substrate 118. The dielectric layers 206, 208 may be formed from or include an adhesive that binds a plating mask 200, 202 with the conductive pads 210, 212. The dielectric layers 206, 208 have thickness dimensions 230. The thickness dimension 230 of the dielectric layer 206 may be the same as or different from the thickness dimension 230 of the dielectric layer 208. In accordance with one embodiment, the thickness dimensions 230 of the dielectric layers 206, 208 are increased in size in order to separate the contacts 110 from the conductive pads 210, 212. Increasing the separation between the contacts 110 and the conductive pads 210, 212 may increase a differential electrical impedance characteristic of conductive pathways that extend between contacts 110 on opposite sides 120, 122 of the substrate 118 and that include the conductive pads 210, 212. By way of example only, the thickness dimension 230 may be at least 0.05 millimeters. In another example, the thickness dimension 230 may be at least 0.0508 millimeters. In another embodiment, the thickness dimension 230 may be at least 0.06 millimeters.
The plating mask 200, 202 includes layers that are deposited onto the dielectric layers 206, 208 to protect one or more areas located between the plating mask 200, 202 and the substrate 118 from being removed or etched. For example, the plating mask 200, 202 may include or be formed from a dielectric material, such as a photoresist, that is deposited and then crosslinked to provide a protective layer that prevents the conductive pads 210, 212 from being removed through an etching process.
In the illustrated embodiment, the dielectric layers 206, 208 and the plating masks 200, 202 may be selectively etched so that portions of the dielectric layers 206, 208 are removed and filled or plated with a metal or metal alloy to form conductive interconnects 214, 216. The interconnects 214, 216 may be similar to the vias 204 in that the interconnects 214, 216 provide conductive pathways. The conductive pathways of the interconnects 214, 216 electrically couple the conductive pads 210, 212 with the contacts 110.
The contacts 110 are mounted to the plating masks 200, 202 such that the contacts 110 are electrically coupled with the interconnects 214, 216. Alternatively, the contacts 110 may be mounted to the conductive pads 210, 212. The contacts 110 are elongated between fixation ends 228 and outer ends 226. The fixation ends 228 may be coupled to the plating masks 200, 202 and the outer ends 226 may be free ends which are configured for engagement with the conductive pads 210, 212. For example, the contacts 110 may be joined to the plating masks 200, 202 as cantilevered beams.
In one embodiment, after the contacts 110 are mounted to the plating masks 200, 202, a conductive plating layer 232 is deposited onto the contacts 110 and the plating masks 200, 202. For example, a metal or metal alloy may be deposited onto the contacts 110 and the plating masks 200, 202. The plating layer 232 may be deposited onto the dielectric layers 206, 208 but removed by an etching process. A differential electrical impedance characteristic of a conductive pathway that extends between the contacts 110 on opposite sides 120, 122 of the substrate 118 and that includes the plating layers 232 and the contacts 110 may be related to the size of the plating layers 232. For example, reducing the size and/or thickness of the plating layers 232 deposited onto the plating masks 200, 202 may increase the differential electrical impedance characteristic of the conductive pathway. As described below, the size of the plating layers 232 is reduced in one embodiment by decreasing the size of the plating masks 200, 202 relative to the contacts 110.
In operation, the outer ends 226 are engaged by conductive members 220, 222 of the first and second electronic packages 104, 106 when the first and second electronic packages 104, 106 mate with the opposite sides 120, 122 of the interposer connector assembly 102. The conductive members 220, 222 may be conductive pads and/or traces of the electronic packages 104, 106.
The conductive members 220, 222 are electrically joined with each other by the interposer connector assembly 102. For example, the interposer connector assembly 102 provides a conductive pathway that couples the conductive members 220, 222. The conductive pathway includes the contacts 110, the conductive pads 210, 212, the interconnects 214, 216, the conductive plating layers 232, and the via 204 in the illustrated embodiment. Alternatively, the conductive pathway may include different components and/or a different number of components. For example, the conductive pads 210, 212 may be coupled with the via 204 and/or the contacts 110 may be mounted to the conductive pads 210, 212 without using the interconnects 214, 216 to electrically couple the contacts 110 with each other.
The via 204 has an inside diameter dimension 224 within the substrate 118. For example, the via 204 may have the inside diameter dimension 224 that defines the width of the via 204 within the thickness of the substrate 118. The inside diameter dimension 224 may establish the thickness of the conductive material in the via 204 through the thickness of the substrate 118. In one embodiment, the inside diameter dimension 224 is reduced to increase a differential electrical impedance characteristic of a conductive pathway that extends through the interposer connector assembly 102 and includes the contacts 110, the conductive pads 210, the interconnects 214, 216, the conductive plating layers 232 and the via 204. By way of example only, the inside diameter dimension 224 may be smaller than 16 mils, or 0.4 millimeters. In another example, the inside diameter dimension 224 may be 12 mils, or 0.3 millimeters, or less.
The conductive pads 210 are elongated along longitudinal directions 302 that are oriented along or parallel to the side 120 of the substrate 118. The conductive pads 210 have length dimensions 324 that are measured between opposite ends 326, 328 of the conductive pads 210 along the longitudinal directions 302. The conductive pads 210 have width dimensions 330 that are measured between opposite sides 332, 334 of the conductive pads 210 along lateral directions 306 that are oriented perpendicular to the longitudinal directions 302.
Conductive pads 210 that are adjacent or neighbor each other along the longitudinal directions 302 are separated from each other by a first separation dimension 304. Conductive pads 210 that are adjacent or neighbor each other along the lateral directions 306 are separated by a second separation dimension 308. As shown in
The vias 204 associated with the conductive pads 210 are separated from each other in the array 300 by first and second pitch dimensions 310, 312 along the longitudinal and lateral directions 302, 306. The pitch dimensions 310, 312 may differ or be approximately the same. One or more of the pitch dimensions 310, 312 may be increased to increase a differential electrical impedance characteristic of the conductive pathways that extend through the vias 204 and include the contacts 110 (shown in
Increasing one or more of the separation and/or pitch dimensions 304, 308, 310, 312 may reduce the pin count of the interposer connector assembly 102, or the number of conductive pathways extending through the interposer connector assembly 102 between contacts 110 (shown in
As shown in
One or more of the border dimensions 314, 320 may be reduced in size to increase a differential electrical impedance characteristic of the conductive pathway that extends through the conductive pads 210, 212 (shown in
The contact 110 may extend from one edge 400 to an opposite edge 402 along the longitudinal direction 302. The contact 110 has a length dimension 404 that is measured between the edges 400, 402 along the longitudinal direction 302. The contact 110 extends between opposite sides 406, 408 along the lateral direction 306. The contact 110 may have several different width dimensions 410 that are measured between the sides 406, 408 along the lateral direction 306. For example, as shown in
The width dimension 330 of the conductive pad 210 to which the contact 110 is electrically coupled is no larger than the width dimension 410 of the contact 110 in one embodiment. For example, the width dimension 330 of the conductive pad 210 may be smaller than the width dimension 410c of the contact 110 in the fixation end 228 of the contact 110. In another example, the width dimension 330 of the conductive pad 210 may be no larger than the largest width dimension 410 of the contact 110. Alternatively, the width dimension 330 may slightly exceed the width dimension 410 of the contact 110. For example, the width dimension 330 of the conductive pad 210 may be 110% or less of the width dimension 410 of the contact 110. In another example, the width dimension 330 may be no more than 108% or 105% of the width dimension 410. Reducing the size of the conductive pad 210 relative to the size of the contact 110 may increase a differential electrical impedance characteristic of the conductive pathway that includes the contact 110 and the conductive pad 210. For example, reducing the width dimension 330 of the conductive pad 210 relative to the width dimension 410 of the contact 110 may increase the differential electrical impedance characteristic of the conductive pathway that electrically couples the contacts 110 on the opposite sides 120, 122 (shown in
In the illustrated embodiment, the conductive pad 210 is formed on the substrate 118 such that the end 328 of the conductive pad 210 does not extend beyond the edge 402 of the contact 110. For example, the end 328 of the conductive pad 210 may be approximately coextensive with the edge 402 of the contact 110 such that the end 328 is not visible in the view shown in
As described above, the size of the plating mask 200 may be reduced to increase a differential electrical impedance characteristic of the conductive pathway that extends between the contacts 110 on the opposite sides 120, 122 (shown in
In the illustrated embodiment, the plating mask 200 is formed on the substrate 118 such that the back edge 502 of the plating mask 200 does not extend beyond the edge 402 of the contact 110. For example, the back edge 502 may be approximately coextensive with the edge 402 such that the back edge 502 is not visible in the view shown in
As described above, the dimensions and/or relative sizes of one or more conductive components of the interposer connector assembly 102 may be reduced in size and/or the relative positions of the components may be moved. Changing the relative positions and/or reducing the dimensions and/or sizes of the conductive components can increase differential electrical impedance characteristics of the conductive pathways that extend through the interposer connector assembly 102. For example, the differential electrical impedance characteristic of a conductive pathway that includes contacts 110 on opposite sides 120, 122 of the substrate 118, conductive pads 210, 212, the interconnects 214, 216, plating layers 232 on the plating masks 200, 202, and the via 204 may be at least 65 Ohms. In another example, the differential electrical impedance characteristic may be at least 80, 85, or 90 Ohms. These conductive pathways may be the conductive pathways that carry high speed data signals through the interposer connector assembly 102. By increasing the differential electrical impedance characteristics of the conductive pathways, high data rates may be used to communicate data through the interposer connector assembly 102.
Dimensions, types of materials, orientations of the various components, and the number and positions of the various components described herein are intended to define parameters of certain embodiments, and are by no means limiting and are merely example embodiments. Many other embodiments and modifications within the spirit and scope of the claims will be apparent to those of skill in the art upon reviewing the above description. The scope of the subject matter described herein should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein.” Moreover, in the following claims, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects. Further, the limitations of the following claims are not written in means-plus-function format and are not intended to be interpreted based on 35 U.S.C. §112, sixth paragraph, unless and until such claim limitations expressly use the phrase “means for” followed by a statement of function void of further structure.
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