1. Field of the Invention
The present invention relates to an interrupt coalescing scheme, more specially, to an interrupt coalescing scheme for high throughput TCP offload engine and method thereof.
2. Description of the Prior Art
The computer performance has increased in recent years, causing the demands on computer networks increased significantly; faster computer processors and higher memory capabilities drive the needs for networks with high bandwidth capabilities to enable high speed transfer of significant amounts of data.
The communication speed in networking systems has surpassed the growth of microprocessor performance in many network devices. For example, Ethernet has become the most commonly used networking protocol for local area networks. The increase in speed from 10 Mb/s Ethernet to 10 Gb/s Ethernet has not been matched by a commensurate increase in the performance of processors used in most network devices.
As speed has increased, design constraints and requirements have become more and more complex with respect to following appropriate design and protocol rules and providing a low cost, commercially viable solution. This phenomenon has produced an input/output (I/O) bottleneck because network device processors cannot always keep up with the rate of data flow through a network. An important reason for the bottleneck is that the TCP/IP stack is processed at a rate slower than the speed of the network. The processing of TCP/IP has typically been performed by software running on a central processor of a server. Reassembling out-of-order packets, processing interrupts and performing memory copies places a significant load on the CPU. In high-speed networks, such a CPU may need more processing capability for network traffic than for running other applications.
A TCP/IP offload engine (TOE) helps to relieve this I/O bottleneck by removing the burden (offloading) of processing TCP/IP from the microprocessor(s) and I/O subsystem. A TCP/IP offload engine has typically been implemented in a host bus adapter (“HBA”) or a network interface card (“NIC”).
If TOE throughput cannot be sufficiently increased simply by increasing processor clock speeds, then other techniques will have to be employed if the desired increased throughput is to be achieved. One technique for increasing throughput involves increasing the width of the processor's data bus and using a wider data bus and ALU. Although this might increase the rate at which certain TCP/IP offload engine functions are performed, the execution of other functions will still likely be undesirably slow due to the sequential processing nature of the other TCP/IP offload tasks. Other computer architecture techniques that might be employed involve using a multi-threaded processor and/or pipelining in an attempt to increase the number of instructions executed per unit time, but again clock rates can be limiting. It is envisioned that supporting the next generation of high-speed networks will require pushing the clock speeds of even the most state-of-the-art processors beyond available rates. Even if employing such an advanced and expensive processor on a TCP/IP offload engine were possible, employing such a processor would likely be unrealistically complex and economically impractical.
In view of the above problems associated with the related art, it is an object of the present invention to provide an interrupt coalescing scheme for high throughput TCP offload engine. An interrupt descriptor queue is used to store the information of each interrupt event when CPU is not fast enough to handle every interrupt individually. Thus the invention improves the performance of networking process by reducing number of interrupts.
It is another object of the present invention to provide a method of handling an interrupt coalescing scheme for high throughput TCP offload engine. The method searches the interrupt event descriptor in the interrupt queue header for fast efficiently throughput of data networking.
It is another object of the present invention to provide a method of handling an interrupt coalescing scheme for high throughput TCP offload engine. TCP offload engine saves information in interrupt event descriptors and the software may process multiple interrupt queue descriptors asynchronously within one interrupt context.
Accordingly, one embodiment of the present invention is to provide an interrupt coalescing scheme for high throughput TCP offload engine, which includes: at least one interrupt descriptor queue receiving and storing a plurality of interrupt events from a TCP offload engine, then interrupt events executed by a software, wherein the interrupt descriptor queue comprising: a plurality of interrupt event descriptors storing runtime information of interrupt events copied from a plurality of TCP queue's headers in the TCP offload engine; and an interrupt queue header containing and managing a plurality of event descriptor pointers for queuing, wherein event descriptor pointers point to interrupt event descriptors.
In addition, a method of handling interrupts in an interrupt coalescing scheme includes: a TCP offload engine copying a TCP connection information and a TCP queue's header information to an interrupt event descriptor in an interrupt descriptor queue; a descriptor write pointer in an interrupt queue header is incremented to indicate a new interrupt event descriptor has been added; and a software receiving an interrupt signal and reading at least one interrupt event descriptor in the interrupt descriptor queue.
Other advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings wherein are set forth, by way of illustration and example, certain embodiments of the present invention.
The foregoing aspects and many of the accompanying advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
The present invention provides an interrupt coalescing scheme for high throughput TCP offload engine (TOE).
The Interrupt Descriptor Queue Unit 50 is designed to offload host TCP processing. Referring
Conventionally, in state S22, the TCP queue header stores the runtime information of this TCP connection and it could be updated before processed by software, which is executed by processing unit. Therefore, an interrupt descriptor queue scheme for high speed TCP receiving data assembly is designed. An interrupt descriptor queue is used wherein the interrupt queue header and interrupt event descriptor format are illustrated as
The interrupt queue header 31 includes: IQDR_BADR (28 bits) presenting an interrupt queue descriptor ring base address, 16 bytes aligned and software written; IQDR_SIZE (4 bits) presenting an interrupt queue descriptor ring size, calculated as 2̂(IODR_SIZE+3), and software written; IQDR_Wptr presenting an interrupt queue descriptor ring write pointer and software written; IQDR_Rptr presenting an Interrupt queue descriptor ring read pointer and software written; and several interrupt event descriptor pointers.
In the interrupt queue header 31, interrupt queue read pointer points to an interrupt descriptor whose frame includes: a WinSize (16 bits) presenting the WinSize from TCP queue header; a TQDR_Wptr (16 bits) presenting TQDR_Wptr from TCP queue header; CTL (1 bit) presenting CTL bit from TCP queue header; OSQ (1 bit) presenting OSQ bit from TCP queue header; SAT (1 bit) presenting SAT bit from TCP queue header; IPOPT (1 bit) presenting IPOPT bit from TCP queue header; ABN (1 bit) presenting ABN bit form TCP queue header; DACK (1 bit) presenting DACK bit from TCP queue header; TCPQID (8 bit) presenting TCP queue id that this interrupt event is about; TotalPktSize (17 bits) presenting TotalPktSize from TCP queue header; Sequence (32 bits) presenting Sequence from TCP queue header; Acknowledge (32 bits) presenting Acknowledge from TCP queue header; SeqCnt (16 bits) presenting SeqCnt from TCP queue header; and AckCnt (16 bits) presenting AckCnt from TCP queue header.
Accordingly, Whether a TCP packet matches a TCP queue or not is by comparing source IP address, destination IP address, source TCP port number and destination TCP port number. When a received TCP packet matches, it will be appended to the end of TCP queue, and TCP queue header will be updated accordingly. A variety of circumstances are defined when interrupts should be triggered and related TCP queue header information will be copied to interrupt event descriptor.
Accordingly, the present invention provides a method of handling interrupt event descriptor coalescing scheme for high throughput TCP offload engine. Referring to
In STEP 41 triggering the interrupt has following events;
By providing above information of TCP queue and connection status, the software is capable to handle multiple TCP interrupt events saved in interrupt event descriptors without missing any interrupt event when the CPU cannot catch up the speed of the data transmitting from high speed networking system. With this interrupt coalescing mechanism, the host system can reach very high TCP transport throughput.
While the invention is susceptible to various modifications and alternative forms, a specific example thereof has been shown in the drawings and is herein described in detail. It should be understood, however, that the invention is not to be limited to the particular form disclosed, but to the contrary, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the appended claims.