Patent Application
20100250811
This application is based on and claims priority under 35 U.S.C. 119 from Japanese Patent Application No. 2009-72078, which was filed on Mar. 24, 2009.
1. Technical Field
The present invention relates to an interrupt controller and an image-forming device.
2. Related Art
There are known techniques for controlling the timing of an interrupt request that occurs in response to data reception.
According to an aspect of the invention, there is provided an interrupt controller including: a timer that repeatedly measures a predesignated length of time; an interrupt request unit that, when data is received by a receiving unit while the timer is measuring the length of time, outputs an interrupt request after measurement of the length of time is completed; a measurement unit that measures a frequency of data reception of the receiving unit; and an updating unit that changes the length of time measured by the timer so as to be shorter than the predesignated length of time when the frequency of reception measured by the measurement unit exceeds a threshold frequency.
Exemplary embodiment(s) of the present invention will be described in detail based on the following figures, wherein:
Configuration
Next, the configuration of communication controller 14 will be described. Communication controller 14 is one example of the interrupt controller of the present invention. As shown in
Interrupt controller 42 includes status register 421 and mask register 422. Status register 421 stores interrupt cause information, a count value, and a received packet count. The interrupt cause information is information indicating the cause of an interrupt that occurs in response to data reception by packet-receiving unit 41. The count value is a value that indicates the length of a period during which no packets are received by packet-receiving unit 41. The received packet count indicates the number of packets received by packet-receiving unit 41 during a period starting from a unit time before the point at which the cause of an interrupt occurs. The received packet count is counted and stored by interrupt controller 42. In addition, the received packet count is utilized as a value that represents the frequency of data reception of packet-receiving unit 41. That is, interrupt controller 42 is one example of the reception frequency measurement unit of the present invention and measures the frequency of data reception of packet-receiving unit 41. In addition, mask register 422 stores an interrupt mask bit. The interrupt mask bit is information that controls the output of an interrupt request. For example, if the interrupt mask bit is “0”, the output of an interrupt request is permitted. On the other hand, if the interrupt mask bit is “1”, the output of any new interrupt request is prohibited. In addition, in the following descriptions, prohibiting the output of an interrupt request will be referred to as “masking the interrupt request” and permitting the output of an interrupt request will be referred to as “unmasking the interrupt request”.
Operation
Next, operations of image-forming device 1 according to an aspect of the present exemplary embodiment will be described. In image-forming device 1, an interrupt request process is implemented in response to the reception of a packet. First, an outline of the interrupt request process will be described with reference to the time chart shown in
When packet-receiving unit 41 receives packet Pa at time instant T1, packet Pa is DMA (Direct Memory Access) transferred to main memory 12. DMA transfer refers to a process in which communication controller 14 transfers data to main memory 12 for storage through a route that does not involve CPU 11. When packet Pa is received by packet-receiving unit 41, the interrupt controller 42 stores interrupt cause information Na, which indicates the cause of an interrupt that occurs in response to reception of packet Pa, in status register 421. Interrupt cause information Na includes an address that indicates the storage location of packet Pa within main memory 12. When interrupt cause information Na is stored in status register 421, the interrupt status is switched to “On”.
When the DMA transfer is completed at time instant T2, interrupt controller 42 waits until timer 43 finishes measuring length of time F as the interrupt mask bit stored in mask register 422 has been set to “1”. Then, when timer 43 finishes measuring length of time F at time instant T3, interrupt controller 42 sets the interrupt mask bit stored in mask register 422 to “0” and unmasks the interrupt request. Then, interrupt controller 42 outputs an interrupt request signal. That is, when data is received by packet-receiving unit 41 while timer 43 is measuring the length of time, interrupt controller 42 outputs an interrupt request after measurement of the length of time is completed. In this way, when the interrupt request signal responding to the reception of packet Pa is output, the interrupt status is turned off. Then, interrupt controller 42 sets the mask bit stored in mask register 422 to “1” and again masks the interrupt request.
When the interrupt request signal is output from interrupt controller 42 at time instant T3, the interrupt request signal is supplied to CPU 11. When the interrupt request signal is supplied at time instant T4, CPU 11 starts interrupt process Ra corresponding to interrupt cause information Na stored in status register 421. In interrupt process Ra, for example, packet Pa, which is stored in the address contained in interrupt cause information Na, is read from main memory 12, and after being read, packet Pa is supplied to image output device 17 via image processor 15. That is, CPU 11 is one example of the processor of the present invention and, when an interrupt request is output by interrupt controller 42, implements a process of supplying the image data received by receiving unit 41 to image output device 17 as an interrupt process corresponding to the interrupt request. When interrupt process Ra is completed at time instant T5, interrupt controller 42 erases interrupt cause information Na from status register 421. Subsequently, when packet-receiving unit 41 receives packet Pb at time instant T6, interrupt controller 42 and CPU 11 implement a process similar to the process described above.
Next, a process of interrupt controller 42 will be described concretely with reference to the flowchart shown in
If no packets were received while timer 43 was measuring length of time F (step S13: NO), when timer 43 restarts measurement of length of time F, interrupt controller 42 sets the interrupt mask bit stored in mask register 422 to “1” and masks the interrupt request (step S14). Subsequently, interrupt controller 42 adds 1 count to the count value stored in status register 421 (step S15). Subsequently, interrupt controller 42 determines whether the count value stored in status register 421 exceeds a threshold (step S16). If the count value is below the threshold (step S16: NO), interrupt controller 42 returns to step S11. On the other hand, if the count value exceeds the threshold (step S16: YES), interrupt controller 42 increases the set value stored in timer register 430 to increase the length of time to be measured by timer 43 (step S17). As described above, the count value is a value that represents the length of a period during which no data is received by packet-receiving unit 41. That is, interrupt controller 42 is one example of the changing unit of the present invention and changes the length of time measured by timer 43 to be longer than the predesignated length of time if no data is received by packet-receiving unit 41 for a length of time exceeding the threshold related to the length of time.
Subsequently, interrupt controller 42 determines whether the set value stored in timer register 430 exceeds the upper limit (step S18). If the set value stored in timer register 430 is below the upper limit (step S18: NO), interrupt controller 42 returns to step S11. On the other hand, if the set value stored in timer register 430 exceeds the upper limit (step S18: YES), once a new packet is received by packet-receiving unit 41 (step S19), interrupt controller 42 sets the interrupt mask bit stored in mask register 422 to “0” to unmask the interrupt request (step S20) and outputs the interrupt request signal (step S21). That is, when data is received by packet-receiving unit 41 while timer 43 is measuring a length of time, which is longer than a predetermined maximum length of time, interrupt request unit 42 outputs the interrupt request before the measurement of the length time is completed. Subsequently, interrupt controller 42 returns the set value stored in timer register 430 to the initial value (step S22) and then returns to step S11 again. That is, when data is received by packet-receiving unit 41 while timer 43 is measuring a length of time, which is longer than the predetermined maximum length of time, interrupt controller 42 changes the length of time measured by timer 43 to match the predesignated length of time.
On the other hand, in step S13, if a packet was received while timer 43 was measuring length of time F (step S13: YES), interrupt controller 42 outputs an interrupt request signal (step S23). Then, when timer 43 restarts measurement of length of time F, interrupt controller 42 sets the interrupt mask bit stored in mask register 422 to “1” and masks the interrupt request (step S24). Subsequently, interrupt controller 42 determines whether the frequency of packet reception is high based on the received packet count stored in status register 421 (step S25). For example, if the received packet count stored in status register 421 is below a threshold, interrupt controller 42 determines that the frequency of packet reception is low (step S25: NO) and returns to step S11 again. On the other hand, if the received packet count stored in status register 421 exceeds the threshold, interrupt controller 42 determines that the frequency of packet reception is high (step S25: YES). In this case, interrupt controller 42 decreases the set value stored in timer register 430 to shorten the length of time to be measured by timer 43 (step S26) and then returns to step S11 again. That is, if the measured frequency of reception exceeds the threshold related to the frequency of reception, interrupt controller 42 changes the length of time measured by timer 43 so as to be shorter than the predesignated length of time.
The above has been a description of an exemplary embodiment, but details of the exemplary embodiment may vary as follows. Moreover, each of the following modified examples may be combined as appropriate.
In the exemplary embodiment, timer 43 measures the length of time even while no data is being received by packet-receiving unit 41, but timer 43 may measure the length of time in response to data reception by packet-receiving unit 41.
As in the exemplary embodiment, when packet-receiving unit 41 receives packet Pa at time instant T1, a DMA transfer of packet Pa is implemented during the period from time instant T1 to time instant T2. When the DMA transfer is completed at time instant T2, interrupt controller 42 outputs an interrupt request signal. Interrupt controller 42 also starts timer 43 at time instant T2. This operates timer 43 and starts the measurement of length of time F. That is, when the interrupt request is output by interrupt controller 42, timer 43 measures a predesignated length of time from the point at which the interrupt request was output. When timer 43 starts, interrupt controller 42 sets the mask bit stored in mask register 422 to “1” and masks the interrupt request. As in the above case, when the interrupt request signal is output from interrupt controller 42 at time instant T2, CPU 11 implements interrupt process Ra corresponding to interrupt cause information Na stored in status register 421 during the period from time instant T3 to time instant T4.
Subsequently, when packet-receiving unit 41 receives packet Pb at time instant T5, a DMA transfer of packet Pb is implemented during the period from time instant T5 to time instant T6. When the DMA transfer is completed at time instant T6, interrupt controller 42 waits until timer 43 finishes measuring length of time F as the interrupt mask bit stored in mask register 422 has been set to “1”. Then, when timer 43 finishes measuring length of time F at time instant T7, interrupt controller 42 sets the interrupt mask bit stored in mask register 422 to “0” and unmasks the interrupt request. Then, interrupt controller 42 outputs the interrupt request signal to CPU 11. In other words, interrupt controller 42 is one example of the interrupt request controller of the present invention that, when data is received by packet-receiving unit 41 while timer 43 is measuring the length of time, prohibits the output of the interrupt request until the measurement of the length of time is completed and permits the output of the interrupt request after the measurement of the length of time is completed.
In addition, because interrupt cause information Nb is stored in status register 421, interrupt controller 42 restarts timer 43 at time instant T7. This operates timer 43 again and starts the measurement of length of time F. When timer 43 starts, interrupt controller 42 sets the mask bit stored in mask register 422 to “1” and masks the interrupt request. When the interrupt request signal is output from interrupt controller 42 at time instant T7, CPU 11 implements interrupt process Rb corresponding to interrupt cause information Nb stored in status register 421 during the period from time instant T8 to time instant T9.
In the exemplary embodiment, interrupt controller 42 may change the set value stored in timer register 430 depending on the processing capacity of CPU 11, bus 10, or main memory 12. For example, if the processing capacity of CPU 11, bus 10, or main memory 12 is high, interrupt controller 42 lowers the initial value stored in timer register 430 to shorten the length of time to be measured by timer 43. On the other hand, if the processing capacity of CPU 11, bus 10, or main memory 12 is low, interrupt controller 42 increases the initial value stored in timer register 430 to increase the length of time to be measured by timer 43. In addition, interrupt controller 42 measures the utilization rate of the CPU at predetermined time intervals, and if the measured utilization rate is high, it increases the set value stored in timer register 430, whereas if the measured utilization rate is low, it may lower the set value stored in timer register 430.
In the exemplary embodiment, interrupt controller 42 measures the frequency of packet reception by packet-receiving unit 41, but the main unit that measures the frequency of packet reception is not limited to this. For example, a circuit that measures the frequency of packet reception may be separately installed in communication controller 14.
Moreover, in the exemplary embodiment, the number of packets received by packet-receiving unit 41 during a period starting from a unit time before the point at which the cause of an interrupt occurs is used as the frequency of packet reception by the packet-receiving unit 41, but the value used as the frequency of packet reception is not limited to this. For example, independently of the timing at which the cause of an interrupt occurs, the number of packets received per unit time by packet-receiving unit 41 may be counted at predetermined time intervals and used as the frequency of packet reception. In addition, if interrupt requests are output in response to high-priority packets from among the packets received by packet-receiving unit 41, the number of high-priority packets received by packet-receiving unit 41 may be used as the frequency of data reception.
Timer 43 may be a subtraction timer that measures the time corresponding to the set value through subtraction operations, or it may be an addition timer that measures the time corresponding to the set value through addition operations.
In the exemplary embodiment, interrupt controller 42 controls timer 43, but in addition to interrupt controller 42, CPU 11 may also control timer 43. In this case, CPU 11 may change the set value stored in timer register 430 in a manner similar to interrupt controller 42. Moreover, in the exemplary embodiment, interrupt controller 42 includes status register 421 and mask register 422, but in addition to interrupt controller 42, CPU 11 may also include these units. In this case, CPU 11 and communication controller 14 are coordinated to function as the interrupt controller of the present invention.
In the exemplary embodiment, processes of communication controller 14 may be implemented using a single or multiple hardware resources or may be implemented by the execution of one or multiple programs by CPU 11. In addition, such programs may be provided by being stored on computer-readable recording media, including magnetic recording media, such as a magnetic tape or a magnetic disk, optical recording media, such as an optical disk, magneto-optical recording media, or a semiconductor memory. It is also possible to allow such programs to be downloaded via communication lines such as the Internet.
The foregoing description of the embodiments of the present invention is provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations will be apparent to practitioners skilled in the art. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, thereby enabling others skilled in the art to understand the invention for various embodiments and with the various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the following claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2009-072078 | Mar 2009 | JP | national |
