BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
Other objects, features and advantages will occur to those skilled in the art from the following description of a preferred embodiment and the accompanying drawings, in which:
FIG. 1 is a schematic diagram of one prior art inverter-filter leg showing inverter drive voltage and filter output current;
FIG. 2 illustrates the inverter drive voltage waveforms with blanking time occurring in the prior art inverter-filter leg of FIG. 1 for filter output currents, positive, negative and at zero;
FIG. 3 illustrates the high ripple current into and distorted voltage out of the filter of FIG. 1 due to the blanking time;
FIG. 4 illustrates zero current clamping occurring in the prior art inverter-filter of FIG. 1;
FIG. 5 illustrates the ideal inverter output voltage and the actual inverter output voltage distorted due to blanking time and zero current clamping errors;
FIG. 6 is a representation of the inverter output or local current and the average current for different bus voltages illustrating the change in distortion or “flat topping” of the output voltage with applied voltage and output current;
FIG. 7 shows the calculated average current and load current waveform intersections that define “flat top” region where the discontinuous current mode occurs;
FIGS. 8A and B illustrate a portion of the output voltage waveform depicting the loss of voltage due to flat topping and an improved calculated average current waveform for defining application of a compensation voltage;
FIGS. 9A and B illustrate the output voltage waveform and the compensation voltage to be applied to it to compensate for the non-linear distortions;
FIGS. 10 and 11 depict the improvement in RMS voltage with current at 60 Hz and 50 Hz, respectively;
FIGS. 12 and 13 depict the improvement in THD at 60 Hz and 50 Hz, respectively;
FIG. 14 is a schematic block diagram of an inverter-filter with a non-linear compensation system of this invention; and
FIG. 15 is a directory of FIGS. 15A and 15B which are flow block diagrams of the non-linear compensation method of this invention applied to an inverter-filter.
DETAILED DESCRIPTION OF THE INVENTION
Aside from the preferred embodiment or embodiments disclosed below, this invention is capable of other embodiments and of being practiced or being carried out in various ways. Thus, it is to be understood that the invention is not limited in its application to the details of construction and the arrangements of components set forth in the following description or illustrated in the drawings. If only one embodiment is described herein, the claims hereof are not to be limited to that embodiment. Moreover, the claims hereof are not to be read restrictively unless there is clear and convincing evidence manifesting a certain exclusion, restriction, or disclaimer.
There is shown in FIG. 1, one inverter leg 10 of a conventional, prior art, three phase inverter-filter. Inverter-filter 10 includes a pair of switches 12, 14, such as insulated gate bi-polar transistors (IGBTs), each paralleled by a diode 16, 18 respectively. Switching signals Sh and Sl are applied to the bases of switches 12 and 14 to produce a pulse width modulated (PWM) output at inverter pole 20 to inductor 22 having inductance L, and thence through filter 24 to provide the inverter output at 26. A supply voltage Vdc is applied across switches 12 and 14 via lines 28 and 30 connected between which are filter capacitors 32 and 34 providing a mid-point voltage VF.
In any particular period, the pulse width modulated inductor voltage 39 has a positive portion 40, appearing at output 26, represented by the value (Vdc/2−VF) while the negative portion 42 has the value −(Vdc/2−VF). During this positive period current 43 (Il) has a positive slope as at 44 and during the negative portion of the period it has a negative slope 46. The peak to peak value of the current is referred to as Δi while the average current is expressed as Iav.
In practice positive 40 and negative portions 42 do not exactly follow directly after one another, for if they did there would be a condition, due to practical limitations, where when one was going off and the other coming on there could be a momentary short across the power supply Vdc. To prevent this, a delay called blanking time is purposely introduced between the turning off of one of switches 12 and 14 and the turning on of the other. This solution, however, creates another problem: “blanking” time error. To alleviate this problem the timing of the switching or reference signals Sh, Sl connected to the bases of switches 12 and 14 are shortened to avoid any possible overlap.
Thus, while the switching or reference signal having positive 40 and negative 42 portions is the ideal, the actual switching signal Sh is slightly shorter for the positive portion of the cycle leaving a gap or blank 50a, FIG. 2. Similarly, switching signal Sl is also shortened leaving a gap or blank 52a, so that there can clearly be no overlap of the on conditions of switches 12 and 14. However, this shortening of the switching signal Sh and Sl, FIG. 2, which creates the gaps 50a and 52a result in a shortening of pulse 40 so that it appears as at 40a. Thus the pulse widths of the output signals are foreshortened in the case where Il 43a is positive 44a with respect to the zero axis 45a. In contrast, if the current Il 43b is lower than zero axis 45b, gaps 50b and 52b create a pulse 40b which is larger than required. When the current Il 43c is around zero 45b, then the pulse width modulated pulse 40C is the right size but it is shifted slightly.
The current I, 60, FIG. 3 into filter 24, FIG. 1, has a high ripple factor through the inverter pole 20, FIG. 1. As a result, FIG. 3, the voltage 62 out of filter 24, FIG. 1, is distorted or “flat topped” as shown at 64, FIG. 3.
A second source of error in conventional devices, zero current clamping error occurs because of the natural characteristics of semiconductor devices. When the current Il 43′, 43″, FIG. 4, is close to zero 45′, 45″ a clamping occurs as at 70 and 70′ where the current clamps to zero instead of following the normal path 72′ 72″.
The combination of these non-linearities including blanking time and zero current clamping results in a voltage output at the load 80, FIG. 5, which is less than the ideal or required voltage 82, such as a nominal voltage of 120V. For example, in one instance the output voltage 80 at the load reaches only 106 volts: 14 volts short of the 120 volt peak of the ideal required voltage 82.
In accordance with this invention, in order to correct this voltage, it is first required to find the points 84, 86, for example in FIG. 5, where the two voltage curves diverge: the discontinuous current mode, and then generating a compensation voltage for the period of that mode. In accordance with this invention it is understood that at the limit of the discontinuous current mode (DCM), with uni-power factor, the circuit voltage equations for the filter inductor yield:
For any given inverter system characterized by a DC voltage, a filter inductor L, and a switching period, TS there is a value of the load current that may produce discontinuous current mode at any time. This is depicted in FIG. 6, where there are a number of Iav average curves 90 calculated for a number of different bus voltages shown in conjunction with a number of load currents Iload 92 for a number of different currents. There it can be seen that for a high enough voltage 90a, there is no intersections with any of the currents 92 and so there is no discontinuous current mode. However, for lower voltages, more in the range of general desirability, the discontinuous current mode is a factor. For example, at the next lower voltage 90b, it can be seen that there is an intersection with the highest current curve 92a so that intersecting points 84a and 86a define a discontinuous current mode. Similarly, with a lower voltage 90c there occur intersection points 84b and 86b with current 92a as well as intersection points 84c and 86c with voltage characteristic 92b and so on. This critical current in each case may be calculated with:
when this condition is met, the output voltage waveform becomes distorted. These threshold values result in a characteristic 100, FIG. 7, for Iav that can be used to determine whether and where occurs the discontinuous current mode 102 for any particular value of load current 104, Iload. The discontinuous current mode is the mode occurring between points 82 and 84 on the load current curve 104.
The complex and nonlinear characteristics of the phenomena at zero-current clamping make difficult the development of a compensation method especially designed for the inverter-filter case. The solution used for the inverter-motor drive case is based on applying a pulse (spike) of voltage during the time intervals when the zero-current occurs. Therefore, this is not a real waveform compensation method, but rather a method to avoid zero-current clamping. The problems arise from the difficulty in properly synchronizing the application of a pulse with the region of zero-current and totally nonlinear (violent even) character of the compensation. These two aspects may jeopardize the results within a system experiencing large temperature changes and technological parameter variation of the passive components. Furthermore, this problem cannot be corrected at the pulse level since a wider pulse will make the current pass through zero, but will produce different final and average values of the current. There the approach at the inverter uses the average level (low frequency) through a proper modification of the fundamental frequency reference.
For a better harmonic compensation the actual difference between the actual and desired voltage waveforms in FIG. 5 is used. The voltage development stops during the interval with the zero current clamping and it starts building up again as soon as the current circulation is re-established. The “flat top” is basically following a sinusoidal waveform with a smaller magnitude. The difference between the two waveforms will also be a portion of a sinusoid.
Practically, however, it turns out that attempting to add a portion of a sinusoid on top of the distorted load voltage 80, FIG. 5, in order to reach the ideal 82, encounters a serious problem of attempting to smoothly transition from one to the other. Therefore, a further achievement of this invention generates a start ramp and a finish ramp which are interposed between the distorted load voltage and the compensation waveform to obtain the compensation voltage. To accomplish this the value of Iav, characteristic value 100a, FIG. 8A, equation (5), is calculated during the first part 130 of the cycle with the voltage V at 120 volts. During the other part 132 of the cycle Iav is calculated using V=106 volts, the voltage of the distorted Iload. This gives two intersection points, 84 as before but not 86 as would be expected if the voltage continued to be 120, but 86-2, FIG. 8A. Then on load voltage 80, FIG. 8B, a start ramp 134 can be introduced at intersection point 84 after which sinusoid 136 is introduced. Then at point 86-2 the finish ramp 138 is introduced. Here, start ramp 134 has a positive slope and finish ramp 138 has a negative slope. However it will be understood that on the negative going portion of the cycle the start ramp 134 would have a negative slope and the finish ramp would have positive slope.
Compensation waveform, sinusoid 136, is calculated off-line and generated by the DSP as the actual difference between the distorted and desired voltage sinusoidal waveforms while ramps 134 and 138 are generated by the DSP with a fixed slope following the intersection points determined as described above. Having generated the compensation voltage 140 composed of ramps 134 and 138 and compensation waveform 136, FIG. 9A, this can now be added to distorted load voltage 80, FIG. 8B, to overcome the distortion of flat-top 64.
The improvement resulting from this invention is shown in FIGS. 10-12. In FIGS. 10 and 11 it can be seen that the voltage without compensation 150 drops from the nominal voltage of 120 to well below 105 volts, whereas with compensation 152 the voltage barely goes below 120 at 60 cycles. At 50 cycles, FIG. 11, the result is similar where the voltage without compensation 150a is again below 105 volts, whereas with compensation it remains nearly at the nominal 120 volt level 152a. Total harmonic distortion (THD) is also well compensated for as shown in FIGS. 12 and 13. In FIG. 12 at 60 Hz it can be seen that the voltage total harmonic distortion variation without compensation 154 is as high as 4%, whereas with compensation 156 it is no more than 3½%. This is an important margin when faced with requirements, as is often the case, that the total harmonic distortion be kept below 5%: 4% is a bit close to that margin; 3½% is a lot better. At 50 Hz, FIG. 13, the results are also good, as it can be seen that the total harmonic distortion 154a, FIG. 13, for 50 Hz is as high as 4% where with compensation 156a it never rises above 3%.
In one embodiment a three phase inverter 10′ is driven by an inverter-filter non-linearity blanking time and zero current clamping compensation system 200, FIG. 14, including a comparator circuit 202 and a compensation circuit 204 all of which may be contained on a single DSP chip 206 which also may contain current average measurement circuit 208 and sinusoid reference drive 210. Comparator circuit 202 in this embodiment includes a memory look-up table or off line calculation 212 and a comparator 214. Compensation circuit 204 includes a compensation waveform generator 216, start ramp 218, finish ramp 220, a compensation voltage generator 222 and adder 224. Inverter 10′ includes gate drivers 226, for driving switches 12a, 14a, 12b, 14b, and 12c and 14c in a full three phase inverter arrangement. A pulse width generator 228 provides the switching signals to gate driver 226.
In operation comparator 214 compares the average current from average current measurement circuit 208 with the values in memory look-up table 212. If the average current exceeds that of the discontinuous current mode threshold values, then start ramp 218 is activated. The compensation voltage seen as the output of the compensation circuit 222 follows this ramp until the ramp equals the sinusoidal waveform generated by 216. When the average current measurement by circuit 208 becomes less than that from memory look-up table 212, finish ramp circuit 220 supplies the finish ramp to compensation circuit 222. In this way the entire compensation voltage is constructed and delivered to adder 224 which combines that with the original sinusoidal reference drive voltage 210. This output is then used by pulse width modulation generator 228 to generate the signals to gate drivers 226 for driving switches 12a-12c and 14a-14c so that the output of the inverter will be closer to the ideal since they have been compensated for distortions.
This invention also contemplates a method of inverter-filter non-linearity blanking time and zero current clamping compensation. The method according to this invention is shown in FIGS. 15, 15A and 15B where the average output current of the inverter is measured, 250, and the discontinuous current mode threshold values are generated or looked up 252. The measured average output current and the discontinuous current mode threshold values are compared in absolute values 254. If a discontinuous current mode has not occurred 256 (that is the measured average output current is less than discontinuous current mode threshold in absolute values), the system goes back to step 250 and the PWM generator 276 works with the original reference voltage 274 without any additional compensation. If discontinuous current mode condition has occurred (that is the measured averaged output current is larger than discontinuous current mode threshold in absolute values), then the query is made as to whether the measured averaged output current is positive 258. If it is, then start ramp up occurs 260, ramp up is ended 262, and the compensation sinusoidal waveform is generated 264. The compensation waveform generation is stopped 266. The finish ramp is then started 268 and when the finish ramp is ended 270, it is combined 272 with the original drive voltage 274 to provide the compensated voltage to the pulse width modulation generator 276. If at 258 the average output current is not positive, then the start ramp down is started 278, after which the start ramp down is ended 280 and the compensation waveform is started 282. When it is completed 284, then the finish ramp up 286 begins after which the finish ramp up is ended at 288. The waveforms are ORed together 290, and depending upon the condition of switch 291 in response to input from 256 compensation is applied or not. The completed waveform is then added 272, to the original drive voltage 274 as before to come up the compensation voltage for pulse width modulation generator 276.
Although specific features of the invention are shown in some drawings and not in others, this is for convenience only as each feature may be combined with any or all of the other features in accordance with the invention. The words “including”, “comprising”, “having”, and “with” as used herein are to be interpreted broadly and comprehensively and are not limited to any physical interconnection. Moreover, any embodiments disclosed in the subject application are not to be taken as the only possible embodiments.
In addition, any amendment presented during the prosecution of the patent application for this patent is not a disclaimer of any claim element presented in the application as filed: those skilled in the art cannot reasonably be expected to draft a claim that would literally encompass all possible equivalents, many equivalents will be unforeseeable at the time of the amendment and are beyond a fair interpretation of what is to be surrendered (if anything), the rationale underlying the amendment may bear no more than a tangential relation to many equivalents, and/or there are many other reasons the applicant can not be expected to describe certain insubstantial substitutes for any claim element amended.
Other embodiments will occur to those skilled in the art and are within the following claims.
Patent Application
20080094863
