Patent Application
20170229872
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the United States Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
One or more implementations relate generally to a pre-charge circuit and control based on solid-state switching.
Capacitors are often used across the DC terminals of inverters to maintain the DC voltage ripple below a specific magnitude. These capacitors provide current to the H-bridges throughout the switching operation, so they are marginally discharged during switch conduction then recharged by a DC power source.
When DC power is first connected to a power converter, the capacitors may be pre-charged to match the voltage at their input terminals. Uncharged capacitors instantaneously behave like short-circuits, so large inrush currents can be pulled from the DC power supply. This is particularly problematic for DC battery systems because they do not have limits on the magnitude of short-circuit current they can provide. When unconstrained, these large inrush currents can cause DC protection circuitry to trip and can lead to component or conductor failures in some cases.
The included drawings are for illustrative purposes and serve to provide examples of possible structures and operations for the disclosed inventive systems, apparatus, methods and computer-readable storage media. These drawings in no way limit any changes in form and detail that may be made by one skilled in the art without departing from the spirit and scope of the disclosed implementations.
Some downsides to circuit 25 relate to the limitations of switching mechanisms S1 and S2. Contactors S1 and S2 rely on mechanical operations that are inherently slow and prone to latency. This makes it difficult to control the switching operation with a high degree of accuracy.
Given the magnitude of the current flowing through contactors S1 and S2, the power dissipation due to contact resistance can be substantial. This can lead to excessive heating which can impact the operation (e.g., accuracy of current sensing devices) and reliability (e.g., due to accelerated component aging) of surrounding components. The contact resistance can also increase throughout the operational lifetime of the part, which can lead to further heating and accelerated degradation.
High current contactors are also usually bulky power components that are not well-suited to a printed circuit board (PCB) application. This necessitates an external mounting and cabling solution that can be cumbersome and costly.
PV array 52 may be any type of device capable of converting solar energy into electrical energy. In one example, PV inverter 56 may convert direct current (DC) power from PC array 52 into alternating current (AC) power for different local AC loads 66 and/or other remote AC devices connected to power grid 64. PCS 60 may charge battery system 54 using power supplied by PV array 52 or power grid 64 and also may convert stored DC energy in battery system 54 into AC power for powering local loads 66 and exporting power to the power grid 64.
DER system 50 may use an energy management system (EMS) 58 to coordinate power flow between PV array 52, battery system 54, local loads 66, and power grid 64. EMS 58 may communicate with other energy sources throughout the power system, manage power flow within DER 50, and respond to varying grid conditions or dispatch commands.
Battery system 54 typically relies on three main components that interact with each other. These include a battery management system (BMS) 57, PCS 60, and EMS 58. BMS 57 monitors the state and condition of battery 55 and provides protection against unsafe operating states (e.g., high battery cell temperatures). BMS 57 also provides handshaking and information transfer with other power components. Battery 55 can be a single battery or multiple batteries combined within battery system 54.
PCS 60 is a linking element that enables power transfer between battery 55 and loads 66 connected to electrical panel 62. PCS 60 is designed to convert DC power from battery 55 into AC power which may be used to power local loads 66 or to export to the power grid 64. PCS 60 may be bidirectional to convert AC power from power grid 64 and/or PV array 52 into DC power for charging battery 55.
EMS 58 coordinates power flow between power grid 64, battery 55, local loads 66, and PV array 52. EMS 58 may implement algorithms to manage battery charging and discharging based upon electricity price structures such as time-of-use metering or demand charging.
PCS 60 may act as a bridge between BMS 57 and EMS 58. PCS 60 converts power demand signals from EMS 58 into real power flow between the power converter and battery 55. As a result, PCS 60 is uniquely equipped to collect detailed information about battery system 54 in real-time. PCS 60 also has access to physical and operational parameters that would not otherwise be conveyed to EMS 58. For example, PCS 60 may convey battery temperature, instantaneous power, and state of charge of battery system 54 to EMS 58.
PCS 60 includes a digital signal processor (DSP) 74 that manages the switching controls within an inverter power circuit 74 such as the step wave power converter described in U.S. Pat. Nos. 6,608,404 and 7,808,125 which are herein incorporated by reference in their entireties. These controls are based on a feedback process involving a parameter set point, which can be set manually by a user or set through EMS 58.
Other example inverter and bridge circuits used in PV inverter 56 and PCS 60 are described in U.S. patent applications such as U.S. Pat. No. 6,198,178; U.S. Pat. No. 8,031,495; U.S. U.S. Pat. No. 6,628,011; U.S. Pat. No. 6,765,315; U.S. Pat. No. 6,738,692; and U.S. Pat. No. 7,087,332 which are all also herein incorporated by reference in their entireties.
Battery 55 in battery system 54 may store energy output from PV array 52. DSP 74 operating within PCS 60 may measure current and/or voltage data from both battery system 54 and PV system 51 and perform functions in PCS 60, such as power measurements, control, and inverter system switching.
A solid-state based pre-charge circuit 100 includes a DC input 102 that connects to battery 55 in battery system 54 and includes a DC output 112 that connects to H-bridges within inverter 74. In one example, pre-charge circuit 100 is located within PCS 60, but may be located and connected externally to PCS 60, PV inverter 56, or any other inverter circuit. It should be understood that the use of pre-charge circuit 100 in DER system 50 in
Pre-charge circuit 100 uses solid-state switching devices 104 to address prior pre-charge circuit shortcomings and provide improved controllability. Pre-charge circuit 100 replaces a mechanical contactor with a controllable solid-state switch 104, such as field effect transistors (FET) or insulated-gate bipolar transistors (IGBT). Any number of solid-state devices 104 can be used, and in one example, between 1 and 10 FETs 104 are used. In any case, the solid-state switches are actuated by a driver 120 which are coordinated by a DSP 74. In another embodiment, relay 106 (S2) within the resistive path can also be replaced with solid-state switches such as FETs or IGBTs. For example, a same number, or a different number, of stacked solid-state switches similar to switches 104 may be connected in parallel between DC input 102 and resistor 108. It is understood that relay 106 is also actuated by a driver which is coordinated by a DSP 74, but this is not shown in
On the shunting path 114, rather than relying on large and expensive solid-state devices to meet power specifications (e.g., greater than 100 A), multiple solid-state devices 104 are ganged together in parallel and switched by a single driver 120. This provides the added benefit of distributing the dissipated power (conduction losses) through a larger surface area, thereby reducing the thermal load. Since solid-state switching devices 104 are PCB-mountable, a thermal management solution can be built into the PCB by tuning the copper trace thickness and footprint. An external PCB-mounted heatsink can also be used to further dissipate heat.
In one example, driver 120 is controlled by DSP 74, which also may control H-bridge circuitry in inverter 74. That is, single DSP 74 may control all of the sub-circuits in inverter 74 and PCS 60, including pre-charge circuit 100. In another example, a separate DSP may control pre-charge circuit 100.
After being prompted to leave the idle state, DSP 130 at time T1 closes pre-charge relay 106, which connects current limiting resistor 108 to battery system 54. Input capacitors 110 are then charged through resistive branch 116 for a configurable charge duration, such as a 1 second default time period. The DC voltage 150 on DC bus 70 exponentially approaches some nominal value and DC current 152 spikes while charging capacitors 110 and then exponentially decays down. The charge duration depends on the characteristics of the input capacitance and pre-charge resistor; in tandem these circuit elements form an RC circuit which is well known in the art. After the charge duration has elapsed, the input capacitor bank 110 should be substantially charged to the DC voltage of the DC input terminal 102.
After the charge duration elapses, solid-state switches 104 are switched on with driver 120 at time T2, which connects parallel shunting branch 114 between battery system 54 and DC bus 70. Before this occurs, it is important that the voltage at the output DC bus 70 is approximately equal to the voltage at the input terminals 102. If the output voltage is significantly lower, large and potentially damaging currents can flow through the output DC bus 70 until the input capacitor bank 110 is fully charged. The DSP 74 measures the DC voltages at the input 102 and output 112 of the pre-charge circuit and ensures this condition is met prior to switching in the shunting branch 114.
Once the shunting branch 114 is connected, the resistive branch 116 and shunting branch 114 provide parallel conduction paths simultaneously. This configuration remains in place for a configurable duration, such as a 1 second default time.
DSP 74 then opens pre-charge relay 106 at time T3, which disconnects resistive branch 116 from pre-charge circuit 100 and leaves only shunting branch 114 connected. Thereafter, solid-state switches 104 remain in conduction mode throughout the normal operation 160 of inverter 140 when converting DC power from battery 55 into AC power on AC bus 80. Solid-state switches 104 provide a continuous electrical link between battery system 54 and DC bus 70.
During normal operation 160, solid-state switches 104 are opened at any time, transitioning battery system 54 back to an idle state. This disconnect mode completely disconnects DC terminals 102 from inverter 74, preventing all power flow, and preserving stored energy in battery system 54. Again, it should be understood that pre-charge circuit 100 may be used with any switching circuit that may need to input pre-charging. For example, DC power supplied to inverter 74 may not necessarily come from a battery 55, but may come from PV array 52 or from any other power source.
Switching of solid-state switches 104 is coordinated precisely by DSP 74 in PCS 60 via control drivers 120. By using faster solid-state switches 104, DSP 74 can reduce the duration of the pre-charge routine by minimizing the activation overlap of resistive branch 116 with shunting branch 114 (the time between T2 and T3).
Solid-state switching pre-charge circuit 100 improves control and reliability compared to mechanical contact approaches. Solid-state switches 104 have lower power losses, can employ simple thermal management strategies, and have better reliability and safety. Solid-state switches 104 may have a longer useful lifetime compared with mechanical contactors (typically limited to less than 1 million switching cycles) and offer more predictable resistive characteristics as they age.
Implementing solid-state switches on the resistive branch 116 further improves the controllability of the pre-charge circuit 100 through the ability to control and coordinate all pre-charge switches using a single DSP 74. However, the current magnitudes through the resistive branch 116 are low and the conduction durations are limited, so reliability concerns, power losses, and thermal loads are less significant. In this case, it is acceptable to use a single inexpensive mechanical contactor.
By default, solid-state switches 104 remain open until powered by driver 120. Therefore, in one example, communication and control by DSP 74 is established before pre-charge circuit 100 can be activated. By contrast, contactor systems are closed by a simple mechanical activation and may be more susceptible to false activation. In more extreme cases, contactors can fuse shut, which may completely short the pre-charge circuit 100 and may lead to large current magnitudes during start-up.
As mentioned above, solid-state switches 104 are also well-suited to board mounted applications, which are compatible with design approaches used throughout inverter systems 74. Pre-charge circuit 100 may reduce the volume within an enclosure, constrain power flow to PCB traces, and reduce overall power system costs. Pre-charge circuit 100 may be used in any power conversion system.
While only a single computing device 1000 is shown, the computing device 1000 may include any collection of devices or circuitry that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the operations discussed above. Computing device 1000 may be part of an integrated control system or system manager, or may be provided as a portable electronic device configured to interface with a networked system either locally or remotely via wireless transmission.
Processors 1004 may comprise a central processing unit (CPU), a graphics processing unit (GPU), programmable logic devices, dedicated processor systems, micro controllers, or microprocessors that may perform some or all of the operations described above. Processors 1004 may also include, but may not be limited to, an analog processor, a digital processor, a microprocessor, multi-core processor, processor array, network processor, etc.
Some of the operations described above may be implemented in software and other operations may be implemented in hardware. One or more of the operations, processes, or methods described herein may be performed by an apparatus, device, or system similar to those as described herein and with reference to the illustrated figures.
Processors 1004 may execute instructions or “code” 1006 stored in any one of memories 1008, 1010, or 1020. The memories may store data as well. Instructions 1006 and data can also be transmitted or received over a network 1014 via a network interface device 1012 utilizing any one of a number of well-known transfer protocols.
Memories 1008, 1010, and 1020 may be integrated together with processing device 1000, for example RAM or FLASH memory disposed within an integrated circuit microprocessor or the like. In other examples, the memory may comprise an independent device, such as an external disk drive, storage array, or any other storage devices used in database systems. The memory and processing devices may be operatively coupled together, or in communication with each other, for example by an I/O port, network connection, etc. such that the processing device may read a file stored on the memory.
Some memory may be “read only” by design (ROM) by virtue of permission settings, or not. Other examples of memory may include, but may be not limited to, WORM, EPROM, EEPROM, FLASH, etc. which may be implemented in solid-state semiconductor devices. Other memories may comprise moving parts, such a conventional rotating disk drive. All such memories may be “machine-readable” in that they may be readable by a processing device.
“Computer-readable storage medium” (or alternatively, “machine-readable storage medium”) may include all of the foregoing types of memory, as well as new technologies that may arise in the future, as long as they may be capable of storing digital information in the nature of a computer program or other data, at least temporarily, in such a manner that the stored information may be “read” by an appropriate processing device. The term “computer-readable” may not be limited to the historical usage of “computer” to imply a complete mainframe, mini-computer, desktop, wireless device, or even a laptop computer. Rather, “computer-readable” may comprise storage medium that may be readable by a processor, processing device, or any computing system. Such media may be any available media that may be locally and/or remotely accessible by a computer or processor, and may include volatile and non-volatile media, and removable and non-removable media.
Computing device 1000 can further include a video display 1016, such as a liquid crystal display (LCD) or a cathode ray tube (CRT) and a user interface 1018, such as a keyboard, mouse, touch screen, etc. All of the components of computing device 1000 may be connected together via a bus 1002 and/or network.
For the sake of convenience, operations may be described as various interconnected or coupled functional blocks or diagrams. However, there may be cases where these functional blocks or diagrams may be equivalently aggregated into a single logic device, program or operation with unclear boundaries. Having described and illustrated the principles of a preferred embodiment, it should be apparent that the embodiments may be modified in arrangement and detail without departing from such principles.
The present application claims priority to U.S. Provisional Patent Application Ser. No. 62/293,715 filed on Feb. 10, 2016, entitled: POWER CONTROL SYSTEMS which is incorporated by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 62293715 | Feb 2016 | US |
