Patent Application
20130108063
This relates generally to electronic devices, and, more particularly, to testing electronic devices.
Electronic devices such as media players, portable computers, and cellular telephones are generally tested during manufacturing. Testing is often performed using procedures that are compliant with the IEEE 1149.1 standard. This type of testing, which is sometimes referred to as Joint Test Action Group (JTAG) testing, can be used to capture and analyze scan chain data and perform other debug procedures.
Challenges can arise with conventional JTAG testing procedures. In some situations, it is necessary to probe a printed circuit board within a device to perform tests or to make manufacturing changes to a printed circuit board once testing is complete. Other test procedures rely on device software that is susceptible to freezing.
It would therefore be desirable to be able to provide improved techniques for testing electronic devices.
Electronic devices may be provided with audio circuits and circuitry such as controller circuitry that is configured to support communications and test mode operations. An electronic device may have a port with which external equipment may be coupled to the electronic device.
During normal operation, a connector such as an audio connector may be inserted into a connector port in an electronic device. The audio connector may be associated with a headset or other accessory and may be used to carry audio signals. For example, the audio connector may have a microphone terminal for carrying microphone signals and left and right audio terminals for carrying stereo audio.
During test mode operations, a connector associated with a tester may be inserted into the connector port. For example, an audio plug associated with the tester may be inserted into an audio jack in an electronic device. Using a monitor circuit, the electronic device can monitor contacts in the audio jack for commands from the tester.
To place the electronic device in test mode, the tester may supply the electronic device with input through the audio jack in the electronic device. The tester may, for example, apply a predetermined voltage to a microphone contact or other contact in the audio jack, may apply a pattern of voltages to contacts in the audio jack, may produce resistance values across one or more pairs of terminals within the audio jack, may generate time-varying signals that are applied to one or more contacts within the audio jack, or may produce other signals that direct the electronic device to enter test mode.
The electronic device may have a monitor circuit that monitors signals on the audio jack or other connector. In response to detecting predetermined signals on the audio jack or other connector with the monitor circuit, the electronic device may enter test mode and may use the controller circuitry to support test mode operations. During testing, the tester that issued signals to the electronic device to place the device in test mode may be used in transmitting and receiving test data with the controller circuitry in the electronic device. Arrangements of this type may facilitate testing (e.g., JTAG testing) of enclosed electronic devices. Enclosed electronic devices may include, as examples, devices that do not include dedicated JTAG external connectors and devices in which accessing internal circuit boards for JTAG testing may require disassembly of the devices.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.
Electronic devices may be provided with circuitry that supports testing. An illustrative system environment for a device that has circuitry that supports testing is shown in
Device 12 may include a connector such as connector 14. Connector 14 may have two contacts, three contacts, four contacts, five contacts, six contacts, six or more contacts, six or fewer contacts, seven contacts, seven or more contacts, seven or fewer contacts, thirty contacts, or any other suitable number of contacts.
Connector 14 may be coupled to different types of external equipment. As shown in
Power adapter 18 may convert alternating current power from alternating current (AC) source 20 into direct current (DC) signals at connector 22. When it is desired to charge a battery in device 12 or to otherwise provide power to device 12, power adapter connector 22 may be connected to mating electronic device connector 14, as illustrated by path 36.
Accessory 26 may include a connector such as connector 24 that mates with connector 14. Accessory 26 may be a mono or stereo headset with a microphone, a mono or stereo headset without a microphone, a charging station, an external set of speakers, a computer (e.g., a laptop or desktop computer that is being used to provide power to device 12 and/or that is being used to synchronize data with device 12), or other suitable accessories or external equipment. When it is desired to use accessory 26 with device 12, accessory connector 24 may be plugged into connector 14 of electronic device 12, as indicated by path 34.
Testing may be performed using tester 30. Tester 30 may be a Joint Test Action Group (JTAG) tester or test equipment that supports other testing protocols. JTAG testers sometimes use four or five pin interfaces (e.g., interfaces that include pins such as a JTAG test data input pin TDI, a JTAG test data output pin TDO, a JTAG clock pin TCK, a JTAG state machine control pin TMS, and, if desired, a reset pin). In some test environments, it may be desirable to minimize pin counts, so protocols such as the Serial Wire Debug (SWB) protocol have been developed that support testing over two pins (e.g., using a SWDIO data pin and a clock pin SWCLK). Serial Wire Debug interfaces can be used to support JTAG testing. Illustrative configurations in which tester 30 is a tester of the type that may support JTAG and/or Serial Wire Debug testing are sometimes described herein as an example. In general, however, tester 30 may support any suitable test protocols. As shown by path 32, test connector 28 of tester 30 may be mated with connector 14 of electronic device 12 when it is desired to test device 12.
Illustrative circuitry that may be provided in electronic device 12 is shown in
Device 12 may use a monitor circuit such as monitor circuit 54 to monitor the status of connector 14. For example, monitor circuit 54 may monitor the contacts of connector 14 for the presence of a signal or connector characteristic that indicates that device 12 should enter a testing mode (e.g., a JTAG mode).
Switching circuitry 52 may be used to selectively couple the lines in communications path 58 to lines such as lines in paths 60 and 62. For example, during normal operation of device 12 by a user, switching circuitry 52 may be configured to route signals from connector 14 to audio circuit 46 using two or more lines in path 60. During test mode operations, switching circuitry 52 may be configured to route signals from connector 14 to test module 44 of control circuitry 38 via two or more lines in path 62.
Audio circuit 46 may be, for example, an audio integrated circuit that handles analog and/or digital audio signals. Functions such as media playback, microphone signal amplification, noise cancellation, digital-to-analog and analog-to-digital conversion, equalization, volume control, pin assignment swapping (e.g., to accommodate headsets in which the microphone and ground terminals are reversed), and other control and audio processing features may be handled by audio circuit 46. In some contexts, audio circuit 46 may be referred to as a codec. Non-audio functions may, if desired, be integrated into audio circuit 46 or provided using other circuits in device 12.
Control circuit 38 may be implemented using one or more integrated circuits. Control circuit 38 may, for example, be implemented using an integrated circuit of the type that is sometimes referred to as a system-on-a-chip (SOC) integrated circuit. System-on-a-chip integrated circuits generally include a processor and other circuits. Control circuit 38 may include memory or may be coupled to external storage (e.g., memory in components 56).
Control circuit 38 may include processing circuits such as one or more testing and communications modules. As an example, control circuit 38 may include a communications module such as Universal Serial Bus (USB) module 40, a communications module such as Universal Asynchronous Receiver Transmitter (UART) module 42, and other communications circuits. Control circuit 38 may include circuitry that is configured to support test mode operations such as testing circuitry 44. Testing circuitry 44 may support test protocols such as four or five wire JTAG protocols and/or protocols in which JTAG data is conveyed use a two-wire test interface such as a Serial Wire Debug interface.
Power management unit 48 may be used to handle operations associated with receiving external power through connector 14. For example, when power adapter 18 (
Accessories 26 (
Device 12 may contain other components 56. Components 56 may include one or more displays, status indicator lights, buttons, sensors, microphones, speakers, a battery, amplifiers, radio-frequency transceiver circuits, microprocessors, microcontrollers, volatile memory (e.g., dynamic random-access memory, static random-access memory, etc.), non-volatile memory (e.g., flash memory or other solid state storage), hard drives, application-specific integrated circuits, and other electrical components. These components may be interconnected with the other components shown in
To ensure that device 12 enters a JTAG test mode or other desired testing mode, device 12 may be provided with external input. The external input may take the form of insertion of a predefined connector into connector 14, signals that are supplied to connector 14 by tester 30, and/or other suitable input for directing device 12 to enter a test mode of operation.
A state diagram showing operations involved in using device 12 in a system environment such as system 10 of
As indicated by line 72, when a piece of external equipment 16 is plugged into device 10, device 12 may perform operations to determine whether to enter test mode (state 66). These operations may include, for example, using monitor circuit 54 to measure signals on the contacts of connector 14. Signal measurements may be made, for example, to compare the signals on the contacts to reference signals (e.g., to compare signal voltages to reference voltages), to compare the magnitudes of the signals to each other (e.g., to compare signal voltages on one or more contacts to signal voltages on one or more other contacts), to compute resistances, to evaluate the states of sensors that monitor whether a connector is plugged into connector 14, etc.
In response to a determination by device 12 that device 12 is not being instructed to enter test mode (i.e., because the external equipment that was connected to device 12 was a power adapter or other accessory and not a tester), device 12 may transition to state 70, as indicated by line 78. During the operations of state 70, device 12 and the external equipment that is connected to device 12 (e.g., power adapter 18 or other accessories such as accessory 26) may be operated normally. Once the external equipment is removed, device 12 may transition back to state 64, as indicated by line 80.
In response to a determination by device 12 that device 12 is being instructed to enter test mode (i.e., because the external equipment that was coupled to device 12 was a tester such as tester 30), device 12 may transition to state 68 (test mode), as indicated by line 74. During state 68, test circuitry 44 or other circuitry in control circuitry 38 that is configured to support test mode operations may be activated and used for handling test operations. For example, JTAG circuitry may be used to perform boundary scan test operations, may be used in conveying test data to tester 30, and may be used in performing other test operations for testing whether device 12 is operating satisfactorily. If errors are identified, a test operator may be alerted (e.g., by displaying an alert message on tester 30). Debugging operations may be performed in which test data captured by circuitry 44 is transmitted to tester 30 for analysis. Tester 30 may also direct the components of device 12 to perform various actions (e.g., adjusting integrated circuit settings, etc.) and may evaluate the ability of device 12 to execute these actions.
Once testing has been completed, tester 30 may be disconnected from connector 14 and, as indicated by line 76, device 12 may be operated while being decoupled from external equipment (state 64).
Switching circuitry 52 may contain electronic switches that are controlled by control signals from control circuitry in device 12 (e.g., control circuit 38 and/or other storage and processing circuitry in device 12). Switches within switching circuitry 52 may be based on transmission gates (e.g., gates based on metal-oxide-semiconductor transistors) or other electrically controllable switch technologies.
There may be any suitable number of switches in switching circuitry 52 (e.g., one or more, two or more, five or more, ten or more, etc.). The number of switches that are used in switching circuitry 52 may be selected to provide a desired amount routing flexibility for signals within device 12. For example, if it is desired to be able to route a set of audio signals from connector 14 to audio circuit 46 in either normal or reversed configuration (e.g., to accommodate normal and reversed microphone/ground line pin assignments in connector 14), switching circuitry 52 may be provided with sufficient switching resources to route the microphone and ground contacts in connector 14 to a pair of respective pins in audio circuit 46 in a normal configuration or in a configuration in which the signals are reversed).
As another example, if it is desired to route signals from a contact in connector 14 to several possible destinations such as a pin in audio circuit 46, a pin associated with USB module 40, a pin associated with UART module 42, and a pin associated with test circuitry 44, switching circuitry 52 may be provided with switches for forming a multiplexing circuit that is capable of selecting which of these various paths should be formed in device 12. Configurations for switching circuitry 52 that include relatively more switches may be used to provide enhanced amounts of interconnection flexibility, whereas configurations for switching circuitry 52 that include relatively fewer switches may be used to conserve device resources.
Switching circuitry 52 and audio circuitry 46 or other circuitry in device 12 may, if desired, receive a signal from connector 14 via path 82. This signal may be used in connection with the signal on path 60A to determine whether a mating connector has been inserted into connector 14 in the position associated with contact P1. Consider, as an example, a configuration in which contact 14 is a four pin female audio connector (sometimes referred to as an audio jack or four-contact audio connector). This type of connector, which is also sometimes referred to as a TRRS (tip-ring-ring-sleeve) connector, may use contact P1 to mate with a corresponding tip contact in a four-pin male audio connector (sometimes referred to as an audio plug), may use contact P2 to mate with a first corresponding ring contact in a four-pin male audio connector, may use contact P3 to mate with a second corresponding ring contact in a four-pin male audio connector, and may use contact P4 to mate with a sleeve contact in a four-pin male audio connector.
With one suitable configuration, which is sometimes described herein as an example, contact P1 of connector 14 may be associated with a left channel of audio L. Contact P2 of connector 14 may be associated with a right channel of audio R during normal operation. During testing (e.g., JTAG testing), contact P2 may be associated with a signal SWDIO (e.g., a first of two Serial Wire Debug signals). During normal operation, contact P3 may be associated with ground and contact P4 may be associated with a microphone signal from a microphone in an attached accessory (e.g., a headset with a microphone or other accessory 26). In some geographic regions, convention may dictate that the normal pin assignments for contacts P3 and P4 be reversed (i.e., so that contact P3 is used for microphone signals and so that contact P4 serves as a ground terminal). During testing, contact P4 may be associated with a signal SWCLK (e.g., a second of two Serial Wire Debug signals). The signals SWDIO and SWCLK may, if desired, form a testing interface that is used for handling JTAG test data.
To detect whether the tip of an audio plug has been received properly within the tip portion of the audio jack (connector 14), connector 14 may be provided with a sensor that detects the presence (absence) of the audio plug tip portion in the vicinity of contact P1. A mechanical sensor, optical sensor, electrical sensor, or any other suitable type of sensor may be used to detect the presence of all or part of an audio plug within connector 14.
As one example, a sensor (sometimes referred to as a headphone detect sensor) may be implemented by measuring the resistance between a pair of contacts associated with pin P1. The first contact may be, for example, pin P1 itself and the second contact (illustrated as contact HPD in
When the measured resistance between sensor contacts HPD and P1 is relatively high (e.g., over a predefined threshold level), it can be assumed that the tip contact portion of the male audio connector is not present. When the measured resistance between HPD and P21 is low (e.g., below the predefined threshold level), device 12 can conclude that the tip contact from the audio plug has been inserted into connector 14 (e.g., the audio plug is present). Different actions can be taken depending on whether or not the audio tip is present (e.g., actions related to configuring switching circuitry 52 and/or using audio circuitry 46 and/or circuitry such as control circuitry 38).
In the example of
Connector 14 may be an audio jack (female audio connector) that mates with corresponding audio plugs (male audio connectors) such as audio plug 84 that has corresponding tip (T), ring (R), ring (R), and sleeve (S) contacts. Audio plug 84 may be associated with any suitable type of external equipment 16. For example, audio plug 84 may serve as connector 22 of power adapter 18, connector 24 of accessory 26, or connector 28 of tester 30 (
Optional contact 86 may serve as contact HPD of
As shown in
Controller 98 may be coupled to control circuitry such as input-output circuitry 94 via paths such as path 96. Input-output circuitry 94 may include input-output buffers (e.g., output drivers capable of generating voltages at adjustable and/or fixed voltages of desired magnitudes), adjustable resistors, adjustable current sources, or other input-output circuitry. Conductive paths 92 (e.g., traces on a printed circuit board or other substrates) may be used to couple output signals from output buffers, adjustable resistors, and other input-output circuitry 94 to respective lines in path 90. Each of lines 92 may be coupled between a respective input-output pin associated with circuitry 94 and a conductive path such as a conductive wire in path 90. Path 90 may be implemented using a cable containing wires that are connected to respective contacts 88 in a pigtailed connector (connector 28), as shown in
During testing, control circuitry in tester 30 such as controller 98 and input-output circuitry 94 may provide commands to a device under test that direct the device under test to enter test mode. For example, tester 30 may use controller 98 and input-output circuitry 94 to produce a particular pattern of voltages (or resistances) at contacts 88. These signals may be detected by monitoring circuitry in the device under test.
Monitor circuit 54 may measure voltages, currents, resistances, time-varying signals, or other suitable input associated with connector 14. For example, monitor circuit 54 may detect when tester 30 (
As an example, when tester 30 desires to place device 12 in test mode, tester 30 can place a predetermined voltage on one of contacts 102 such as a microphone (M) contact. In response to detection of the predetermined voltage on the microphone contact with monitor circuitry 54, device 12 can be placed in test mode (e.g., using JTAG or other test circuitry 44 to perform tests and communicate with tester 30).
As shown in the third row of the table of
When tester 30 desires to force device 12 into test mode, controller 98 in tester 30 may use an adjustable or fixed output buffer in input-output circuitry 94 to place a 4 volt signal (e.g., a signal in a voltage range of about 3.6 to 4.4 volts or other suitable voltage range) on the microphone terminal of connectors 28 and 14. Monitor circuit 54 may measure the voltage on the microphone line (e.g., using a voltage detector or other suitable circuitry). When a voltage with the predetermined magnitude of about 4 volts is detected, device 12 (e.g., control circuitry in device 12) can activate JTAG or other test circuitry 44 for use in supporting test mode operations (i.e., device 12 may be forced into test mode). Switching circuitry 52 may also be configured to ensure that path 62 is coupled to path 58 (e.g., so that JTAG circuitry 44 is coupled to appropriate contacts in connector 14). Other predetermined voltages may be supplied to the microphone terminal if desired. For example, tester 30 may supply a voltage of 3 volts to force device 12 into a UART mode using UART circuitry 42 of
If desired, JTAG circuitry 44 may be enabled and disabled using a control signal such as a JTAG enable signal (JTAG_EN). For example, JTAG circuitry 44 may be maintained in a disabled state prior to authentication between device 12 and tester 30 (e.g., using a protocol such as a Secure JTAG protocol). By requiring authentication, JTAG attacks may be thwarted (e.g., tester 30 may be assured of the authenticity of device 12, device 12 can be assured that data received from tester 30 is authorized, and communications between tester and 30 and device 12 can be secured against unauthorized interception). Prior to authentication, JTAG_EN may be deasserted (e.g., held low at a logic “0” value as shown in
In the example of
When the pattern of voltages shown in the “mode 1” column of the table of
If desired, fewer than four voltages may be supplied to contacts 102. For example, voltages V1 and V2 may be provided to contacts P1 and P2, respectively, while contacts P3 and P4 are left floating (as an example). The configurations of
If desired, tester 30 may use controller 98 and input-output circuitry 94 or other control circuitry to generate time-varying signals on contacts 88 of connector 28. Monitor circuit 54 (
Curve 112 of
If desired, tester 30 may use controller 98 and input-output circuitry 94 to impose patterns of one or more different resistances across different respective pairs of contacts 102 to place device 12 into desired modes of operation. As shown in
At step 116, device 12 may use monitor circuit 54 to monitor signals on contacts 102. Monitor circuit 54 may, for example, monitor one or more of contacts 102 to detect voltage levels, resistances, time-varying signals, patterns of signals on multiple contacts, signals with particular values on a single one of contacts 102, etc.
If the signals that monitor circuit 54 detects on contacts 102 of connector 14 indicate that device 12 should be operated normally (e.g., in a non-test mode), device 12 may be operated normally while monitor circuit 54 continues to monitor the status of contacts 102 (e.g., to detect voltages, to detect resistances, to detect time-varying signals, etc.), as indicated by line 118. During these operations, switching circuitry 52 may, as an example, have a normal configuration such as a configuration that couples audio circuit 46 (
In response to detection of a particular signal or pattern of signals (e.g., a predetermined voltage on one contact, a predetermined pattern of voltages on multiple contacts, a resistance or resistances associated with one or more pairs of contacts, a predetermined time-varying signal, or other signals that serve as commands to device 12 to enter test mode), device 12 may enter test mode (step 120). During test mode operations, switching circuitry 52 may be configured to support test operations and testing circuitry may be activated. For example, path 62 may be coupled to path 58 using switching circuitry 52 and JTAG or other testing circuitry 44 may be used to perform test mode operations.
If desired, test mode operations may be secured using a protocol such as a Secure JTAG protocol. As shown in
In response to detection of signals from tester 30 to enter test mode, Secure JTAG debug module 124 and Secure JTAG server 122 may be used to authenticate tester 30 (step 130). If authentication fails, access to JTAG state machine 126 may be blocked (step 132). If authentication is successful, tester 30 may be provided with access to JTAG state machine 126 and device 12 may be tested by tester 30 (step 134). During testing, the control circuitry of device 12 may configure switching circuitry 52 to support test mode operations.
The foregoing is merely illustrative of the principles of this invention and various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention.
