Claims
- 1. An integrated circuit comprising:
a first transistor coupled between a supply voltage and a first node, wherein a control electrode of the first transistor is coupled to a reference voltage; and a second transistor coupled between the first node and an output pad of the integrated circuit, wherein a voltage output high level at the pad will be the lesser of the reference voltage level or the supply voltage.
- 2. The integrated circuit of claim 1 wherein the first transistor is NMOS and the second transistor is PMOS.
- 3. An integrated circuit comprising:
a differential amplifier having a first input coupled to a pad of the integrated circuit and a second input coupled to a reference voltage; a pull-up transistor coupled between a supply voltage and the pad; and a logic gate having an output coupled to a control electrode of the pull-up transistor and an input coupled to an output of the differential amplifier.
- 4. The integrated circuit of claim 3 wherein a voltage output high level at the pad will be the lesser of the reference voltage level or the supply voltage.
- 5. The integrated circuit of claim 3 wherein the differential amplifier outputs a logic one when a voltage level at the pad is greater than a voltage level of the reference voltage.
Parent Case Info
[0001] This is a divisional application of U.S. patent application 09/535,064, filed Mar. 23, 2000, which claims the benefit of U.S. provisional patent application 60/126,235, filed Mar. 24, 1999, which are incorporated by reference along with all references cited in this application.
Provisional Applications (1)
|
Number |
Date |
Country |
|
60126235 |
Mar 1999 |
US |
Divisions (1)
|
Number |
Date |
Country |
Parent |
09535064 |
Mar 2000 |
US |
Child |
09898183 |
Jul 2001 |
US |