Altera Corporation, Data Sheet, “Flex 10K Embedded Programmable Logic Family,” Jul., 1995, ver. 1, pp. 1-39. |
Altera Corporation, Data Sheet, “Apex 20K”, May, 1999, pp. 23-88. |
Chappell et al. “Fast CMOS ECL Receivers With 100-mV Worst-Case Sensitivity,” IEEE Journal of Solid-State Circuits, vol. 23, No. 1, Feb. 1988, pp. 59-66. |
Claude, “Cross-boundary PLDs,” Semiconductor Currents, Jun. 1991, pp. 9-10. |
Guardiani et al. “Applying a submicron mismatch model to practical IC design,” IEEE 1994 Custom Integrated Circuits Conference, 1994, pp. 297-300. |
Gunning et al., “A CMOS Low-Voltage Swing Transmission-Line Transceiver,” IEEE International Solid-State Circuits Conference, 1992, pp. 58-59. |
Haines “Field-programmable gate array with non-volatile configuration,” Microprocessors and Microsystems, vol. 13, No. 5, Jun. 1989, pp. 305-312. |
Hanafi et al. “Design and Characterization of CMOS Off-Chip Driver/Receiver with Reduced Power-Supply Disturbance,” IEEE Journal of Solid-State Circuits, vol. 27, No. 5, May 1992, pp. 783-785. |
Martinez “IEEE 1194.1 BTL-Enabling Technology for High Speed Bus Applications,” National Semiconductor Application Note 829, Jun. 1992, pp. 1-5. |
Knack “Debunking High-Speed PCB Design Myths,” ASIC & EDA, Jul. 1993, pp. 12-26. |
Pelgrom et al. “A 3/5 V Compatible I/O Buffer,” IEEE Journal of Solid-State Circuits, vol. 30, No. 7, Jul. 1995, pp. 823-825. |
Pelgrom et al. “Matching Properties of MOS Transistors,” IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1433-1440. |
Prince et al. “ICs going on a 3-V diet,” IEEE Spectrum , May 1992, pp. 23-25. |
Roberts et al. “Session XIX: High Density SRAMs,” IEEE International Solid-State Circuits Conference, Feb. 27, 1987, pp. 252-254. |
Senthinathan et al., “Application Specific CMOS Output Driver Circuit Design Techniques to Reduce Simultaneous Switching Noise,” IEEE Journal of Solid-State Circuits, vol. 28, No. 12, Dec. 1993, pp. 1383-1388. |
Senthinathan et al., “Simultaneous Switching Ground Noise Calculation for Packaged CMOS Devices,” IEEE Journal of Solid-State Circuits, vol. 26, No. 11, Nov. 1991, pp. 1724-1728. |
Ueda et al. “A 3.3V ASIC for Mixed Voltage Applications With Shut Down Mode,” IEEE 1993 Custom Integrated Circuits Conference, May 9-12, 1993, pp. 25.5.1 to 25.5.4. |
Voldman “ESD Protections ina Mixed Voltage Interface and Multi-Rail Disconnected Power Grid Environment in 0.50- and 0.25-μm Channel Length CMOS Technologies,” EOS/ESD Symposium, 1994, pp. 3.4.1 to 3.4.10. |
Vu et al. “A Gallium Arsenide SDFL Gate Array with On-Chip RAM,” IEEE Journal of Solid-State Circuits, vol. sc-19, No. 1, Feb. 1984, pp. 10-22. |
Williams “Mixing 3-V and 5-V ICs,” IEEE Spectrum, Mar. 1993, pp. 40-42. |