Claims
- 1. A method of forming a PNP transistor, comprising:
- forming a surface layer of P- conductivity at a surface of a P+ substrate;
- forming an isolation region of N- conductivity in said surface layer;
- forming a collector region of P- conductivity in said isolation region by implanting an acceptor impurity through a window, defined by a mask, into said surface layer resulting in the isolation region surrounding and containing said collector region;
- forming a base region of N conductivity in said collector region by implanting a donor impurity through said window into said collector region resulting in the collector region surrounding and containing said base region;
- performing co-diffusion of said base and collector region; and
- forming an emitter region of P+ conductivity in said base region.
- 2. The method of claim 1 wherein said step of forming a layer of P- type conductivity at a surface of a P+ type substrate comprises epitaxially depositing a P- type layer on said substrate.
Parent Case Info
This application is a Continuation of application Ser. No. 08/599,267, filed Feb. 9, 1996, abandoned, which is a continuation of Ser. No. 08/310,610, filed Sep. 22, 1994, abandoned.
US Referenced Citations (8)
Non-Patent Literature Citations (2)
Entry |
Analysis and Design of Analog Integrated Circuits, (Third Ed.) by Gray and Meyer, John Wiley & Sons, Inc. pp. 148-149 (1993). |
S. Wolf & R.N. Tauber, "Silicon Processing for the VLSI ERA" vol. I, 1986 pp. 242-245, 296-299. |
Continuations (2)
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Number |
Date |
Country |
Parent |
599267 |
Feb 1996 |
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Parent |
310610 |
Sep 1994 |
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