The present invention relates generally to semiconductors and more particularly to isolated Zener diodes and methods of making the same.
Zener diodes are some of the most extensively-used components in semiconductor technology, being used for a wide variety of applications, including voltage regulation and protection from electrostatic discharge events. Two different kinds of breakdown current may affect the operation of a diode at breakdown: impact ionization, or avalanche breakdown current; and tunneling, or Zener breakdown current. The term “Zener diode,” as it is classically used, and as it will be used herein, refers to a diode in which tunneling breakdown and avalanche breakdown occur simultaneously.
In power integrated circuit (IC) technology, the Zener diode is commonly integrated into a circuit and is in “discrete” form as a separate unit as is normally the case. In general, Zener diodes, especially when used in smart power technologies, should have both zero temperature coefficient (“zero TC”) and long term stability. Zero temperature coefficient means that the reverse voltage is substantially invariant with temperature, within a useful temperature range. Long term stability means that the reverse voltage does not change with time over the useful life of the device. Due to Zener diode's zero TC and long term stability, they are widely used in voltage clamping and reference. However, conventional Zener diodes suffer from substrate current injection when forward biased. This substrate current injection may result in design difficulty since the diode's two terminal currents are not the same. The injected current may also disturb operation of other parts of the circuit.
Accordingly, it is desirable to develop a Zener diode that retains characteristics of zero TC and long term stability, and that also has reduced substrate current when forward biased. In addition, it is desirable that the Zener diode not disturb operation of other components of the circuit with which it is integrated. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.
A more complete understanding of the present disclosure may be derived by referring to the detailed description and claims when considered in conjunction with the following figures. For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the described technology. Additionally, elements in the drawing figures are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of embodiments of the present invention. The same reference numerals in different figures may denote the same elements.
The following detailed description is merely illustrative in nature and is not intended to limit the scope of the claims and uses of the devices herein disclosed. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background or the following detailed description.
As a preliminary matter, the terms “first,” “second,” “third,” “fourth,” and the like in the description and in the claims, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. In addition, a first semiconductor region having a first conductivity may, for example, have the same conductivity as a second semiconductor region having a second conductivity. Thus while regions may be distinct by numbering as “first” and “second”, associated properties may not be distinct. Furthermore, the terms “comprise,” “include,” “have,” and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Further, the terms “left,” “right,” “front,” “back,” “top,” “bottom,” “over,” “under,” in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
In addition, the terms “inboard” and “outboard” as used herein, relate to position relative to a central axis of symmetry or other point, line or plane of reference. Thus, “inboard” means closer to the reference than another component; and “outboard” means further from the reference than another component. Unless otherwise indicated, the frame of reference in this disclosure is a center line or plane of symmetry.
The present disclosure relates to isolated Zener diodes that are substantially free of substrate current injection when forward biased. While the isolated Zener diodes provide near zero substrate injection currents, the magnitude of any injection current depends upon other factors as well, such as for example any potential applied to the isolation. In general, the term “substantially free of substrate injection current” means that the isolated Zener diodes have an injection current, when forward biased, of less than about 8%, and more especially less than about 3%, of the total anode current when cathode, body and isolation are at the same potential; and, when a 5 volt potential is applied to the isolation, the injection current reduces further to less than about 1% and more especially less than about 0.3% of total anode current. These isolated Zener diodes will consequently find many uses, especially in advanced smart power technologies.
In
Referring now to
In the central region of diode 100 (i.e. the right side of
The diode structure extending from layer 130 to cathode 220 includes the following regions. The region above layer 140 [may be 160 (if present) or 165 (if region 160 is not present)], includes a region 180. Region 180 may be a heavily doped n-type well. A cathode 220 is formed in the upper surface region of region 180. As shown, peripheral areas of region 180 interface with peripheral areas of region 170 and also peripheral areas of region 160, underlying the anode 210.
In
Referring to the left side of
A silicide block or layer 260 extends between cathode 220 and anode 210 on the upper surface of the Zener diode 100. In addition, oxide regions 270 extend between isolation 250 and body 230, and between body 230 and cathode 220. These are not shown in
In the embodiment of
In general, examples of the isolated Zener diodes of this disclosure have substrate injection currents of as little as 0.5% to about 3% of the total anode current when forward biased, as can be seen in the graph of
It will be readily apparent to one of skill in the art who has read this disclosure and reviewed the drawings that there are a variety of ways to make the isolated Zener diodes of the present disclosure. One example will be explained, with the understanding that other methods with modifications and variations within the scope of knowledge of a person of ordinary skill in the art are within the scope of the appended claims.
Referring to
A Zener diode that includes a first semiconductor region having a first conductivity with an anode formed in the first region. It also has a second semiconductor region having a second conductivity with a cathode formed in the second region. There is also a third semiconductor region, below the first and second regions and spaced apart from the first and second regions. In addition, there is a fourth semiconductor region extending vertically, located outboard of the first and second semiconductor regions. A silicide block extends from the cathode region to the anode region. When the diode is forward biased, it is substantially free of substrate injection current. The third region may be a highly doped n-type buried layer. The fourth semiconductor region may be a moderately doped n-type well. The fourth semiconductor region, which surrounds the first and second regions, may substantially form sides of a tub shape, with the third region as a base of the tub.
In addition, the diode may have a moderate to highly doped p-type fifth region interposed between the first region and the third region, and between the second region and the third region.
The fourth region may include an upper region comprising a moderately doped n-type well, and a lower region comprising a heavily doped n-type sinker region.
The perimeters of the first region and second region may not be in contact with a perimeter of the fifth region.
The diode may further include a sixth region interposed between the first region and the fifth region, and between the second region and the fifth region. The sixth region may be a p-type epitaxial region.
The diode has a substrate injection current of less than about 3.0% of the total anode current when no potential is applied to an isolation, and less than about 0.3% of total anode current when a 5 volt potential is applied to the isolation relative to the body.
In another embodiment, there is presented a Zener diode that includes four regions. A first semiconductor region includes a moderately doped n-type well with an anode formed in the first region. A second semiconductor region includes a highly doped n-type well with a cathode formed in the second region. A third semiconductor region includes a highly doped n-type buried layer. The third region is located below the first and second regions and spaced apart from the first and second regions. A fourth semiconductor region extends vertically, outboard of the first and second semiconductor regions. The fourth semiconductor region surrounds the first and second regions and substantially forms sides of a tub shape, with the third region as a base of the tub. A silicide block extends from the vicinity of the cathode region to the vicinity of the anode region. When the diode is forward biased, it is substantially free of substrate injection current.
When forward biased, substrate injection current may be less than about 3.0% of the total anode current when cathode body and isolation are at the same potential, and less than about 0.3% of total anode current when a 5 volt potential is applied to the isolation relative to he body.
The diode may in addition include a moderate to highly doped p-type fifth region interposed between the first region and the third region, and between the second region and the third region. Further, the diode may include a sixth region interposed between the first region and the fifth region, and between the second region and the fifth region. The sixth region may be a p-type epitaxial region.
The present disclosure also includes a method of making an isolated Zener diode that includes several process steps. The process includes forming a first semiconductor region having a first conductivity; forming a second semiconductor region having a second conductivity; forming an anode in the first region and a cathode in the second region; forming a third semiconductor region, below the first and second regions, the region spaced apart from the first and second regions; and forming a fourth semiconductor region extending vertically, the fourth region outboard of the first and second semiconductor regions so that the fourth region forms walls of a tub and the third region forms a base of the tub. A silicide block is configured to extend from the vicinity of the cathode region to the vicinity of the anode region.
The method may include forming the third semiconductor region to include an n-type buried layer. Further, the method may include forming the fourth semiconductor region to include a moderately doped n-type well. In addition, the method includes the possibility of forming the fourth semiconductor region to include a moderately doped n-type well. Forming the fourth region may include forming and upper region and forming a lower region. The upper region may be a moderately doped n-type well, and the lower region may be a highly doped n-type sinker region.
The following example is intended to illustrate an advantage of an embodiment of the present disclosure and does not limit the scope of the disclosure or the appended claims.
Substrate injection currents were compared for a pair of Zener diodes: a Control Zener diode A and an isolated Zener diode according to the present disclosure.
For the control Zener diode, measurements were taken while the cathode and the substrate were ground while ramping the anode from 0 to 2 volts (curve A). For the isolated Zener diode, the measurement was done by ramping the anode from 0 to 2 volts while keeping other terminals at ground (substrate, body, cathode and isolation terminals). The measured result is shown in
The results are shown in
While at least one example embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the example embodiment or embodiments described herein are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the described embodiment or embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope of the invention as set forth in the appended claims and the legal equivalents thereof.