1. Field of the Invention
The present invention relates to three-dimensional (3D) memory devices. In particular, embodiments according to the present invention provide a method for manufacturing bit lines and word lines in such memory devices, and a memory structure that can be made using the method.
2. Description of Related Art
High density memory devices are being designed that comprise arrays of flash memory cells, or other types of memory cells. In some examples, the memory cells comprise thin film transistors which can be arranged in three dimensional (3D) architectures.
In one example, a 3D memory device includes a plurality of stacks of strings of memory cells. The stacks include active strips separated by insulating material. The 3D memory device includes an array including a plurality of word lines structures, a plurality of string select structures, and ground select lines, arranged orthogonally over the plurality of stacks. Memory cells including charge storage structures are formed at cross-points between side surfaces of the active strips in the plurality of stacks and the word lines structures.
The 3D memory device is characterized by multiple planes, each of which can include a planar array of active strips. Active strips in a plane can terminate at one end at a contact pad, and at another end at a source line. At either end, active strips can have irregular and discontinuous patterns. Such patterns present challenges for manufacturing processes including etching processes for active strips. Furthermore, patterns for string select gate structures are isolated between adjacent stacks, while patterns for word lines are not isolated between adjacent stacks. Thus, it can be complicated for an etch process to form both word lines and string select gate structures due to different patterns for word lines and string select gate structures.
It is desirable to improve manufacturing processes for 3D memory devices that can result in higher reliability and lower costs.
A method for manufacturing a semiconductor device includes providing a substrate having a plurality of active layers, forming a plurality of holes through the plurality of active layers, and filling the plurality of holes with an isolation material such as oxide seals to form filled holes. The plurality of holes is positioned in the plurality of active layers such that a plurality of stacks of active strips can be formed in the plurality of active layers after the filling, and be terminated at the plurality of holes filled with the isolation material.
In one embodiment, the plurality of holes can be configured in a row. A mask can be used to define a plurality of parallel lines, including lines that cross over respective filled holes in the plurality of holes. The plurality of active layers and the filled holes can be etched using a first etch process, to form the plurality of stacks of active strips terminating with strips of isolation material where the lines crossed over the respective holes.
In an alternative embodiment, the plurality of holes can be configured in a first row and a second row. A mask can be used to define a plurality of parallel lines, including a first subset of lines that cross over respective filled holes in the first row, and a second subset of lines that cross over respective filled holes in the second row. The plurality of active layers and the filled holes can be etched using a first etch process, to form the plurality of stacks of active strips including a first set of stacks terminating with strips of isolation material where the lines crossed over the respective holes in the first row of holes, and a second set of stacks terminating with strips of isolation material where the lines crossed over the respective holes in the second row of holes. Select gate structures can be formed over stacks of active strips in the first set of stacks between strips of isolation material at which stacks in the second set of stacks terminate.
In another embodiment, the plurality of holes can be configured in a first row, and a plurality of conductive pillars can be configured in a second row. A mask can be used to define a plurality of parallel lines, including lines that cross over respective filled holes in the first row and respective conductive pillars in the second row. The plurality of active layers, the conductive pillars and the filled holes can be etched using a first etch process, to form the plurality of stacks of active strips including strips of more narrow conductive pillars and terminating at strips of isolation material where the lines crossed over the respective holes and conductive pillars.
The plurality of active layers and the isolation material in the plurality of holes can be etched using a first etch process, to form the plurality of stacks of active strips, and a plurality of isolation strips aligned with the stacks. The substrate can have a plurality of spaced-apart pillars of a first conductor material connecting the plurality of active layers. The plurality of spaced-apart pillars can be etched using the first etch process, to form a plurality of more narrow conductive pillars aligned with the stacks and between a first end of the plurality of active strips and the plurality of isolation strips. The plurality of active layers can be etched using the first etch process, to form stacks of contact pads terminating the plurality of active strips at a second end of the plurality of active strips.
A body of conductor material can be formed by depositing a second conductor material over the substrate. The body of conductor material can be etched using a second etch process, to remove the second conductor material from areas defining patterns for the plurality of active strips, the plurality of source lines, the plurality of isolation strips, the stacks of pads, word lines, ground select lines and string select gate structures. The body of conductor material can be etched using a third etch process, to form the word lines, the ground select lines and the string select gate structures over the plurality of stacks. A string select gate structure over a particular stack in the plurality of stacks is isolated from string select gate structures over adjacent stacks in the plurality of stacks.
A layer of memory material can be formed on side walls of the active strips in the plurality of stacks before the body of conductor material is formed over the substrate.
An integrated circuit device made according to the method is also provided.
Other aspects and advantages of the present invention can be seen on review of the drawings, the detailed description and the claims, which follow.
A detailed description of various embodiments is described with reference to the Figures. The following description will typically be with reference to specific structural embodiments and methods. It is to be understood that there is no intention to limit the invention to the specifically disclosed embodiments and methods but that the invention may be practiced using other features, elements, methods and embodiments. Preferred embodiments are described to illustrate the present invention, not to limit its scope, which is defined by the claims. Those of ordinary skill in the art will recognize a variety of equivalent variations on the description that follows. Like elements in various embodiments are commonly referred to with like reference numerals.
In the example shown in
A stack of contact pads 112A, 113A, 114A, and 115A terminate active strips, such as the active strips 112, 113, 114, and 115 in the plurality of stacks. As illustrated, these contact pads 112A, 113A, 114A, and 115A are electrically connected to different bit lines for connection to decoding circuitry to select planes within the array. These contact pads 112A, 113A, 114A, and 115A can be patterned at the same time that the plurality of stacks is defined.
A stack of contact pads 102B, 103B, 104B, and 105B terminate active strips, such as active strips 102, 103, 104, and 105. As illustrated, interlayer connectors 172, 173, 174, 175 electrically connect contact pads 102B, 103B, 104B, and 105B to different bit lines in metal layers, such as a metal layer ML3, for connection to decoding circuitry to select planes within the array. The stack of contact pads 102B, 103B, 104B, and 105B can be patterned at the same time that the plurality of stacks is defined.
Any given stack of active strips is coupled to either the stack of contact pads 112A, 113A, 114A, and 115A, or the stack of contact pads 102B, 103B, 104B, and 105B, but not both. The stack of active strips 112, 113, 114, and 115 is terminated at one end by the stack of contact pads 112A, 113A, 114A, and 115A, passes through SSL gate structure 119, ground select line GSL 126, word lines 125-1 WL through 125-N WL, ground select line GSL 127, and is terminated at the other end by source line 128. The stack of active strips 112, 113, 114, and 115 does not reach the stack of contact pads 102B, 103B, 104B, and 105B.
The stack of active strips 102, 103, 104, and 105 is terminated at one end by the stack of contact pads 102B, 103B, 104B, and 105B, passes through SSL gate structure 109, ground select line GSL 127, word lines 125-N WL through 125-1 WL, ground select line GSL 126, and is terminated at the other end by a source line (obscured by other parts of the figure). The stack of active strips 102, 103, 104, and 105 does not reach the stack of contact pads 112A, 113A, 114A, and 115A.
A layer of memory material is disposed in interface regions at cross-points between surfaces of the active strips 112-115 and 102-105 and the plurality of word lines 125-1 WL through 125-N WL. In particular, the layer of memory material is formed on side walls of the active strips in the plurality of stacks. Ground select lines GSL 126 and GSL 127 are conformal with the plurality of stacks, similar to the word lines.
Every stack of active strips is terminated at one end by contact pads and at the other end by a source line. For example, the stack of active strips 112, 113, 114, and 115 is terminated at one end by contact pads 112A, 113A, 114A, and 115A, and terminated on the other end by a source line 128. At the near end of the figure, every other stack of active strips is terminated by the contact pads 102B, 103B, 104B, and 105B, and every other stack of active strips is terminated by a separate source line. At the far end of the figure, every other stack of active strips is terminated by the contact pads 112A, 113A, 114A, and 115A, and every other stack of active strips is terminated by a separate source line.
Bit lines and string select gate structures are formed at the metals layers ML1, ML2, and ML3. Bit lines are coupled to a plane decoder (not shown). String select gate structures are coupled to a string select line decoder (not shown).
The ground select lines GSL 126 and 127 can be patterned during the same step that the word lines 125-1 WL through 125-N WL are defined. Ground select devices are formed at cross-points between surfaces of the plurality of stacks and ground select lines GSL 126 and 127. The SSL gate structures 119 and 109 can be patterned during the same step in which the word lines 125-1 WL through 125-N WL are defined. String select devices are formed at cross-points between surfaces of the plurality of stacks and string select (SSL) gate structures 119 and 109. These devices are coupled to decoding circuitry for selecting the strings within particular stacks in the array.
The memory device includes a first row and a second row of isolation strips, and a first set and a second set of interdigitated stacks of active strips. The first set includes active strips (e.g. 112-115) extending from contact pads in a first stack of contact pads (e.g. 112A-115A), and terminating at corresponding isolation strips in the first row of isolation strips (e.g. 129). The second set includes active strips (e.g. 102-105) extending from contact pads in a second stack of contact pads (e.g. 102B-105B), and terminating at corresponding isolation strips in the second row of isolation strips (not shown). A source line (e.g. 128) is aligned with a stack of active strips (e.g. 112-115) in the Y direction, and between the active strips (e.g. 112-115) and an isolation strip (e.g. 129). The isolation strip 129 can be an example of an isolation strip in either the first row of isolation strips or the second row of isolation strips.
The active layers (e.g. 210) can be made using intrinsic or lightly doped polysilicon while the pillars (e.g. 221, 222) can be made using relatively heavily doped n+-type polysilicon or other conductive material selected for conductivity and compatibility with the manufacturing processed utilized. The pillars (e.g. 128,
In the embodiment illustrated, for the formation of interdigitated active strips, the plurality of holes are arranged in a first row including a first hole 331, and in a second row including a second hole 332. The first row of holes and the second row of holes are arranged along the X direction in the X-Y plane. The first row of holes is aligned with the first row of conductive pillars in the Y direction, and the second row of holes is aligned with the second row of conductive pillars in the Y direction. For example, the first hole 331 in the first row of holes is aligned with the first conductive pillar 221 in the first row of conductive pillars, and the second hole 332 in the second row of holes is aligned with the second conductive pillar 222 in the second row of conductive pillars. In other embodiments, the active strips may not be interdigited for example, and the isolation holes may be formed in only one row.
Although the plurality of holes are illustrated in layout view showing one active layer (e.g. 210), each of the holes is as deep as the plurality of active layers in the Z direction perpendicular to the X-Y plane. The holes filled with the isolation material (e.g. 331, 332) are used to form isolation strips at one end of active strips (e.g. 112-115,
Bit line pad cuts (e.g. 341, 342) can be made to divide the device into blocks of stacks of active strips such that layers of active strips in the blocks can support respective bit lines via contact pads in the respective blocks. For instance, a block with four layers of active strips can support four bit lines, while another block with four layers of active strips can support four other bit lines. In one embodiment, the bit line pad cuts can be made in the same process to etch the plurality of isolation holes, and then to fill the holes with the isolation material such as silicon oxide or silicon nitride. The bit line pad cuts can be filled with the same isolation material as the plurality of isolation holes. Although the bit line pad cuts are illustrated in layout view showing one active layer (e.g. 210), each of the bit line pad cuts is as deep as the plurality of active layers in the Z direction perpendicular to the X-Y plane.
In one embodiment, as illustrated in
In an alternative embodiment, the plurality of holes can be configured in a first row and a second row. For instance, the plurality of holes are arranged in a first row including a first hole 331 (
Furthermore, as illustrated in the example of
In another embodiment, the plurality of holes can be configured in a first row, and a plurality of conductive pillars can be configured in a second row. For instance, the plurality of holes are arranged in a first row including a first hole 331 (
As illustrated in the example of
A plurality of isolation strips is formed by the first etching process from the first row of holes and the second row of holes filled with the isolation material (e.g. 331, 332,
A plurality of more narrow conductive pillars is formed by the first etching process from the first row of conductive pillars and the second row of conductive pillars (e.g. 221, 222,
Stacks of contact pads are formed by the first etching process from the plurality of active layers (e.g. 210,
As illustrated in
The plurality of isolation strips, already formed using the first etch process (
The third etch process also removes the remaining portions of the body of conductor material 510 that are not portions of the word lines, the ground select lines, and the string select gate structures. The remaining portions removed include the portions over the stacks of pads (BL pad), over the plurality of source lines, and over the plurality of isolation strips.
Depending upon the implementation, layer 895 of memory material can comprise multilayer dielectric charge storage structures. For example, a multilayer dielectric charge storage structure includes a tunneling layer including a silicon oxide, a charge trapping layer comprising a silicon nitride and a blocking layer comprising a silicon oxide. In other implementations, layer 895 of memory material can include only a charge trapping layer without the tunneling layer or the blocking layer.
In other embodiments, different programmable resistance memory materials can be used as the memory material, including metal oxides like tungsten oxide on tungsten or doped metal oxide, and others. Various kinds of programmable metallization material can also be implemented as the memory material to form programmable metallization cells (PMC). Some of such materials can form devices that can be programmed and erased at multiple voltages or currents, and can be implemented for operations storing multiple bits per cell.
As described here, the plurality of stacks of active strips in the memory device is formed in first and second sets of interdigitated stacks of active strips. The first set includes strips extending from contact pads in a first stack of contact pads and terminating at corresponding isolation strips in a first row of isolation strips, and the second set includes strips extending from bit lines pads in a second stack of contact pads and terminating at corresponding isolation strips in a second row of isolation strips.
As illustrated in the cross-sectional view in
Then, a plurality of holes is formed by etching through the plurality of active layers (920), and the holes are filled with an isolation material such as oxides or silicon nitride. The plurality of holes are arranged in a first row and a second row. The first row of holes is aligned with the first row of conductive pillars, and the second row of holes is aligned with the second row of conductive pillars.
The substrate is etched using a first etch process to form a plurality of stacks of active strips, a plurality of isolation strips aligned with the stacks, and stacks of contact pads terminating the plurality of active strips at a second end of the plurality of active strips (930).
The substrate, including the plurality of spaced-apart pillars of a first conductor material as precursor formations for forming source lines, is also etched using the first etch process to form a plurality of more narrow conductive pillars (e.g. 421, 422,
A layer of memory material is deposited over the plurality of stacks of active strips, and at least on side walls of the active strips (950). The layer of memory material can include multilayer dielectric charge storage structures, and different programmable resistance memory materials.
A body of conductor material is then formed by depositing a second conductor material over the substrate. The body of conductor material is etched using a second etch process to remove the second conductor material from certain areas (960). The removed areas define patterns for the plurality of active strips, the plurality of source lines, the plurality of isolation strips, the stacks of contact pads, word lines, ground select lines and string select gate structures.
The body of conductor material is etched using a third etch process to form the word lines, the ground select lines and the string select gate structures over the plurality of stacks (970). A string select gate structure over a particular stack in the plurality of stacks is isolated from string select gate structures over adjacent stacks in the plurality of stacks.
A row decoder 1040 is coupled to a plurality of word lines 1045, and arranged along rows in the memory array 1060. A column decoder 1070 is coupled to a plurality of bit lines 1065 arranged along columns in the memory array 1060 for reading and programming data from the memory cells in the memory array 1060. A bank decoder 1050 is coupled to a plurality of banks in the memory array 1060 on bus 1055. Addresses are supplied on bus 1030 to column decoder 1070, row decoder 1040 and bank decoder 1050. Sense amplifiers and data-in structures in block 1080 are coupled to the column decoder 1070, in this example via data bus 1075. Sensed data from the sense amplifiers are supplied via output data lines 1085 to output circuits 1090. Output circuits 1090 drive the sensed data to destinations external to the integrated circuit 1000. Input data is supplied via the data-in line 1005 from input/output ports on the integrated circuit 1000 or from other data sources internal or external to the integrated circuit 1000, such as a general purpose processor or special purpose application circuitry, or a combination of modules providing system-on-a-chip functionality supported by the memory array 1060, to the data-in structures in block 1080.
In the example shown in
While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.