CROSS-REFERENCE TO RELATED APPLICATIONS
This application refers to and claims the priority date of U.S. provisional patent 63468190 entitled “HighEgPT&IsothermalBond” filed on 22 May 2023 with EFS ID 48040488, the disclosure of which is hereby incorporated by reference in its entirety.
FIELD OF THE EMBODIMENTS
The embodiments relate to heterogenous wafer to wafer bonding of semiconductor wafers of different substrate materials.
DESCRIPTION OF RELATED ART
Although silicon wafer to silicon wafer bonding is a mature technology in mass manufacturing, the state of the art for bonding heterogeneous materials is still limited to dice. This invention teaches the heterogenous wafer to wafer bonding of semiconductor wafers of different substrate materials at the whole wafer scale.
SUMMARY OF THE EMBODIMENTS
One embodiment disclosed herein relates to a method of wafer-to-wafer bonding between at least one pair of semiconductor wafers having different substrate materials, and subsequent removal of a substrate of at least one wafer of the at least one pair of semiconductor wafers. In the embodiment, the method includes bringing at least one pair of semiconductor wafers of different substrate materials into direct physical contact at a temperature within ±10° C. of a bonding temperature required to bond the at least one pair of semiconductor wafers to one another, to thereby bond the at least one pair of semiconductor wafers to one another. The method further includes removing from at least one semiconductor wafer of the at least one pair of semiconductor wafers at least 90% of the substrate thickness over at least 90% of the area of the at least one semiconductor wafer at a temperature within ±10° C. of the bonding temperature required to bond the at least one pair of semiconductor wafers to one another. In accordance with this embodiment, the method provides direct physical contact between the at least one pair of semiconductor wafers and prohibits and excludes subsequent heating or annealing or cooling outside the temperature range of ±10° C. of the bonding temperature of the at least one pair of semiconductor wafers before the removal is completed. In another embodiment, the different substrate materials are formed from constituent atoms that are at least 90% different from one another.
BRIEF DESCRIPTION OF THE FIGURE
FIGS. 1 through 4 illustrate embodiments of an isothermal heterogeneous wafer-to-wafer bonding and substrate removal process not drawn to scale. The figures illustrate a method of bonding a pair of semiconductor wafers of different substrate materials and subsequent removal of most of the substrate of at least one wafer of the pair of wafers.
FIG. 1 illustrates an embodiment of bonding focal plane array (FPA) epitaxial wafers on indium phosphide (InP) substrates to readout integrated circuit (ROIC) wafer on silicon (Si) substrate at 20˜22° C. temperature range.
FIG. 2 illustrates an embodiment of applying perfluoropolyether (PFPE) inert grease to seal the exposed wafer bonding interfaces at 20˜22° C.
FIG. 3 illustrates an embodiment of etching InP substrates in an acid comprising > 1/10 weight of HCl stopping at arsenide epitaxial layers inside the FPA epitaxial wafers at 20˜22° C.
FIG. 4 illustrates another embodiment of dissolving and removing the PFPE inert grease in PFPE solvent, and annealing the bonded wafer pairs above 20˜22° C.
DETAILED DESCRIPTION
In this disclosure, two processes are considered to be “in sequential temporal order” if and only if the first of the two processes is performed and completed before the second process, and the second of the two processes is started and performed after the first process with optional process(es) allowable between the first and second processes. In this disclosure, two processes are considered to be “consecutive” if and only if the first and second processes are performed back to back with no break between them, which prohibits any other process or break between the first and second processes.
Sequentiality and consecutiveness as defined above do not require or imply each other.
One embodiment shown in FIGS. 1 through 4 (not drawn to scale) illustrates an isothermal heterogeneous wafer-to-wafer bonding and substrate removal process involving a method of bonding a pair of semiconductor wafers of different substrate materials and subsequent removal of most of the substrate of at least one wafer of the pair of wafers. In this specific embodiment, the method of wafer-to-wafer bonding between at least one pair of semiconductor wafers having different substrate materials, and subsequent substantial removal of a substrate of at least one wafer of the at least one pair of semiconductor wafers, may include the following five steps (i), (ii), (iii), (iv) and (v) in sequential temporal order.
Steps (i) and (iii) are mandatory. Steps (ii), (iv) and (v) are optional. FIG. 1 shows the mandatory step (i) to bond focal plane array (FPA) epitaxial wafers on indium phosphide (InP) substrates to readout integrated circuit (ROIC) wafer on silicon (Si) substrate at 20˜22° C. temperature range. The mandatory step (i) brings at least one pair of semiconductor wafers of different substrate materials into direct physical contact at a temperature within ±10° C., ±3° C. or ±1° C. of a bonding temperature 21° C. required to bond the at least one pair of semiconductor wafers to one another, to thereby bond the at least one pair of semiconductor wafers to one another.
The bonding temperature required to bond the at least one pair of semiconductor wafers to one another is between 0° C. and 100° C., inclusive. The bonding temperature required to bond the at least one pair of semiconductor wafers to one another is between 20° C. and 22° C., inclusive. A first wafer of the at least one pair of semiconductor wafers may comprise a focal plane array (FPA) epitaxial wafer on InP substrate 2, and/or a second wafer of the at least one pair of semiconductor wafers may comprise a readout integrated circuit (ROIC) wafer on Si substrate 1. This first step (i) provides direct physical contact between the at least one pair of semiconductor wafers and prohibits and excludes subsequent heating or annealing or cooling outside the temperature range of ±10° C., ±3° C. or ±1° C. of the bonding temperature 21° C. of the at least one pair of semiconductor wafers before step (iii) completes. The different substrate materials of ROIC wafer 1 and FPA wafer 2 are comprised of constituent atoms that are at least 90% different from one another.
FIG. 2 shows the optional step (ii) to apply perfluoropolyether (PFPE) inert grease to seal exposed wafer bonding interfaces at 20˜22° C. Step (ii) is the additional processing between step (i) and step (iii) at a temperature within ±10° C., ±3° C. or ±1° C. of the bonding temperature 21° C. The PFPE inert grease 3 seals the exposed wafer bonding interface formed between the ROIC wafer on Si substrate 1 and the FPA epitaxial wafer on InP substrate 2.
FIG. 3 shows the mandatory step (iii) to etch InP substrates in an acid comprising > 1/10 weight of HCl stopping at arsenide epitaxial layers inside the FPA epitaxial wafers at 20˜22° C. This mandatory step removes from at least one semiconductor wafer of the at least one pair of semiconductor wafers at least 90% of the substrate thickness over at least 90% of the area of the at least one semiconductor wafer at a temperature within ±10° C., ±3° C. or ±1° C. of the bonding temperature 21° C. required to bond the at least one pair of semiconductor wafers to one another.
In one embodiment, at least 99% of the substrate thickness is removed. The entirety of the substrate thickness is removed, leaving only epitaxial portions of the original semiconductor wafer. One wafer substrate of the at least one pair of semiconductor wafers is InP with or without dopant, and the other wafer substrate of the at least one pair of semiconductor wafers is Si with or without dopant. The entire thickness of the doped or undoped InP substrate is removed in step (iii) by an acid comprising no less than 1% or 10% by weight of hydrochloric acid (HCl), and the InP substrate removal etch stops at an essentially arsenide epitaxial layer. The PFPE inert grease 3 still seals the exposed wafer bonding interface formed between the ROIC wafer on Si substrate 1 and the FPA epitaxial wafer with InP substrate substantially removed 4.
FIG. 4 shows the optional step (iv) to dissolve and remove the PFPE inert grease in PFPE solvent and the optional step (v) to anneal bonded wafer pairs above 20˜22° C. The at least one pair of semiconductor wafers comprising the at least one semiconductor wafer whose substrate was removed in step (iii) is heated to and/or annealed at a temperature more than 10° C. above the bonding temperature 21° C. after completion of steps (i) and (iii). The at least one pair of semiconductor wafers comprising the at least one semiconductor wafer whose substrate was removed in step (iii) is heated to and/or annealed at a temperature more than 10° C. above the bonding temperature 21° C. after completion of step (i), the additional processing step (ii) and step (iii).
The result is the FPA epitaxial wafer with InP substrate substantially removed 4 wafer-to-wafer bonded to the ROIC wafer on Si substrate 1. The at least one pair of semiconductor wafers comprises a total of no less than 107, 108, 109 or 1010 pixels and no less than 107, 108, 109 or 1010 readout unit cells. The method bonds multiple wafers of a first type to a single wafer of a second type, and each substrate of the multiple wafers of the first type is substantially removed.
B. F. Levine & A. R. Hawkins & S. Hiu & B. J. Tseng & J. P. Reilley & C. A. King & L. A. Gruezke & R. W. Johnson & D. R. Zolnowski & J. E. Bowers stated in their paper “Characterization of wafer bonded photodetectors fabricated using various annealing temperatures and ambients”: “In order to better understand the bonding process and the optimum fusion conditions, we have performed a systematic variation of the bonding temperature (T=650, 550, and 475° C.) and the surrounding flowing gas ambient (H2,N2, and forming gas consisting of 10% H2+90% N2) . . . . These wafers were fused in an oven using the following conditions: 650° C. in H2, 650° C. in N2; 650° C. in forming gas (10% H2+90% N2), 550° C. in H2 and 475° C. in H2. After bonding, the InP substrate and the InGaAs etch stop layer were removed” at unspecified temperature. Since most InP etches do not exceed 300° C., their bonding process at ≥475° C. and their substrate removal process at <300° C. are not performed within the temperature range required by this patent application. Refer to B. F. Levine & A. R. Hawkins & S. Hiu & B. J. Tseng & J. P. Reilley & C. A. King & L. A. Gruczke & R. W. Johnson & D. R. Zolnowski & J. E. Bowers, “Characterization of wafer bonded photodetectors fabricated using various annealing temperatures and ambients”, Appl. Phys. Lett., 15 Sep. 1997; 71 (11): 1507-1509.
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Patent Application
20240395633
