Patent Application
20080240296
This disclosure is generally directed to wireless data communication networks and more particularly to systems and methods for estimating and correcting large carrier frequency offsets.
In conventional wireless data communication networks, clock frequency variations among members of the network produce carrier frequency offsets that may approach the same order of magnitude as symbol rates, resulting in high symbol error rates.
Conventional methods typically implement parallel hardware such as, for example, a channelized bank of matched filters spanning the expected range of frequency offset. The difference in center frequencies of the filter bank is selected to be less than the lock range of the phase-locked loop (PLL) circuit. The frequency of the filter channel yielding maximum energy is the frequency to which the digital downconverter should be tuned for coarse translation prior to the PLL. Accordingly, such conventional methods require the addition of certain hardware to implement the parallel filter bank.
Other conventional methods employ a Fast Fourier Transform (FFT) that interrogates the entire frequency span collected by the input time-sampling process. The time series is first windowed to minimize boundary-related artifacts, transformed, and then converted to a power spectrum. A series of successive power spectra may be averaged to improve the overall spectral estimate. The frequency of the peak-energy spectrum bin is the frequency to which the digital downconverter should be tuned for coarse translation prior to the PLL. Such conventional methods require relatively less hardware to implement.
Still other conventional methods implement a sequential filter bank with a single downconverter and matched filter that is time shared across the frequency-offset search range by applying an FM sweep to the local digital oscillator. The sweep is terminated and held when the energy detector declares a detected peak. Such conventional methods limit hardware complexity, but require a significant increase in preamble time to acquire a lock.
There is therefore a need for an improved system and method for estimating and correcting large carrier frequency offsets without significantly increasing receiver hardware complexity or preamble length.
This disclosure provides a system and method for estimating and correcting large carrier frequency offsets without significantly increasing receiver complexity or preamble length. Thus, the systems and methods according to embodiments of the present disclosure increase reliability with respect to decoding headers and payloads.
In one embodiment, the present disclosure provides a method of sequential carrier acquisition. The method includes varying a downconverter frequency through a sequence of frequencies. The method also includes synchronizing changes in the downconverter frequency with incoming symbols. The method further includes iteratively updating a frequency estimate associated with the incoming symbols and decreasing a search step size until convergence occurs.
In another embodiment, the present disclosure provides a method of sequential carrier acquisition in a receiver for use in a communication network. The method includes initializing a receiver and setting an initial frequency step size based on a previously determined nominal value. The method also includes varying a downconverter frequency through a sequence of frequencies beginning with the initial frequency step size. The method further includes synchronizing changes in the downconverter frequency with incoming symbols. The method still further includes iteratively updating a frequency estimate associated with the incoming symbols and decreasing the frequency step size until convergence occurs.
In another embodiment, the present disclosure provides a receiver for use in a communications network. The receiver includes a circuit configured to vary a downconverter frequency through a sequence of frequencies. The circuit may also synchronize downconverter frequency changes with incoming symbols. The circuit may further iteratively update a frequency estimate associated with the incoming symbols and decrease a search step size until convergence occurs.
Other technical features may be readily apparent to one skilled in the art from the following figures, descriptions and claims.
For a more complete understanding of this disclosure and its features, reference is now made to the following description, taken in conjunction with the accompanying drawings, in which:
The present disclosure provides a system and method for estimating and correcting large carrier frequency offsets without adding significantly to receiver complexity or preamble length. Embodiments of the present disclosure perform coarse frequency estimation during a brief carrier acquisition phase that is completed during a reasonably short preamble, and then hands frequency control to the nominal carrier frequency & phase tracking of a phase-locked loop (PLL) circuit.
The system and method according to one embodiment of the present disclosure generally includes an initialization mode, a pre-lock scan mode, an iterative search mode and a termination mode for a receiver in any suitable communication system. In one embodiment, the communication system may be any suitable wireless communication system.
In the initialization mode, the initial value of the frequency estimate (fe) is set to the nominal value, i.e., a value obtained from the frequency tracking PLL during a previous successfully received message. Then, the initial search step size or initial frequency step size (fs) is set to a large initial value (fs0). Next, the nominal carrier frequency tracking PLL is disabled, but other nominal receiver functions continue to run. In
In the pre-lock scan mode 108, the downconverter frequency (f) is varied in a repeating sequence of frequencies separated by a relatively large initial frequency step size (fs0). The system dwells at each frequency for one symbol period, aligning dwell periods with actual symbols as detections occur. The system then repeats until the receiver locks onto a sufficiently reliable sequence of detected symbols. This occurs at lock point 118 and the receiver disables the automatic gain control on the input signal.
In iterative search mode 110, after each symbol detection, the system calculates the frequency centroid (fc) based on the 3-symbol history of downconverter frequency {f1,f2,f3} and received energy {e1,e2,e3}, as shown by the relationship exemplified by Equation 1 below.
f
c=(f1×e1+f2×e2+f3×e3)÷(e1+e2+e3) (Eqn. 1)
Then, based on direct phase measurements from the running detector/decoder, the system calculates the current phase drift per symbol (dp) and scales it using a factor (k) to obtain an estimate of the current frequency offset (fdp) as shown by the relationship exemplified in Equation 2 below.
f
dp
=k×dp (Eqn. 2)
The system then updates the frequency estimate (fe) using an adaptively weighted combination of (fc), (fdp), and the previous value of (fe) (designated as fe1) using the relationship exemplified by Equation 3 below.
f
e=(ac×fc+adp×fdp+ae1×fe1) (Eqn. 3)
After calculating (fe), weighting coefficients (ac, adp, ae1) take adaptive values reflecting the varying relative reliability of the frequency estimates (fc, fdp, fe1) with the scale preserving constraint as shown by the relationship exemplified by Equation 4 below.
a
c
+a
dp
+a
e1=1 (Eqn. 4)
If certain criteria have been met, the system then decreases the frequency step size (fs) depending upon a measure of convergence. For example, in one embodiment, the system may update the current frequency in a sequence that includes combinations of iteratively updated values of fe and fs. For example, the sequence may be: {fe1, fe1+fs1, fe2, fe2−fs2, fe3, fe3+fs3, fe4, fe4−fs4, . . . }.
As the step size is decreased, the system approaches the correct frequency. For example, the system repeats the above-described steps in the iterative mode until convergence or timeout as exemplified by convergence point 120. Convergence 120 occurs when the frequency step size (fs) is sufficiently small, or when symbols are being decoded with sufficient reliability. Accordingly, the step size is decreased until the correct frequency is finally realized.
At convergence or timeout 120, the system re-enables the automatic gain control and the nominal frequency tracking PLL. In a preferred embodiment of the disclosure, the system includes a receiver in a direct sequence spread spectrum communication network, detecting symbols using a matched filter.
In
According to one embodiment of the present disclosure, hardware complexity is limited by using the same single downconverter and matched filter that is used during the subsequent PLL-tracked header and payload decoding phase. The only addition to the nominal receiver is a fairly simple finite state machine used to execute an iterative frequency search for maximum energy and optimum symbol detection.
Accordingly, embodiments of the present disclosure use adaptive decreasing step size to determine a relatively precise optimum frequency over a wide frequency range in relatively few steps, e.g., requiring less than one third the time needed for an equivalent linear scan of the same range.
Step 202 includes setting the initial value of the frequency estimate (fe) to a nominal value. For example, the nominal value may be a value obtained from the frequency tracking PLL during a previous message that was successfully received. The initial frequency step size (fs) is set to a large initial value (fs0). The nominal carrier frequency tracking PLL is disabled but all other nominal receiver functions are run as normal.
Step 204 includes varying the downconverter frequency f in a repeating sequence of frequencies. For example, the repeating sequence of frequencies may be separated by a relatively large initial frequency step size (fs0). In one embodiment, method 200 remains or dwells at each frequency for one symbol period and aligns the dwell periods with the actual symbols as each detection occurs. Step 204 is generally repeated until the receiver locks onto a sufficiently reliable sequence of detected symbols. When this occurs, method 200 disables the automatic gain control (AGC) on the input signal.
Step 206a includes performing an iterative search, taking one step after each symbol detection. For example, step 206a includes calculating the frequency centroid based on a three-symbol history of the downconverter frequency and received energy. In one embodiment, for example, the frequency centroid may be realized using the relationship exemplified by Equation 1 described earlier herein.
Step 206a may also include calculating the current phase drift per symbol (dp) and scaling the current phase drift per symbol to obtain an estimate of the current frequency offset (fdp). In one embodiment, for example, the current frequency offset (fdp) may be realized using the relationship exemplified by Equation 2 described earlier herein.
Step 206b includes updating the frequency estimate (fe) using an adaptively weighted combination of fc, fdp, and the previous value of frequency estimate (fe) (designated as fe1). In one embodiment, for example, the frequency estimate (fe) may be updated using the relationship exemplified by Equations 3 and 4 described earlier herein.
Finally, step 208 may include decreasing the frequency step size (fs) and updating the current frequency in a sequence based on iteratively updated values of fs and fe. In one embodiment, for example, the sequence may be given by: {fe1, fe1+fs1, fe2, fe2−fs2, fe3, fe3+fs3, fe4, fe4−fs4, . . . }.
It should be understood that method 200 preferably performs step 208 until convergence or timeout. In one embodiment, convergence occurs when frequency step size (fs) is sufficiently small or when symbols are decoded with sufficient reliability. After convergence, in step 210, method 200 re-enables the automatic gain control (AGC) and the nominal frequency tracking PLL.
Accordingly, in one embodiment, method 300 rapidly narrows the search range to frequencies that are relatively near the correct value. Thus, the nominal receiver performs well while running simultaneously with any carrier acquisition search. Thus, method 300 provides rapid receiver lock and thus allows time and phase information from the detector to be used in carrier acquisition prior to PLL handoff.
It should also be understood that method 200 may be accomplished by a receiver having any suitable circuit or circuits configured to perform the steps of method 200. In one embodiment, the present disclosure provides a system and method for generally replacing conventional frequency sweeps. The system and method requires using an adaptive decreasing step size to determine a relatively precise optimum frequency over a wide frequency range. Accordingly, the present disclosure requires less than one third of the time needed for an equivalent conventional sweep of the same range.
It may be advantageous to set forth definitions of certain words and phrases used in this patent document. The term “couple” and its derivatives refer to any direct or indirect communication between two or more elements, whether or not those elements are in physical contact with one another. The terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation. The term “or” is inclusive, meaning and/or. The phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like.
While this disclosure has described certain embodiments and generally associated methods, alterations and permutations of these embodiments and methods will be apparent to those skilled in the art. Accordingly, the above description of example embodiments does not define or constrain this disclosure. Other changes, substitutions, and alterations are also possible without departing from the spirit and scope of this disclosure, as defined by the following claims.
