JACK DETECTION CIRCUIT

Abstract

A jack detection circuit includes a transition circuit and an AD converter. The transition circuit linearizes analog signals sent from a switching circuit. The AD converter converts the linearized analog signals to digital output signals thereby decreasing the complexity of signal recognition.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects, advantages, and novel features of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

FIG. 1 shows a circuit diagram of a conventional jack detection circuit.

FIG. 2 shows a circuit diagram of another conventional jack detection circuit.

FIG. 3 shows a block diagram of the jack detection circuit according to the first embodiment of the present invention.

FIG. 4 shows a circuit diagram of the jack detection circuit according to the first embodiment of the present invention.

FIG. 5 shows a circuit diagram of the jack detection circuit according to the second embodiment of the present invention.

FIG. 6 shows a circuit diagram of the jack detection circuit according to the third embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIG. 3, it illustrates a block diagram of a jack detection circuit according to the first embodiment of the present invention. The jack detection circuit is utilized for detecting a jack or key state of an analog device and/or its analog signal so as to generate a digital signal. The jack detection circuit includes a switching circuit 91, a transition circuit 10 and an analog-to-digital converter 20 (AD converter for abbreviation hereinafter). The transition circuit 10 transfers a first signal inputted from the switching circuit 91 to a second signal, wherein one embodiment of the first and the second signals includes an analog current signal. The AD converter 20 converts and outputs the second signal to a digital output signal.

Referring to FIG. 4, it depicts a circuit diagram of the jack detection circuit in accordance with the first embodiment of the present invention including the switching circuit 91, the transition circuit 10, the AD converter 20 and a resistor R₅. The resistor R₅ has a first end and a second end, wherein the first end is coupled to a second signal output terminal of the transition circuit 10, and the second end is coupled to a reference voltage, e.g. a ground end. In this embodiment, the switching circuit 91 has four resistor units and each of the resistors has one of the four switches SW₁, SW₂, SW₃ and SW₄ and a corresponding resistance element, e.g. resistors R₁, R₂, R₃ and R₄. The switches SW₁, SW₂, SW₃ and SW₄ can be controlled by an analog device so as to be in an ON state or in an OFF state. For example, if the analog device is a keyboard, each key on the keyboard corresponds to one switch or a group of switches. When a user presses a key on the keyboard, its corresponding switch or switches will be conducted (turned on). In another example, if an analog device is plugged to the jack detection circuit shown in FIG. 3, the switches can be impressed to conduct by a plugging force from a user. In this embodiment, assume R₁=R ohm, R₂=2R ohm, R₃=4R ohm and R₄=8R ohm. In addition, depending on different applications, the number of resistor units of the switching circuit 91 could be four as well as any other number.

Referring to FIG. 4 again, the transition circuit 10 according to the first embodiment of the present invention includes a first reference voltage generator 11 and a first current mirror 12. The first reference voltage generator 11 has an operational amplifier 111 and a first transistor 112. The positive input terminal of the operational amplifier 111 receives a first reference voltage V_ref, its negative input terminal is connected to the source of the first transistor 112 and coupled to the switching circuit 91 and its output terminal is coupled to the gate of the first transistor 112. If the operational amplifier 111 is an ideal amplifier, the voltage on the negative input terminal V_ref′ is substantially identical to the first reference voltage V_ref on the positive input terminal. Therefore, a corresponding current I_in3 can be determined by the voltage V_ref′ divided by the equivalent resistance of the switching circuit 91, and their relationships are shown in Table 1.

The first current mirror 12 includes a second transistor 121 and a third transistor 122 having their gates connected with each other. If the ratio aspect of the transistor 121 is identical to that of the transistor 122, a current aI_in3 proportional to the current I_in3 can be formed. Because the operation and implementation of a current mirror are well known by the person skilled in the art, their detailed descriptions will not be described herein.

TABLE 1
						digital
						output
SW1	SW2	SW3	SW4	Iin3	Vin3	signal
Off	Off	Off	Off	0	0	0000
Off	Off	Off	On	Vref/8R	aIin3 × R5 = X	0001
Off	Off	On	Off	Vref/4R	aIin3 × R5 = 2X	0010
Off	Off	On	On	(Vref/8R + Vref/4R)	aIin3 × R5 = 3X	0011
Off	On	Off	Off	Vref/2R	aIin3 × R5 = 4X	0100
Off	On	Off	On	(Vref/8R + Vref/2R)	aIin3 × R5 = 5X	0101
Off	On	On	Off	(Vref/4R + Vref/2R)	aIin3 × R5 = 6X	0110
Off	On	On	On	(Vref/8R + Vref/4R + Vref/2R)	aIin3 × R5 = 7X	0111
On	Off	Off	Off	Vref/R	aIin3 × R5 = 8X	1000
On	Off	Off	On	(Vref/8R + Vref/R)	aIin3 × R5 = 9X	1001
On	Off	On	Off	(Vref/4R + Vref/R)	aIin3 × R5 = 10X	1010
On	Off	On	On	(Vref/8R + Vref/4R + Vref/R)	aIin3 × R5 = 11X	1011
On	On	Off	Off	(Vref/2R + Vref/R)	aIin3 × R5 = 12X	1100
On	On	Off	On	(Vref/8R + Vref/2R + Vref/R)	aIin3 × R5 = 13X	1101
On	On	On	Off	(Vref/4R + Vref/2R + Vref/R)	aIin3 × R5 = 14X	1110
On	On	On	On	(Vref/8R + Vref/4R + Vref/2R + Vref/	aIin3 × R5 = 15X	1111
				R)
wherein X = (aVref × R5)/8R

Referring to FIG. 4 again, an input end of the AD converter 20, according to the first embodiment of the present invention, is connected between the first current mirror 12 and the first end of the resistor R₅. The AD converter 20 is a voltage AD converter and its input voltage V_in3 equals a multiplication of the current aI_in3 and the resistor R₅, i.e. V_in3=R₅×aI_in3 as shown in Table 1, and hence the input voltage V_in3 has linear characteristics. After the input voltage V_in3 is converted by the AD converter 20, a corresponding digital output signal will be outputted from the output bus N. The relationships between the conducting states of the switching circuit 91, the input voltage V_in3 of the AD converter 20 and the digital output signals are also shown in Table 1. In this embodiment, since the switching circuit 91 has four switches, the outputted digital signals are four-bit digital signals.

Referring to FIG. 5, it illustrates a jack detection circuit according to the second embodiment of the present invention. The jack detection circuit also includes the switching circuit 91, the AD converter 20 and the resistor R₅, and the jack detection circuit also has a transition circuit 30 which has a reference voltage generator 31 and a current mirror 32. This embodiment differs from the first embodiment in the types of the transistors, i.e. the transistors in the transition circuit 30 of the second embodiment are P-type transistors while the transistors in the transition circuit 10 of the first embodiment are N-type transistors. A negative input terminal of the operational amplifier 311 receives the first reference voltage V_ref, its positive input terminal is connected to the source of the transistor 321 and coupled to the switching circuit 91, and its output terminal is connected to the gate of the transistor 321. In this manner, the transition circuit 30 can also transfer a first signal I_in4 to a second signal aI_in4 which varies linearly in accordance with the conducting states of the switching circuit 91. Therefore, the AD converter 20 receives an input voltage V_in4=R₅×aIin₄ and can have linearly varied interval of comparison voltage.

Referring to FIG. 6, it shows a jack detection circuit according to the third embodiment of the present invention. The jack detection circuit also includes the transition circuit 10, the resistor R₅ and the switching circuit 91. The differences herein with respect to the first embodiment are that the third embodiment further includes a comparison current circuit 40 and the type of the AD converter 50 is different. The transition circuit 10 also transfers a first signal I_in5 to a second signal aI_in5, as described above. The comparison current circuit 40 comprises a second reference voltage generator 41 and a second current mirror 42. The second reference voltage generator 41 has an operational amplifier 411 and a transistor 412. A positive input terminal of the operational amplifier 411 receives a second reference voltage V_ref″ (in this embodiment the second reference voltage V_ref″ equals the first reference voltage V_ref), its output terminal is coupled to the gate of the transistor 412, and its negative input terminal is connected to the source of the transistor 412 and coupled to a first end of the resistor R₅. The second end of the resistor R₅ is coupled to a reference voltage, e.g. a ground end, so as to form a reference current I_ref=V_ref″/R₅ flowing through the transistor 412. In this embodiment, the second current mirror 42 maps the reference current I_ref to a comparison current I_c which is inputted, together with the second signal aI_in5 of the transition circuit 10, into the AD converter 50 to be compared, and finally a digital output signal will be outputted from the output bus N. The AD converter 50 in this embodiment is a current AD converter, which is utilized for comparing the second signal aI_in5 outputted from the transition circuit 10 with the comparison current I_c outputted from the comparison current circuit 40, and the second signal aI_in5 varies linearly in accordance with conducting states of the switching circuit 91.

In addition, embodiments shown in FIG. 4, FIG. 5 and FIG. 6 can be varied and implemented by other circuit structure, for example but not limited to, interchanging the V_CC and the ground shown in all figures.

Although the invention has been explained in relation to its preferred embodiment, it is not used to limit the invention. It is to be understood that many other possible modifications and variations can be made by those skilled in the art without departing from the spirit and scope of the invention as hereinafter claimed.

Claims

1. A jack detection circuit for detecting a jack or key state of an analog device and/or an analog signal outputted from the analog device so as to generate a digital signal, the jack detection circuit comprising: a switching circuit for forming an equivalent resistance in accordance with the jack or key state of the analog device and/or the analog signal outputted from the analog device; anda transition circuit, coupled to the switching circuit, for generating a reference current in accordance with a first reference voltage and the equivalent resistance; andan AD converter, coupled to the transition circuit, for generating the digital signal in accordance with the reference current.

2. The jack detection circuit as claimed in claim 1, wherein the equivalent resistance varies in accordance with the variation of the jack or key state of the analog device and/or its analog signal.

3. The jack detection circuit as claimed in claim 2, wherein the switching circuit further comprises a plurality of conducting paths each comprising a switch and a resistor unit connected in series, and the states of the switches are determined by the jack or key state of the analog device and/or its analog signal.

4. The jack detection circuit as claimed in claim 3, wherein the conducting paths are coupled in parallel.

5. The jack detection circuit as claimed in claim 2, further comprising: a reference resistor, coupled to the transition circuit and the AD converter, for generating a voltage signal in accordance with the reference current;wherein the AD converter converts the voltage signal to the digital signal.

6. The jack detection circuit as claimed in claim 5, wherein the voltage signal varies linearly corresponding to the variation of the equivalent resistance.

7. The jack detection circuit as claimed in claim 2, wherein the transition circuit comprises: a first reference voltage generator, coupled to the switching circuit, for generating the first reference voltage and correspondingly generating an initial reference current in accordance with the equivalent resistance and the first reference voltage; anda current mirror, coupled to the first reference voltage generator and the AD converter, for providing the reference current in accordance with the initial reference current.

8. The jack detection circuit as claimed in claim 7, wherein the first reference voltage generator further comprises: a first amplifier, having a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal is coupled to an input voltage and the negative input terminal is coupled to the switching circuit; anda first transistor, coupled to the output terminal, the negative input terminal, the switching circuit and the current mirror.

9. The jack detection circuit as claimed in claim 2, further comprising: a comparison current generator for generating a comparison current in accordance with a second reference voltage and a reference resistor;wherein the AD converter generates the digital signal in accordance with the comparison current and the reference current.

10. The jack detection circuit as claimed in claim 9, wherein the AD converter compares the comparison current and the reference current so as to generate the digital signal.

11. The jack detection circuit as claimed in claim 9, wherein the comparison current generator comprises: a second reference voltage generator, coupled to the reference resistor, for generating the second reference voltage and correspondingly generating an initial comparison current in accordance with the reference resistor and the second reference voltage; andAD converter, for providing the comparison current in accordance with the initial comparison current.

12. The jack detection circuit as claimed in claim 11, wherein the second reference voltage generator comprises: a second amplifier having a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal is coupled to an input voltage and the negative input terminal is coupled to the reference resistor; anda second transistor, coupled to the output terminal, the negative input terminal, the reference resistor and the current mirror.

13. The jack detection circuit as claimed in claim 1, wherein the reference current varies linearly corresponding to the variation of the equivalent resistance.