The invention relates to imager devices generally and particularly to improving the control and operation of an imager pixel.
An imager, for example, a CMOS imager includes a focal plane array of pixel cells; each cell includes a photosensor, for example, a photogate, photoconductor or a photodiode overlying a substrate for producing a photo-generated charge in a doped region of the substrate. A pixel uses CMOS transistors, which are a form of metal oxide semiconductor field effect transistor (MOSFET). A readout circuit is provided for each pixel cell and typically includes at least a source follower transistor and a row select transistor for coupling the source follower transistor to a column output line. The pixel cell also typically has a charge storage node, for example, a floating diffusion region which is, in turn, connected to the gate of the source follower transistor. Charge generated by the photosensor is stored at the storage node. In some arrangements, the imager may also include a transistor for transferring charge from the photosensor to the storage node. The imager also typically includes a transistor to reset the storage node before it receives photo-generated charges.
The CMOS imager is operated by control circuit 250, which controls address decoders 220, 270 for selecting the appropriate row and column lines for pixel readout, and row and column driver circuitry 210, 260 that apply driving voltage to the drive transistors of the selected row and column lines. The pixel output signals typically include a pixel reset signal Vrst taken off of the floating diffusion region when it is reset by reset transistor and a pixel image signal Vsig, which is taken off the floating diffusion region after photo-generated charges are transferred to it. The Vrst and Vsig signals are read by a sample and hold circuit 265 and are subtracted by a differential amplifier 267, to produce a signal Vrst−Vsig for each pixel that represents the amount of light impinging on the pixels. This difference signal is digitized by an analog-to-digital converter 275. The digitized pixel signals are fed to an image processor 280 to form a digital image. The digitizing and image processing can be located on or off the imager chip. In some arrangements the differential signal Vrst−Vsig is amplified as a differential signal and directly digitized by a differential analog to digital converter.
In a CMOS imager pixel cell, for example, a five transistor (5T) pixel cell 100 depicted in
When anti-blooming transistor 112 is turned on by an anti-blooming control signal AB to drain excess charge from the photodiode 102 during the integration period, a high charge barrier AB created by the anti-blooming transistor 112 (
Typically, a charge transfer CMOS transistor 104 is utilized in a pixel cell to create a charge transfer barrier between the floating diffusion region 106 and a CMOS anti-blooming transistor is utilized to create a charge barrier between the photodiode 102 and a discharging point. Controlling these barriers when operating the pixel cells in a high dynamic mode (HiDy), is achieved by applying a variable potential to gates of the anti-blooming transistor 112 or transfer transistor 104. Controlling the anti-blooming transistor 112 and transfer transistor 104 in such a manner controls the maximum charge accumulated in the pixel cells at any given time during charge integration.
However, there is a problem in using CMOS transistors as barriers in imager pixel cells. CMOS transistors have a high deviation in threshold voltage Vth from wafer to wafer, and often from transistor to transistor. The deviation is created to a large extent by the gate oxide layer. For example, the gate oxide layer can assimilate floating charges that make it difficult to precisely control the transistors. This deviation leads to an uncertainty in the amount of charge stored from pixel cell to pixel cell since the threshold voltage Vth of each transistor could vary. The variance of charge storage from pixel cell to pixel cell in an imager array leads to fixed pattern noise (FPN) resulting in diminished image quality because non-uniformity of barrier heights between pixels.
Accordingly, there is a need and desire for an imager with improved anti-blooming and/or charge transfer control.
Various embodiments of the invention provide a new pixel design for an imager in which a junction field effect transistor (JFET) transistor is provided in an anti-blooming path during charge integration. Since a JFET transistor does not have an oxide layer below its gate, it has a better defined threshold voltage (Vth) and thus it provides improved charge control for the pixel. Utilizing a JFET transistor as an anti-blooming transistor thus reduces pixel-to-pixel charge uncertainty. The reduction of fixed pattern noise results in improved image quality.
Some embodiments employ a JFET transistor in the charge transfer path of a pixel.
Still other embodiments employ a JFET transistor both in the anti-blooming path and in the charge transfer path of a pixel.
These and other features and advantages of the invention will be better understood from the following detailed description, which is provided in connection with the accompanying drawings, in which:
In the following detailed description, reference is made to the accompanying drawings, which are a part of the specification, and in which is shown by way of illustration various embodiments whereby the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to make and use the invention. It is to be understood that other embodiments may be utilized, and that structural, logical, and electrical changes, as well as changes in the materials used, may be made without departing from the spirit and scope of the present invention. Additionally, certain processing steps are described and a particular order of processing steps is disclosed; however, the sequence of steps is not limited to that set forth herein and may be changed as is known in the art, with the exception of steps or acts necessarily occurring in a certain order.
The terms “wafer” and “substrate” are to be understood as interchangeable and as including silicon, silicon-on-insulator (SOI) or silicon-on-sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a “wafer” or “substrate” in the following description, previous process steps may have been utilized to form regions, junctions or material layers in or on the base semiconductor structure or foundation. In addition, the semiconductor need not be silicon-based, but could be based on silicon-germanium, germanium, gallium arsenide, or other known semiconductor materials.
The term “pixel” refers to a photo-element unit cell containing a photo-conversion device or photosensor, for example, a photogate, photoconductor or a photodiode and transistors for processing an electrical signal from electromagnetic radiation sensed by the photo-conversion device. The embodiments of pixels discussed herein are illustrated and described as employing five transistor (5T) pixel circuits for the sake of example only. It should be understood that the invention may be used with other pixel arrangements having more or less than five transistors.
Although the invention is described herein with reference to the architecture and fabrication of one pixel cell, it should be understood that this is representative of a plurality of pixels in an array of an imager device such as array 200 of imager device 908 (
Control of anti-blooming transistor 312 is accomplished by applying a control voltage to the transistor gate. Unlike CMOS transistors, the voltage threshold of the anti-blooming transistor 312 is determined by the doping levels in the channel and gate areas of the transistor 312. The gate of anti-blooming transistor 312 represents a p-doped region, for example, electrically isolated from a p-region around photodiode 102. Consequently, the gate potential of anti-blooming transistor 312 may be changed independently from the p-region around photodiode 102 and the gate threshold voltage is unaffected by changes in an underlying oxide layer.
The processor-based system 900, for example a camera system, generally comprises a central processing unit (CPU) 902, such as a microprocessor, that communicates with an input/output (I/O) device 906 over a bus 904. Imaging device 908 also communicates with the CPU 902 over bus 904. The processor-based system 900 also includes random access memory (RAM) 910, and can include removable memory 915, such as flash memory, which also communicate with CPU 902 over the bus 904. Imaging device 908 may be combined with a processor, such as a CPU, digital signal processor, or microprocessor, with or without memory storage on a single integrated circuit or on a different chip than the processor.
Various embodiments of the invention have been illustrated using a photodiode as the charge conversion device, and in the environment of a five transistor pixel. However, it should be appreciated that the invention is not so limited and can be used in any pixel architecture employing one or both of an anti-blooming transistor and charge transfer transistor, and any other transistor where there may be pixel-to-pixel or wafer-to-wafer variations in pixel signal output due to variations in gate trapped charges when a CMOS transistor is employed. Also, other types of photosensors may be used to generate image charge. Accordingly, it is not intended that the present invention be strictly limited to the above-described and illustrated embodiment. Any modifications, though presently unforeseeable, of the present invention that comes within the spirit and scope of the following claims should be considered part of the present invention.