Claims
- 1. A method for selectively forming an antifuse in an integrated circuit comprising the steps of:
forming a first conducting layer on an insulator, which is supported by a semiconductor substrate; forming a bottom conductor layer on the first conducting layer; forming a programming layer on the bottom conductor layer; and forming a top conductor layer on the programming layer.
- 2. The method of claim 1, and further comprising the steps of forming a contact to the first conducting layer and forming a contact to the top conductor layer.
- 3. The method of claim 1, and further comprising the step of forming a refractory metal silicide layer on the first conducting layer, prior to forming the bottom conductor layer.
- 4. The method of claim 3, and further comprising the steps of forming a contact to the refractory metal silicide layer and forming a contact to the top conductor layer.
- 5. The method of claim 1, and further comprising the step of applying a programming voltage to significantly reduce the electrical resistance between the top and bottom conductor layers.
- 6. The method of claim 1, wherein the step of forming the first conducting layer simultaneously forms transistor gates in selected areas of the integrated circuit.
- 7. The method of claim 1, wherein the bottom and top conductor layers comprise a material selected from the group comprising polysilicon and metals.
- 8. The method of claim 1, wherein the programming layer is selected from the group comprising: amorphous silicon, polysilicon, silicon dioxide, silicon nitride, tantalum oxide, and dielectric materials.
- 9. An antifuse structure, formed in an integrated circuit, comprising:
a top conductor layer; a bottom conductor layer; a programming layer positioned between the top and bottom conductor layers; a first conducting layer on the bottom conductor layer; and an insulator disposed between the first conducting layer and a semiconductor substrate.
- 10. The antifuse structure of claim 9, wherein the first conducting layer comprises polysilicon and is used elsewhere in the integrated circuit as a transistor gate layer.
- 11. The antifuse structure of claim 9, wherein the top and bottom conductor layers comprise a material selected from the group comprising polysilicon and metals.
- 12. The antifuse structure of claim 9, and further comprising a refractory metal silicide layer coupled between the first conducting layer and the bottom conductor layer.
- 13. The antifuse structure of claim 12, and further comprising a contact to the refractory metal silicide layer and a contact to the top conductor layer.
- 14. The antifuse structure of claim 9, and further comprising a contact to the first conducting layer and a contact to the top conductor layer.
- 15. The antifuse structure of claim 9, wherein the programming layer is selected from the group comprising: amorphous silicon, polysilicon, silicon dioxide, silicon nitride, tantalum oxide, and dielectrics.
- 16. A method for selectively forming an antifuse in an integrated circuit comprising the steps of:
forming a first conducting layer on an insulator, which is supported by a semiconductor substrate; forming a refractory metal silicide layer on the first conducting layer; forming a bottom conductor layer on the refractory metal silicide layer; forming a programming layer on the bottom conductor layer; and forming a top conductor layer on the programming layer.
- 17. An antifuse structure, formed in an integrated circuit, comprising:
a top conductor layer; a bottom conductor layer; a programming layer, positioned between the top and bottom conductor layers; a refractory metal silicide layer, on the bottom conductor layer; a first conducting layer, on the refractory metal silicide layer; and an insulator, disposed between the first conducting layer and a semiconductor substrate.
- 18. A method for selectively forming an antifuse in an integrated circuit comprising the steps of:
forming a bottom conductor layer on an insulator, which is supported by a semiconductor substrate; forming a programming layer on the bottom conductor layer; and forming a top conductor layer on the programming layer.
- 19. The method of claim 18, and further comprising the steps of forming a contact to the bottom conductor layer and forming a contact to the top conductor layer.
- 20. The method of claim 18, wherein the bottom conductor layer comprises a refractory metal silicide layer on an underlying conducting layer.
- 21. The method of claim 20, and further comprising the steps of forming a contact to the refractory metal silicide layer and forming a contact to the top conductor layer.
- 22. The method of claim 18, and further comprising the step of applying a programming voltage to significantly reduce the electrical resistance between the top and bottom conductor layers.
- 23. The method of claim 18, wherein the step of forming the bottom conductor layer simultaneously forms transistor gates in selected areas of the integrated circuit.
- 24. The method of claim 18, wherein the bottom and top conductor layers comprise a material selected from the group comprising polysilicon and metals.
- 25. The method of claim 18, wherein the programming layer is selected from the group comprising: amorphous silicon, polysilicon, silicon dioxide, silicon nitride, tantalum oxide, and dielectric materials.
- 26. An antifuse structure, formed in an integrated circuit, comprising:
a top conductor layer; a bottom conductor layer; a programming layer, positioned between the top and bottom conductor layers; and an insulator, positioned between the bottom conductor layer and a semiconductor substrate.
- 27. The antifuse structure of claim 26, wherein the bottom conductor layer comprises polysilicon and is used elsewhere in the integrated circuit as a transistor gate layer.
- 28. The antifuse structure of claim 26, wherein the top and bottom conductor layers comprise a material selected from the group comprising polysilicon and metals.
- 29. The antifuse structure of claim 26, wherein the bottom conductor layer comprises a refractory metal silicide layer on an underlying conducting layer.
- 30. The antifuse structure of claim 29, and further comprising a contact to the refractory metal silicide layer and a contact to the top conductor layer.
- 31. The antifuse structure of claim 26, and further comprising a contact to the first conducting layer and a contact to the top conductor layer.
- 32. The antifuse structure of claim 26, wherein the programming layer is selected from the group comprising: amorphous silicon, polysilicon, silicon dioxide, silicon nitride, tantalum oxide, and dielectrics.
- 33. An antifuse, comprising:
a substrate; a field oxide on the substrate; a conductive first etch stop on the field oxide; a second etch stop on the field oxide, the second etch stop being separate from the first etch stop; a first contact connected to the first conductive island; a second contact connected to the second conductive island; a first conductive layer on the first etch stop; a programming layer on the first conductive layer and connected to both the first contact and the second contact; and a second conductive layer on the programming layer and connected to the first contact.
- 34. The antifuse of claim 33, wherein the first conductive layer is free of contact with the first contact and the second contact.
- 35. The antifuse of claim 33, wherein the first contact is free of contact with the first conductive layer and the second conductive layer.
- 36. The antifuse of claim 33, wherein the first etch stop includes a polysilicon layer and a silicide layer.
- 37. The antifuse of claim 36, wherein the polysilicon layer is used elsewhere on the substrate to form an integrated circuit component.
- 38. The antifuse of claim 33, wherein the second etch stop includes a polysilicon layer and a silicide layer.
- 39. The antifuse of claim 33, wherein the first etch stop consists of polysilicon and the polysilicon is formed simultaneously with polysilicon used elsewhere on the substrate to form an integrated circuit component.
- 40. The antifuse of claim 33, wherein the first etch stop halts etching of a hole in which the first contact is formed.
- 41. The antifuse of claim 40, wherein the second etch stop halts etching of a hole in which the second contact is formed.
- 42. An antifuse, comprising:
a substrate; a field oxide on the substrate; a conductive first etch stop on the field oxide; a conductive second etch stop on the field oxide, the second etch stop being separate from the first etch stop; a first contact connected to the first conductive island; a second contact connected to the second conductive island; a first conductive layer on the first etch stop; a programming layer on the first conductive layer and connected to both the first contact and the second contact; and a second conductive layer on the programming layer and connected to the first contact.
- 43. An antifuse having a blown state and an unblown state, comprising:
a substrate; a field oxide on the substrate; a conductive first etch stop on the field oxide; a second etch stop on the field oxide, the second etch stop being separate from the first etch stop; a first contact connected to the first etch stop; a second contact connected to the second etch stop; a first conductive layer on the first etch stop; a programming layer on the first conductive layer and connected to both the first contact and the second contact; a second conductive layer on the programming layer and connected to the first contact; wherein a first current path consists of the second contact, the second conductive layer, capacitance of the programmable layer, the first conductive layer, the first etch stop, and the first contact in the unblown state; and wherein a second current path consists of the first contact, the programmable layer, and the second contact in the blown state.
- 44. The antifuse of claim 43, wherein the first conductive layer is free of contact with the first contact and the second contact.
- 45. The antifuse of claim 43, wherein the first contact is free of contact with the first conductive layer and the second conductive layer.
- 46. The antifuse of claim 43, wherein the first etch stop includes a polysilicon layer and a silicide layer.
- 47. The antifuse of claim 46, wherein the polysilicon layer is used elsewhere on the substrate to form an integrated circuit component.
- 48. The antifuse of claim 43, wherein the second etch stop includes a polysilicon layer and a silicide layer.
- 49. The antifuse of claim 43, wherein the first etch stop consists of polysilicon and the polysilicon is formed simultaneously with polysilicon used elsewhere on the substrate to form an integrated circuit component.
- 50. The antifuse of claim 43, wherein the first etch stop halts etching of a hole in which the first contact is formed.
- 51. The antifuse of claim 50, wherein the second etch stop halts etching of a hole in which the second contact is formed.
- 52. An antifuse having a blown state and an unblown state, comprising:
a substrate; a field oxide on the substrate; a conductive first etch stop on the field oxide; a conductive second etch stop on the field oxide, the second etch stop being separate from the first etch stop; a first contact connected to the first etch stop; a second contact connected to the second etch stop; a first conductive layer on the first etch stop; a programming layer on the first conductive layer and connected to both the first contact and the second contact; a second conductive layer on the programming layer and connected to the first contact; wherein a first current path consists of the second contact, the second conductive layer, capacitance of the programmable layer, the first conductive layer, the first etch stop, and the first contact in the unblown state; and wherein a second current path consists of the first contact, the programmable layer, and the second contact in the blown state.
- 53. An antifuse, consisting of:
a substrate; a field oxide on the substrate; a conductive first etch stop on the field oxide; a second etch stop on the field oxide, the second etch stop being separate from the first etch stop; a first contact connected to the first etch stop; a second contact connected to the second etch stop; a first conductive layer on the first etch stop; a programming layer on the first conductive layer and connected to both the first contact and the second contact; and a second conductive layer on the programming layer and connected to the first contact.
- 54. The antifuse of claim 53, wherein the first conductive layer is free of contact with the first contact and the second contact.
- 55. The antifuse of claim 53, wherein the first contact is free of contact with the first conductive layer and the second conductive layer.
- 56. The antifuse of claim 53, wherein the first etch stop includes a polysilicon layer and a silicide layer.
- 57. The antifuse of claim 56, wherein the polysilicon layer is used elsewhere on the substrate to form an integrated circuit component.
- 58. The antifuse of claim 53, wherein the second etch stop includes a polysilicon layer and a silicide layer.
- 59. The antifuse of claim 53, wherein the first etch stop consists of polysilicon and the polysilicon is formed simultaneously with polysilicon used elsewhere on the substrate to form an integrated circuit component.
- 60. The antifuse of claim 53, wherein an unblown current path consists of the second contact, the second conductive layer, capacitance of the programmable layer, the first conductive layer, the first etch stop, and the first contact.
- 61. The antifuse of claim 136, wherein a blown current path consists of the first contact, the programmable layer, and the second contact.
- 62. The antifuse of claim 53, wherein the first etch stop halts etching of a hole in which the first contact is formed.
- 63. The antifuse of claim 62, wherein the second etch stop halts etching of a hole in which the second contact is formed.
- 64. An antifuse, consisting of:
a substrate; a field oxide on the substrate; a conductive first etch stop on the field oxide; a conductive second etch stop on the field oxide, the second etch stop being separate from the first etch stop; a first contact connected to the first etch stop; a second contact connected to the second etch stop; a first conductive layer on the first etch stop; a programming layer on the first conductive layer and connected to both the first contact and the second contact; and a second conductive layer on the programming layer and connected to the first contact.
- 65. An antifuse, comprising:
a substrate having a surface; a field oxide on the surface; a conductive first etch stop on the field oxide; a second etch stop on the field oxide, the second etch stop being separate from the first etch stop; a first contact connected to the first etch stop, the first contact extending outwardly relative to the surface; a second contact connected to the second etch stop, the second contact extending outwardly relative to the surface; a first conductive layer on the first etch stop; a programming layer on the first conductive layer and connected to both the first contact and the second contact; and a second conductive layer on the programming layer and connected to the first contact.
- 66. The antifuse of claim 65, wherein the first conductive layer is free of contact with the first contact and the second contact.
- 67. The antifuse of claim 65, wherein the first contact is free of contact with the first conductive layer and the second conductive layer.
- 68. The antifuse of claim 65, wherein the first conductive island includes a polysilicon layer and a silicide layer.
- 69. The antifuse of claim 65, wherein the polysilicon layer is used elsewhere on the substrate to form an integrated circuit component.
- 70. The antifuse of claim 69, wherein the second etch stop includes a polysilicon layer and a silicide layer.
- 71. The antifuse of claim 69, wherein the first etch stop consists of polysilicon and the polysilicon is formed simultaneously with polysilicon used elsewhere on the substrate to form an integrated circuit component.
- 72. The antifuse of claim 69, wherein an unblown current path consists of the second contact, the second conductive layer, capacitance of the programmable layer, the first conductive layer, the first etch stop, and the first contact.
- 73. The antifuse of claim 70, wherein a blown current path consists of the first contact, the programmable layer, and the second contact.
- 74. The antifuse of claim 65, wherein the first etch stop halts etching of a hole in which the first contact is formed.
- 75. The antifuse of claim 74, wherein the second etch stop halts etching of a hole in which the second contact is formed.
- 76. An antifuse, comprising:
a substrate having a surface; a field oxide on the surface; a conductive first etch stop on the field oxide; a conductive second etch stop on the field oxide, the second etch stop being separate from the first etch stop; a first contact connected to the first etch stop, the first contact extending outwardly relative to the surface; a second contact connected to the second etch stop, the second contact extending outwardly relative to the surface; a first conductive layer on the first etch stop; a programming layer on the first conductive layer and connected to both the first contact and the second contact; and a second conductive layer on the programming layer and connected to the first contact.
- 77. An antifuse, comprising:
a substrate; a field oxide on the substrate; a conductive first etch stop on the field oxide; a second etch stop on the field oxide, the second etch stop being separate from the first etch stop; a first contact connected to the first etch stop; a second contact connected to the second etch stop; a first conductive layer on the first etch stop; a programming layer on the first conductive layer and connected to both the first contact and the second contact; a second conductive layer on the programming layer and connected to the first contact; wherein the first etch stop is in electrically-conductive contact with only the first conductive layer and the first contact.
- 78. The antifuse of claim 77, wherein an insulative material and the field oxide electrically insulate the first etch stop.
- 79. The antifuse of claim 77, wherein an insulative material and the field oxide electrically insulate the second etch stop.
- 80. The antifuse of claim 77, wherein an unblown current path consists of the second contact, the second conductive layer, capacitance of the programmable layer, the first conductive layer, the first etch stop, and the first contact.
- 81. The antifuse of claim 77, wherein a blown current path consists of the first contact, the programmable layer, and the second contact.
- 82. The antifuse of claim 77, wherein the first etch stop halts etching of a hole in which the first contact is formed.
- 83. The antifuse of claim 82, wherein the second etch stop halts etching of a hole in which the second contact is formed.
- 84. An antifuse, comprising:
a substrate; a field oxide on the substrate; a conductive first etch stop on the field oxide; a conductive second etch stop on the field oxide, the second etch stop being separate from the first etch stop; a first contact connected to the first etch stop; a second contact connected to the second etch stop; a first conductive layer on the first etch stop; a programming layer on the first conductive layer and connected to both the first contact and the second contact; a second conductive layer on the programming layer and connected to the first contact; wherein the first etch stop is in electrically-conductive contact with only the first conductive layer and the first contact.
- 85. An antifuse, comprising:
a substrate; a field oxide on the substrate; a conductive first etch stop directly on the field oxide; a second etch stop directly on the field oxide, the second etch stop being separate from the first etch stop; a first contact connected to the first etch stop; a second contact connected to the second etch stop; a first conductive layer contacting the first etch stop; a programming layer contacting the first conductive layer and connected to both the first contact and the second contact; and a second conductive layer contacting the programming layer and connected to the first contact.
- 86. The antifuse of claim 85, wherein an unblown current path consists of the second contact, the second conductive layer, capacitance of the programmable layer, the first conductive layer, the first etch stop, and the first contact.
- 87. The antifuse of claim 85, wherein a blown current path consists of the first contact, the programmable layer, and the second contact.
- 88. The antifuse of claim 85, wherein the first etch stop halts etching of a hole in which the first contact is formed.
- 89. The antifuse of claim 88, wherein the second etch stop halts etching of a hole in which the second contact is formed.
- 90. An antifuse, comprising:
a substrate; a field oxide on the substrate; a conductive first etch stop directly on the field oxide; a conductive second etch stop directly on the field oxide, the second etch stop being separate from the first etch stop; a first contact connected to the first etch stop; a second contact connected to the second etch stop; a first conductive layer contacting the first etch stop; a programming layer contacting the first conductive layer and connected to both the first contact and the second contact; and a second conductive layer contacting the programming layer and connected to the first contact.
RRELATED APPLICATIONS
[0001] This application is a continuation of U.S. Ser. No. 09/131,130; which is a divisional of U.S. Ser. No. 08/702,951, now U.S. Pat. No. 6,069,064.
Divisions (1)
|
Number |
Date |
Country |
Parent |
08702951 |
Aug 1996 |
US |
Child |
09131030 |
Aug 1998 |
US |
Continuations (1)
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Number |
Date |
Country |
Parent |
09131030 |
Aug 1998 |
US |
Child |
09990022 |
Nov 2001 |
US |