Claims
- 1. A controller circuit for switching between a user mode and a kernel mode in a processor comprising;
a processor; a program counter electrically connected to the processor for monitoring program fetch addresses; a kernel program fetch supervisor circuit having a predetermined address value stored within, electrically connected to the program counter for comparing the address in the program counter to the predetermined address value stored within; a program memory electrically connected to the program counter; a flip-flop circuit electrically connected to the kernel program fetch supervisor circuit for switching between setting a user mode bit and a kernel mode bit; a kernel data fetch supervisor circuit electrically connected to the processor for comparing a data fetch address to a predetermined memory address range; a data memory electrically connected to a processor data interface for storing data; a first AND circuit coupled to the flip-flop and the kernel data fetch supervisor circuit for activating and deactivating a violation reset; and a second AND circuit coupled to the first AND circuit and the kernel program fetch supervisor circuit for activating and deactivating the violation reset bit.
- 2. A method of monitoring and controlling program fetch addresses and data fetch addresses from a processor to control access to a protected memory comprising the steps of:
fetching a program opcode; reading a program opcode address; determining whether the program opcode address is fetched from one of a protected program memory address and an unprotected program memory address; resetting the processor when the program opcode is fetched from the protected program memory address; fetching a data operand when the program opcode address is fetched from the unprotected program memory address; fetching a data operand and reading the data operand address; determining whether the data operand address is fetched from one of a protected data memory address and an unprotected data memory address; resetting the processor when the data operand is fetched from the protected data memory address; calling a starting address of the protected program memory when the data operand address is fetched from the unprotected data memory; fetching a second program opcode; reading the second program opcode address; determining whether the second program opcode address is fetched from one of a protected program memory address and an unprotected program memory address; fetching a third program opcode when the second program opcode address is fetched from the unprotected memory address; and fetching a second data operand when the second program opcode address is fetched from the protected memory address.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is based on Provisional Patent Application Serial Nos. 60/059,082 and 60/059,843, each of which was filed on Sep. 16, 1997, and relates to U.S. patent application entitled “Cryptographic Co-Processor” filed concurrently herewith, the disclosures of which are incorporated herein by reference.
Provisional Applications (2)
|
Number |
Date |
Country |
|
60059082 |
Sep 1997 |
US |
|
60059843 |
Sep 1997 |
US |
Continuations (1)
|
Number |
Date |
Country |
Parent |
09154357 |
Sep 1998 |
US |
Child |
09897670 |
Jul 2001 |
US |