Claims
- 1. A key assignor with a keyboard multiplexer comprising:
- a first memory for temporarily storing the state of key depression on a keyboard and producing key depression signals;
- a multiplex code generator for generating key codes respectively corresponding to each key;
- an inhibit circuit for controlling the key depression signals from the first memory;
- a priority circuit for outputting from the first memory only the key depression signal of top priority in accordance with a preset priority of keys of the keyboard;
- a second memory for temporarily storing the key depression signal selected by the priority circuit and having an output which causes the multiplex code generator to generate a key code corresponding to the key being depressed;
- a third memory directly responsive to said output of the second memory for storing the key depression signal stored in the second memory, and providing a signal to the inhibit circuit to inhibit further key depression signals;
- reset means for providing a write signal which resets the second memory after a predetermined period of time and causes the priority circuit to shift the priority of the keys of the keyboard, whereby a key depression signal of the next priority is processed, and wherein upon all depressed keys are processed, a new state of key depression is written in the first memory and the same processing is repeatedly performed, whereby key codes corresponding to depressed keys are sequentially generated.
- 2. A key assignor according to claim 1, and further comprising a plurality of key code memory means for storing said key codes, each said key code memory means comprising a key code memory for storing a key code corresponding to a depressed key, a comparator for comparing the key code stored in the key code memory and a key code from the keyboard multiplexer to output a coincidence signal when they are coincident with each other, a fourth memory for temporarily storing the coincidence signal from the comparator, an empty key code memory detector for detecting whether or not a key code is stored in the key code memory to output an empty channel signal, a second inhibit circuit responsive to the output from the empty channel detector, a fifth memory for temporarily storing the output from the second inhibit circuit, and a channel priority circuit for prioritizing the fifth memories of all of said key code memory means to output a signal for writing a key code only in the empty key code memory of the highest priority, wherein responsive to no coincidence signal being provided from the comparator, the empty key code memory detector provides the empty channel signal, and the second inhibit circuit applies therethrough the empty channel signal to the fifth memory for storage therein to write the key code in the key code memory in accordance with the priority of the channel priority circuit for assigning the key code to a channel, and wherein responsive to a coincidence signal being provided from the comparator an inhibit signal is applied to the second inhibit circuit to inhibit the same key code from being written in two or more channels, and wherein responsive to where a key code coincident with the key code stored in the key code memory is not provided from the keyboard multiplexer in the state of the key code being already assigned to the channel, the fifth memory detects this to clear the content of the key code memory.
Priority Claims (1)
Number |
Date |
Country |
Kind |
51-47559 |
Apr 1976 |
JPX |
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RELATIONSHIP TO OTHER APPLICATIONS
This application is a continuation-in-part application to Ser. No. 842,524 filed Oct. 17, 1977, now abandoned, by the present inventors.
US Referenced Citations (9)
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
842524 |
Oct 1977 |
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