Patent Application
20170076860
The present invention relates to a magnetic structure, and more specifically, to laminated magnetic material for on-chip magnetic inductors/transformers.
Electroless plating is a technique of plating metal by chemical rather than electrical means, in which the piece to be plated is immersed in a reducing agent that, when catalyzed by certain materials, changes metal ions to metal that forms a deposit on the piece.
Further, electroless plating, also known as chemical or auto-catalytic plating, is a non-galvanic plating method that involves several simultaneous reactions in an aqueous solution, which occur without the use of external electrical power. It is mainly different from electroplating by not using external electrical power. On the other hand, electroplating is a process that uses electric current to reduce dissolved metal cations so that they form a coherent metal coating on, e.g., an electrode.
According to one embodiment, a method of forming a laminated multilayer magnetic structure is provided. The method includes depositing an adhesion layer on a substrate, depositing a magnetic seed layer on top of the adhesion layer, and alternatingly depositing magnetic layers and non-magnetic spacer layers such that an even number of the magnetic layers is deposited while an odd number of the non-magnetic spacer layers is deposited. The odd number being one less than the even number. Every two of the magnetic layers is separated by one of the non-magnetic spacer layers, and the first of the magnetic layers is deposited on the magnetic seed layer. The magnetic layers each have a thickness less than 500 nanometers.
According to one embodiment, a laminated multilayer magnetic structure is provided. The structure includes an adhesion layer deposited on a substrate, a magnetic seed layer deposited on top of the adhesion layer, and magnetic layers and non-magnetic spacer layers alternatingly deposited such that an even number of the magnetic layers is deposited while an odd number of the non-magnetic spacer layers is deposited. The odd number is one less than the even number. Every two of the magnetic layers is separated by one of the non-magnetic spacer layers. The first of the magnetic layers is deposited on the magnetic seed layer, and the magnetic layers each have a thickness less than 500 nanometers.
One or more embodiments describe plated magnetic film materials required for 90% efficient monolithically integrated microbuck converters. According to one or more embodiments, the technique for the microbuck converters scale up CoWP electroless deposition chemistry for 200 millimeter (mm) wafers and uses NiP lamination layers.
Miniaturization of magnetic inductors and integration on semiconductor chips requires the use of high performance magnetic materials. In one or more embodiments, the requirements met include soft magnetic properties with low coercive force (Hc<1.0 oersted (Oe)) and high saturation magnetization, high resistivity (ρ>=110 microohm centimeter (μΩ·cm)) to reduce inductor losses at high frequencies from eddy currents, and excellent thermal stability to a processing temperature that is dictated by the integration process on-chip (≧200-250° Celsius (C)).
One or more embodiments demonstrate that a Co85W5P10 thin film deposited using an electroless chemistry on a Pd activated crystalline Ni80Fe20 or on amorphous CoFeB seed layer meets all the material requirements for a low process temperature integrated inductor. The electroless process was scaled up to 200 millimeter (mm) wafer size using a large magnet capable of applying 0.15 Telsa (T) at the wafer center. Typically, single thin magnetic films can have a complicated magnetic domain structure. Since most of the on-chip devices are operated at high frequencies (>100 megahertz (MHz)), a large eddy current could be induced within magnetic core which results in high alternating current (AC) losses at high frequency. One way to reduce eddy currents is to laminate the magnetic core/yoke with insulator spacers so that the eddy currents are confined within each magnetic layer. As the thickness of each magnetic layer gets thinner, the effective resistance of each magnetic layer gets larger, and hence the eddy currents are smaller.
Another function of the magnetic lamination is to control the magnetic domains. For on-chip planar inductors, magnetic anisotropy (i.e., easy and hard axis) has to be well defined. In the demagnetized state, the magnetic domain forms a flux-closed configuration at the edges of the pattern as shown in
According to embodiments, laminated multilayer structures were fabricated using thin nonmagnetic insulating films of NiP (Ni3P). The NiP films were also deposited by electroless deposition and are non-magnetic. According to one embodiment, there are two particular requirements for the NiP lamination layer: 1) to be pinhole free, and 2) to allow interlayer magneto static coupling between the magnetic thin films.
In materials that exhibit antiferromagnetism, the magnetic moments of atoms or molecules, usually related to the spins of electrons, align in a regular pattern with neighboring spins (on different sublattices) pointing in opposite directions. Antiferromagnets can couple to ferromagnets, for instance, through a mechanism known as exchange bias, in which the ferromagnetic film is either grown upon the antiferromagnet or annealed in an aligning magnetic field, causing the surface atoms of the ferromagnet to align with the surface atoms of the antiferromagnet. This provides the ability to “pin” the orientation of a ferromagnetic film.
Subheadings are utilized below for explanation purposes. The subheadings are not meant to limit the disclosure but are for ease of understanding.
I. Scale-Up of the Magnetic Thin Film Electroless Deposition
On-chip magnetic inductors/transformers are passive elements with wide applications as on-chip power converters and radio frequency (RF) integrated circuits. In order to achieve high energy density, magnetic core materials with thicknesses ranging several hundred nanometers to a few microns are often required. Ferrite materials that are often used in bulk inductors have to be processed at high temperature, e.g., higher than 800° C. Such a high temperature is not compatible with complementary metal-oxide semiconductor (CMOS) chip wiring processing temperatures that are kept below 400° C. for the chip wiring and below 250° C. for the solder bumps. The majority of the reported magnetic materials for integrated on-chip inductors are soft magnetic alloys such as NiFe, CoZrTa, and CoFeB.
These magnetic materials (i.e., soft magnetic allows) are typically deposited by vacuum deposition techniques such as physical vapor deposition (PVD) or chemical vapor deposition (CVD). Vacuum methods have the ability to deposit a large variety of magnetic materials. Vacuum processes typically result in deposits that are difficult to pattern or shape accordingly. Excess deposits need to be removed by a combination of etching and planarization processes and this approach adds considerable cost to the final product. Additionally, patterning these materials leaves jagged and sloping edges, which tend to nucleate strongly pinned magnetic domains.
Compared to ferrite materials, magnetic alloys usually have significantly higher permeability and magnetic flux density, which are needed to achieve high energy density for on-chip devices. However, the resistivity of polycrystalline magnetic alloys is usually low (<100 μΩ·cm).
It has been experimentally shown that CoWP layers, suitable for integrated magnetic core inductors, may be fabricated with a resistivity of 110 μΩ·cm and with soft magnetic properties that were stable after an anneal to 200° C. The high resistivity for the magnetic CoWP alloy was achieved by increasing the P and the W concentration in the film. The deposited CoWP films were amorphous. Non-magnetic lamination layers of NiP were deposited and structures with magnetic CoWP layers laminated with non-magnetic NiP layers were fabricated and evaluated.
II. Electroless CoWP Chemistry
In order to activate the magnetic NiFe or CoFeB seed layer surface, a 55 ppm palladium sulfate solution in 10% sulfuric acid was used at room temperature (22° C.) for 2 minute (min). The palladium dissolves the NiFe or CoFeB seed layer and creates a 10-20 Angstrom (Å) thin layer of palladium nanoparticles on the surface. Optionally, the Pd activation step can be omitted.
An electroless bath 215, which contained cobalt sulfate, sodium hypophosphite, sodium tungstate, citric acid as a metal complexant, boric acid as a buffer, polyethylene glycol as an additive and lead acetate as a bath stabilizer, was used for the CoWP electroless deposition. The polyethylene glycol prevented spontaneous plating on silicon at the back-side of the wafer 220. The solution pH was adjusted to 9.0+0.15 at room temperature (22° C.). The electroless deposition was carried out at 90° C.±1° C. Example bath composition for electroless CoWP deposition and operating conditions of plating are shown in Table 1 of
III. Non-Magnetic NiP as a Spacer for Lamination of CoWP
In exemplary experiments, a 55 parts per million (ppm) palladium sulfate solution in 10% sulfuric acid was used for 2 min at room temperature in order to activate the CoWP for electroless plating. An electroless bath, which contains nickel sulfate, sodium acetate, and sodium hypophosphite as a reducing agent with pH 4, was employed for the NiP deposition as described in Table 2 of
The experimenters developed a chemistry that produces a Ni3P thin film that has non-magnetic properties for use as the laminated layer in between CoWP layers (magnetic layers) and/or in between NiFe layers (magnetic layers). To achieve a desired non-magnetic Ni3P layer, the nickel and phosphorus have a 3:1 ratio of nickel to phosphorus deposited on top of CoWP, and the non-magnetic Ni3P layer has a (target) thickness between 2-500 nm, in one implementation. The experimenters determined that a combination of nickel, acetate, and hypophosphite at pH 4 can achieve the 3:1 ratio of Ni:P at 50° C. to 80° C. NiP plated samples (i.e., wafers 220) were confirmed to be non-magnetic with VSM, and stacks of CoWP/Ni3P/CoWP were built as proof of concept. In order to create the required thickness for the laminated layers of Ni3P (e.g., 2-500 nm), a lower temperature for the Ni3P deposition is preferred (but not a necessity), and 50° C. was used in one implementation. At 50° C. the NiP deposition rate is 2-5 nm/min depending upon whether Pd activation is used.
At 50° C. and with Pd activation, the rate of NiP deposition is 5 nm/min as shown in
IV. Annealing
Some samples (i.e., wafers 220) were annealed in a vacuum furnace (Magnetic Solution, MRT-1000) where a magnetic field of 1 Tesla was applied along the easy axis. For the thermal testing, samples were placed in a Hereaus oven under a constant flow of forming gas. The annealing temperature was set to 200 or 250° C. for one hour. A temperature ramping rate of 5° C./min and a cooling rate of 5° C./min under constant nitrogen gas flow was used.
After the CoWP or the laminated CoWP/NiP/CoWP/NiP/CoWP/NiP/CoWP deposition, samples were annealed for 30 minutes at 150° C. in a vacuum oven with an applied magnetic field of 1 T, and annealed at 200° C. and at 250° C. in a forming gas atmosphere for 1 hour. This post deposition annealing was implemented for stress relaxation and for evaluating the film magnetic properties in a post annealed state. These conditions simulated annealing conditions of insulator curing during the building of the inductor device.
V. Measurements and Characterization
Sheet resistance measurements were obtained with a Magnetron Instruments M700 4-point probe immediately after deposition, and also after annealing. An average resistivity was calculated from the sheet resistivity utilizing the total film thicknesses involved. The seed and plated layers have different resistivity (and the layer resistivity may vary within the individual layer thickness), but the average value for a representative total thickness is characteristic of what will be important in electrical usage.
Magnetic hysteresis loop measurements were performed using a Vibrating Sample Magnetometer (VSM) (MicroSense Model 10) on nominally one inch square samples. The applied magnetic field was typically varied between −100 Oe and +100 Oe. Precise reporting of moment densities was not emphasized in this work, but moment values reported were observed to be generally consistent to ±5 to 10%. Any differences greater than this within a series, for example before and after annealing, are likely changes characteristic of the samples involved.
Crystallographic characterization was performed in a Philips XRD System using Cu Kα line radiation. Cross sections of the specimens were prepared using a focus ion beam (FIB 200TEM workstation), and images were taken in a scanning electron microscope (LEO Zeiss 1560) or with a transmission electron microscope with energy dispersive spectroscopy (TEM/EDS).
Secondary ion mass spectrometry (SIMS) depth profile experiments were performed on a magnetic sector Cameca Wf Ultra instrument equipped with a 36° O2+ column and a floating 60° C. s+ column. Profiles for different trace metals were acquired using a 150 nA3 kilo-electronvolt (keV) O2+ ion beam, while analyzing positive ions (59Co+, 184W+, 31P+) at high mass resolution (M/ΔM=4000) to eliminate mass interferences. Due to the absence of standard samples in the SIMS analysis, count number comparisons between different diffusion species of Co, W, P was not utilized.
Compositional and thickness analyses were performed on the films by Rutherford Backscattering Spectrometry (RBS) using an NEC 3UH Pelletron instrument. The analysis beam was 4He+ at an energy of 2.3 mega-electronvolt (MeV) with a beam current of 30 nanoamps (nA). The total collected charge was 40 microcoulombs (μC). The samples were tilted by 7 degrees off normal and the scattered He ions were detected at a backscattered angle of 170° degrees. The film composition was determined by the ratio of the Co, W, and P peak areas or by the ratio of Co, Fe, and B peak areas. The film thickness was determined by the sum of the Co, W, P peak areas, using the bulk CoWP density. Permeability measurements were performed using a Ryowa Permeameter model PMF-3000.
V. Example Results of Laminated CoWP Films with NiP
Magnetic thin films with insulator multilayer laminated structures have attracted considerable attention because of their ability to substantially reduce eddy current loss compared to the single magnetic layers. According to an embodiment, laminated multilayer structures were fabricated using thin nonmagnetic insulating films of NiP. The NiP films were deposited by electroless deposition. According to an embodiment,
Depositions of each layer of CoWP were always performed in the presence of a magnetic field, while the depositions of each layer of NiP were performed without the magnetic field. Permeability measurements of a 250 nm CoWP (four layers (4×)) and NiP (three layers (3×)) laminated structure are shown
For the alternatively laminated films of CoWP layers and NiP layers (totaling 1.15 μm), a waveform 805A is the real part of relative permeability and a waveform 805B is the imaginary part of relative permeability. For the single 1.23 μm CoWP layer, the real part of the permeability is 810A and the imaginary part is of the permeability is 810B. The real part of relative permeability in waveform 805A has a constant value of 250-300 (dimensionless number with no units) with a roll off frequency at 350 MHz higher than the waveform 810A for the single CoWP layer that has a roll off frequency at 250 MHz. The imaginary part of the relative permeability has a broad peak at 1 GHz possibly indicating good magnetic behavior at high frequency. The permeability measurements demonstrate that the laminated films (of CoWP layers and NiP layers) have lower losses at a frequency higher than 100 MHz.
According to an embodiment,
The graphs in
Next, a laminated structure of CoWP film with 100 nm CoWP layers and 10 nm NiP non-magnetic spacers in between was examined. In this laminated structure, the CoWP film at the bottom is as thin as 67 nm. The total thickness of the laminated films is 0.357 μm. Layers are progressively thicker and smother from bottom to the top of the structure.
As can be seen, the 250 nm CoWP/10 nm NiP laminated structure and the 250 nm CoWP/40 nm NiP laminated structure can be utilized for device integration and accommodate the 250° C. maximum temperature integration route. A beneficial requirement for the CoWP/NiP laminated structure is that the interfaces between the layers are smooth and pinhole free. This ensures soft magnetic properties of the laminated structure and antiferromagnetic magnetostactically coupled magnetic layer with low magnetic losses.
At block 1205, a wafer 220 may have a barrier layer 1305 optionally disposed on top. If the wafer 220 is silicon, the barrier layer 1305 may be silicon dioxide grown and/or deposited on the silicon wafer 220. The barrier layer is non-conducting.
At block 1210, an adhesion layer 1310 is disposed on top of the barrier layer 1305 if present, and/or otherwise the adhesion layer 1310 is disposed directly on top of the wafer 220. The adhesion layer 1310 may be deposited by PVD and/or CVD. Example materials of the adhesion layer 1310 may include Ti, TiN, Ta, and/or TaN.
At block 1215, a magnetic seed layer 1315 may be disposed on top of the adhesion layer 1310. The magnetic seed layer 1315 may be deposited by PVD and/or CVD. Example materials may be NiFe, CoFe, NiFePB, and/or CoFePB. It is noted that block 1220 begins the electroless plating fabrication operations.
At block 1220, as an optional Pd activation, a Pd activation layer 1320-1 may be disposed on top of the magnetic seed layer 1315. The Pd activation layer 1320-1 may not necessarily be continuous, and may be nanocrystals or nanoparticles as discussed above. In one implementation, the Pd activation layer 1320-1 may be nanocrystals of Pd about 2-5 angstroms Å thick. The Pd activation layer 1320-1 (though Pd activation layer 1320-M, where M is the last activation layer 1320) acts as a catalyst to activate the surface. In another implementation, Ni or Co may be utilized as the activation layer 1320-1 although Pd works better than both. Ni works better than Co.
At block 1225, optionally, an activation solution without metals may be added to the solution bath 215. As noted above, in order to activate the plating when CoWP is the magnetic layer, the activation solution may be formulated to contain all the CoWP solution components, e.g., in Table 1 except for the metal salts of cobalt and tungsten. When another chemical compound is to be plated, the activation solution is to contain all the materials for plating except for the metals.
At block 1230, a CoWP magnetic layer 1325A is deposited on top of the Pd activation layer 1320-1. In one implementation, the bath solution 215 may include the chemistry discussed in Table 1 in order to deposit the CoWP magnetic layer. Although the example illustrates that the magnetic layers 1325A-1325N (where N is the last magnetic layer 1325) are CoWP, other materials may be utilized for the magnetic layers 1325A-1325N. In one implementation, the magnetic layers 1325A-1325N may include CoWPB where P is less than 15% and B less than 15%. In another implementation, the magnetic layers 1325A-1325N may include NiFePB, where P is less than 15% and B less than 15%. In yet another implementation, the magnetic layers 1325A-1325N may include CoFeBP, where P is less than 15% and B less than 15%.
At block 1235, as an optional Pd activation, the Pd activation layer 1320-2 may be disposed on top of the CoWP magnetic layer 1325A in preparation for depositing a non-magnetic spacer layer.
At block 1240, a non-magnetic spacer layer 1330A is deposited on top of the Pd activation layer 1320-2. It is again noted that the Pd activation layer 1320 may not be continuous (e.g., may be crystals) and the non-magnetic spacer layer 1330A may actually be deposited directly on portions of the CoWP magnetic layer 1325A. In one implementation, the non-magnetic spacer layers 1330A-1330N−1 may be Ni3P. In one case, the thickness of the Ni3P is greater than 10 nm but less than 500 nm. In another implementation, the non-magnetic spacer layers 1330A-1330N−1 may be Co2P. In yet another implementation, the non-magnetic spacer layers 1330A-1330N−1 may be Fe3P.
At block 1245, as an optional Pd activation, the Pd activation layer 1320-3 may be disposed on top of the non-magnetic spacer layer 1330A in preparation for depositing a non-magnetic spacer layer.
At block 1250, optionally, an activation solution without metals may be added to the solution bath 215 (just as in block 1225). As noted above, in order to activate the plating, the activation solution may be formulated to contain all the CoWP solution components (in Table 1) except for the metal salts of cobalt and tungsten.
At block 1255, the CoWP magnetic layer 1325B is deposited on top of the Pd activation layer 1320-3 (as discussed in block 1230).
At this point, the fabrication process may continue repeating the plating operations of blocks 1235, 1240, 1245, 1250, and 1255 in a loop until the desired amount of layers has been deposited. The laminated multilayer magnetic structure 1300 is illustrated with activation layers 1320-1 through 1320-M, CoWP magnetic layers 1325A through 1325N, non-magnetic spacer layers 1330A though 1330N−1, and non-magnetic spacer layers 1330A through 1330N−1. More or fewer layers may be fabricated.
At block 1405, the adhesion layer 1310 is deposited on a substrate (e.g., a wafer 220), and the magnetic seed layer 1315 is deposited on top of the adhesion layer 1310 at block 1410.
At block 1415, magnetic layers 1325A through 1315N and non-magnetic spacer layers 1330A through 1330N−1 are alternatingly deposited, such that an even number of the magnetic layers is deposited while an odd number of the non-magnetic spacer layers is deposited, where the odd number (e.g., total magnetic layers N) is one less than the even number (e.g., total non-magnetic spacer layers N−1).
At block 1420, every two of the magnetic layers 1325 is separated by one of the non-magnetic spacer layers 1330. In another words, each of the individual non-magnetic spacer layers 1330 is sandwiched between two individual magnetic layers 1325.
At block 1425, the first of the magnetic layers (e.g., magnetic layer 1325A) is deposited on the magnetic seed layer 1315. At block 1425, the magnetic layers 1325A through 1325N each have a thickness less than 500 nanometers. The experimenters have observed and determined that when the single magnetic layer has a thickness of 500 nm, then single magnetic layer tends to recrystallize from an amorphous layer to a crystalline layer at a temperature of 200° C. Integrating the magnetic materials on a silicon chip requires a processing temperature higher than 200° C. Crystalline magnetic layers exhibit high magnetic losses due to eddy currents and to a high damping coefficient. Ideally, a single magnetic domain is preferred (but not a necessity) in each magnetic layer. The single magnetic domain can be achieved with amorphous magnetic thin films that have a resistivity >110 μΩ·cm.
Further, the magnetic layers 1325 comprise CoWP. The magnetic layers 1325 are selected from a group comprising CoWPB, NiFeBP, and CoFePB, where P has less than 15% and B has less than 15% of the total chemical compound. The magnetic layers are amorphous.
The magnetic seed layer 1315 is selected from a group comprising NiFe, CoFe, NiFeBP, and CoFeBP.
The non-magnetic spacer layers 1330A through 1330N are each of equal thickness. The non-magnetic spacer layers 1330A through 1330N each comprise Ni3P. The Ni3P has a thickness of 2-500 nm. The non-magnetic spacer layers 1330A through 1330N are selected from a group comprising Ni3P, Co2P, and Fe3P.
Nanoparticles of Pd (illustrated as Pd activation layers 1320-1 through 1320-M) are deposited at interfaces of the magnetic layers 1325 and non-magnetic spacer layers 1330, when the magnetic layers 1325 and the non-magnetic spacer layers 1330 are deposited by electroless plating.
Nanoparticles of Pd are not utilized when the magnetic layers 1325 and the non-magnetic spacer layers 1330 are deposited by electroplating (and/or other deposition techniques), and the magnetic layers 1325 and non-magnetic spacer layers 1330 are contiguous (i.e., directly touching) without Pd crystals in between as shown in
Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include, but are not limited to, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others.
Removal is any process that removes material from the wafer: examples include etch processes (either wet or dry), and chemical-mechanical planarization (CMP), etc.
Patterning is the shaping or altering of deposited materials, and is generally referred to as lithography. For example, in conventional lithography, the wafer is coated with a chemical called a photoresist; then, a machine called a stepper focuses, aligns, and moves a mask, exposing select portions of the wafer below to short wavelength light; the exposed regions are washed away by a developer solution. After etching or other processing, the remaining photoresist is removed. Patterning also includes electron-beam lithography, nanoimprint lithography, and reactive ion etching.
The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.
This application is a continuation of U.S. patent application Ser. No. 14/854,523, filed Sep. 15, 2015, the disclosure of which is incorporated by reference herein in its entirety.
This invention was made with Government support under University of California Subcontract B601996 awarded by the Department of Energy. The Government has certain rights to this invention.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 14854523 | Sep 2015 | US |
| Child | 14950364 | US |
