Large-dynamic-range lookup table for a transmitter predistorter and system and method employing the same

Abstract

A predistorters for use with a nonlinear element and methods of predistorting for a nonlinear element for use in a 3G, e.g., WCDMA transmitter. In one embodiment, the predistorter includes: (1) a lookup table having non-uniformly spaced entries therein, (2) a compander configured to compand an input signal based on a nonlinearity of the nonlinear element to address the entries and (3) an interpolation offset calculation circuit associated with the lookup table and configured to produce an output based on a value of the input signal and a linear interpolation involving at least two entries from the lookup table.

Description

TECHNICAL FIELD OF THE INVENTION

The invention is directed, in general, to wireless transmitters and, more specifically, to a large-dynamic-range lookup table (LUT) for a transmitter predistorter and a system and method employing the LUT to perform predistortion.

BACKGROUND OF THE INVENTION

Many applications exist for battery-powered, digital wireless transmitters, primarily in cellular communications systems such as those operating under the International Telecommunication Union's Wideband Code Division Multiple Access (WCDMA) standard or other so-called “3G” standards. Such transmitters use one or more amplifiers to amplify components of the input signal to be transmitted. These components are amplitude and phase components in the case of a polar transmitter and in-phase and quadrature components in the case of a Cartesian transmitter.

A highly linear amplifier distorts the signal the least and so is most favored from a standpoint of signal quality. Unfortunately, highly linear amplifiers use relatively large amounts of power and numbers of highly accurate components, making them relatively power consumptive, large and expensive. Though they perform the best, they are thus disfavored in many wireless applications, particularly those that require low-cost transmitters. The amplifier that is best suited overall for low-cost, battery-powered wireless transmitters is a simple amplifier having significant nonlinearity. See, for example, FIG. 1A, in which a nonlinear amplifier 110 distorts a substantially sinusoidal input signal.

Predistortion is often used to compensate for this nonlinearity, resulting in a linearization of the output of the amplifier. The theory underlying predistortion is that, if an amplifier's distortion characteristics are known in advance, an inverse function can be applied to an input signal to predistort it before it is provided to the amplifier. Though the amplifier then distorts the signal as it amplifies it, the predistortion and the amplifier distortion essentially cancel one another, resulting in an amplified, output signal having substantially reduced distortion. See, for example, FIG. 1B, in which a digital predistorter 120 predistorts the substantially sinusoidal input signal such that the output signal is likewise sinusoidal.

In digital transmitters, digital predistortion (DPD) is most often carried out using an LUT that associates output values with input signal values. Entries in the LUT are addressed using samples of the input signal. The output values retrieved from the LUT are used either to predistort the samples (an “inverse gain” configuration) or in lieu of the samples (a “direct mapping” configuration). In modern applications such as WCDMA, samples are transmitted at a very high rate. Thus, the predistorter needs to be able to look up and retrieve output values very quickly.

The spacing between successive LUT entries defines the mapping accuracy. LUTs are capable of providing a nonlinear mapping for signals with a large dynamic range, which is essential for complying with 3G standards such as WCDMA. Most applications employ a uniformly spaced LUT. However, the performance of a uniformly spaced LUT degrades considerably at lower input signal levels because an increase in the signal dynamic range relative to the quantization level substantially decreases the signal-to-noise ratio (SNR). Nonlinear spacing techniques in which more entries are heuristically placed where the mapping is nonlinear can, in theory, mitigate this problem. Unfortunately, although these techniques improve LUT performance in some applications, they do not handle arbitrary nonlinearity well and do not work well in demanding applications, such as transmitter linearization.

A predistortion LUT is typically created when a transmitter is calibrated at the factory. Unfortunately, a factory-calibrated predistortion LUT often fails to linearize the amplifier adequately under varying operational conditions (e.g., temperature, voltage, frequency and voltage standing-wave ratio, or VSWR). Aging, especially in WCDMA and other 3G transmitters, only exacerbates the inadequacy.

SUMMARY OF THE INVENTION

To address the above-discussed deficiencies of the prior art, the invention provides predistorters for use with a nonlinear element and methods of predistorting for a nonlinear element. In one embodiment, a predistorter includes: (1) a LUT having non-uniformly spaced entries therein, (2) a compander configured to compand an input signal based on a nonlinearity of the nonlinear element to address the entries and (3) an interpolation offset calculation circuit associated with the LUT and configured to produce an output based on a value of the input signal and a linear interpolation involving at least two entries from the LUT. In another embodiment, a predistorter includes: (1) a LUT containing base-2-spaced entries, (2) an address calculation block associated with the LUT and configured to calculate addresses for the entries based on a mapping between an amplitude of an input signal and bits of the addresses and (3) an interpolation circuit associated with the LUT and configured to produce a selected one of an interpolation factor and an interpolated output based on a bin width and an offset derived from the input signal.

Another aspect of the invention provides methods of predistorting for a nonlinear element. In one embodiment, a method includes: (1) companding an input signal based on a nonlinearity of the nonlinear element to address uniformly spaced entries contained in a LUT and (2) producing an output from the LUT based on a linear interpolation involving a value of the input signal and at least two of the entries. In another embodiment, a method includes: (1) calculating addresses for base-2-spaced entries in a LUT based on a mapping between an amplitude of an input signal and bits of the addresses and (2) producing a selected one of an interpolation factor and an interpolated output based on a bin width and an offset derived from the input signal.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIGS. 1A and 1B are high-level schematic diagrams showing amplifier distortion, particularly the impact of a simple compression nonlinearity on time domain signal, and a conceptual view of DPD to counteract the transmitter nonlinearity;

FIG. 2 is a high-level schematic diagram of a polar transmitter having a complex baseband and containing an embodiment of a transmitter predistorter;

FIG. 3 is a plot of the power density distribution (PSD) of a WCDMA signal using 128-word linearly interpolated (Lin) and zero-order hold (ZOH) LUTs;

FIG. 4 is a high-level schematic diagram showing nonuniform LUT spacing using a companding function;

FIGS. 5A, 5B and 5C are plots showing the degradation caused by transmitter compression nonlinearity in a WCDMA transmitter in terms of error vector magnitude (EVM), a first adjacent channel leakage ratio at 5 MHz offset (ACLR1) and a second adjacent channel leakage ratio at 10 MHz offset (ACLR2), respectively;

FIGS. 6A and 6B are block diagrams of an adaptive indirect closed loop predistorter in a polar 3G WCDMA transmitter and a Cartesian 3G WCDMA transmitter, respectively;

FIGS. 6C and 6D are block diagrams respectively showing direct-mapping predistortion and complex gain predistortion;

FIG. 7 is a high-level schematic diagram showing nonuniform LUT spacing using a companding function and subsequent amplification;

FIGS. 8A and 8B are plots showing the effect of LUT size and spacing on EVM using uniform and μ-law spacing, respectively;

FIGS. 9A and 9B are plots showing the effect of LUT size and spacing on ACLR1 using uniform and μ-law spacing, respectively;

FIGS. 10A and 10B are plots showing the effect of LUT size and spacing on ACLR2 using uniform and μ-law spacing, respectively;

FIG. 11 is schematic diagram graphically illustrating one embodiment of an LUT entry address calculation technique;

FIG. 12 is a schematic diagram of one embodiment of an address calculation circuit;

FIG. 13 is a schematic diagram of one embodiment of an interpolation offset calculation circuit;

FIG. 14 is a plot showing a mapping of LUT input signal amplitudes to LUT entry addresses;

FIGS. 15A, 15B and 15C are plots showing the effect of WCDMA transmitter performance using base-2 spacing in terms of EVM, ACLR1 and ACLR2, respectively;

FIGS. 16A, 16B and 16C are plots showing the effect of WCDMA transmitter performance using improved base-2 spacing in terms of EVM, ACLR1 and ACLR2, respectively;

FIGS. 17A and 17B are high-level schematic diagrams showing direct mapping and inverse gain configurations, respectively;

FIGS. 18A and 18B are linear/log scale plots showing LUT step size across a 10-bit input for direct mapping and inverse gain LUT configurations, respectively;

FIGS. 19A and 19B are plots showing the effect of WCDMA transmitter EVM performance using improved base-2 spacing for a direct mapping LUT using 16-20 bits and an inverse gain LUT using 8-13 bits, respectively;

FIGS. 20A and 20B are plots showing the effect of WCDMA transmitter ACLR1 performance using improved base-2 spacing for a direct mapping LUT using 16-20 bits and an inverse gain LUT using 8-13 bits, respectively;

FIGS. 21A and 21B are plots showing the effect of WCDMA transmitter ACLR2 performance using improved base-2 spacing for a direct mapping LUT using 16-20 bits and an inverse gain LUT using 8-13 bits, respectively;

FIG. 22 is a flow diagram of one embodiment of a method of predistorting for a nonlinear element carried out according to the principles of the invention; and

FIG. 23 is a flow diagram of another embodiment of a method of predistorting for a nonlinear element carried out according to the principles of the invention.

DETAILED DESCRIPTION

Described herein are efficient LUT spacing (or mapping) techniques. One technique uses a linearly interpolated LUT (a “Lin-LUT”) and a companding function to address the LUT. The companding function is based on the inverse of the nonlinearity that the predistortion is designed to correct. The result is a substantially constant performance across relevant amplitude ranges. Another technique uses a nonlinear, base-2 or modified base-2 LUT spacing that is amenable to efficient index lookup and interpolation between LUT entries. As a result, division in interpolation may no longer be needed, reducing power requirements and increasing operational speeds. Predistorters, transmitters and various methods based on the techniques will also be described.

Theoretical results that relate the spacing of a linearly interpolated LUT to the PA nonlinear characteristics for a dynamic modulation signal will be described herein. Design selection and optimization details of one embodiment of a LUT for a WCDMA transmitter predistorter will then be described. The structure of a predistorter LUTs can be critical to the performance of a WCDMA transmitter as a whole; if the discrete quantization in the LUT is inappropriately selected, both close-in and far-out transmitted signal properties may be degraded.

The described LUT configuration (i.e., spacing and interpolation technique) can be used for both polar and Cartesian transmitter architectures. For a WCDMA transmitter, the input signal may cover a dynamic range of approximately 110 dB to satisfy both power level as well as signal integrity requirements.

Theoretical results that relate the spacing of a linearly interpolated LUT to the probability distribution of a dynamic input signal will now be described. As FIGS. 1A and 1B signify in their use of the term “nonlinear element,” a predistortion LUT can be employed to compensate for nonlinearity in any device or element, and not just an amplifier. Accordingly, the theoretical results described below, and predistorters, methods, transmitters and other systems having nonlinear elements that employ the same, are within the broad scope of the invention irrespective of the type of nonlinear element with which a predistortion LUT may be designed to operate.

1. Constant-SNR Spacing Technique for Linearly Interpolated Predistorter LUTs

1.1. Linear Interpolation in Predistorter LUTs

The use of predistorters employing Lin-LUTs is an efficient way to reduce LUT approximation error (see, e.g., Faulkner, et al., “Adaptive Linearization Using Predistortion—Experimental Results,” in IEEE Trans. on Veh. Technol., vol. 43, May 2004, pp. 323-332, and Teikari, et al., “Baseband Digital Predistorter with Quadrature Error Correction,” in Norchip Conference Proc., November 2004, pp. 159-162). However, no evidence exists that the performance of Lin-LUTs has ever been analyzed. Therefore, the performance of Lin-LUTs will now be analyzed.

Lin-LUTs will be analyzed in the context of a polar transmitter. However, the analysis extends easily to a Cartesian transmitter. FIG. 2 is a high-level schematic diagram of a polar transmitter having a complex baseband and containing an embodiment of a transmitter predistorter. A splitter 210 in the baseband splits an input signal ν_i into an amplitude component ρ and a phase component θ. The predistorter 120 then employs two LUTs, an LUT F to predistort the amplitude component ρ and an LUT P to predistort the phase component θ to yield predistorted amplitude and phase components ρ_a and θ_a, respectively. The amplifier 110 then amplifies the predistorted amplitude and phase components ρ_a and θ_a, which are then recombined to yield an output signal ν_o. Nonlinear amplitude modulation-amplitude modulation (AM-AM) and amplitude modulation-phase modulation (AM-PM) distortions occurring in the amplifier 110 are respectively designated by the amplitude-dependent functions G(r) and ψ(r).

The two LUTs in the predistorter 120 approximate the inverse of the amplifier's amplitude distortion function F(r)=G⁻¹(r) and phase compensation function P(r)=−ψ(F(r)). The LUT approximation errors of F(r) and P(r) respectively result in independently computable amplitude and phase errors at the output of the amplifier. The derivations for the two types of errors are similar. Therefore, only the amplitude error will be explicitly derived herein.

To simplify mathematical expressions, the following derivation assumes that the gain and the input and output impedances of the amplifier are normalized to one (i.e., K=1). The k^th bin of the amplitude LUT is delimited by the amplitude entries r_k and r_k+1, and d_k=r_k+1−r_k is defined to be the width of the k^th interval. The amplitude predistorter F(r) is precisely determined at r_k and r_k+i. For an input amplitude r=r_k+δr, with 0<δ_r<d_k, the linearly interpolated LUT results in an approximation error given by:

$\begin{array}{cc}{\delta }_F=F^{″}\left(r\right)\frac{{\delta }_r\left({\delta }_r-d_k\right)}{2},& \left(1\right)\end{array}$ where F″ is the second-order derivative of F. The amplitude at the output of the amplifier (with normalized gain K=1) is:r_o=r_k+e_rk=G(F+δ_F),  (2)where e_rk is the amplitude error at the amplifier input. Equation (2) can be simplified using a first-order approximation as:

$\begin{array}{cc}\begin{array}{c}{r}_o=G\left(F\left(\mathrm{rk}\right)\right)+G^{\prime }\left(F\left(r_k\right)\right)\times {\delta }_F\\ =r_k+{F^{\prime }\left(r_k\right)}^{-1}\times {\delta }_F,\end{array}\hspace{1em}& \left(3\right)\end{array}$ where Equation (3) uses the relation between F and G, i.e., F=G⁻¹=>G′=1/F⁻¹. F′ is assumed not to change appreciably within the bin (i.e., the number of LUT entries is large enough). Therefore, the amplitude MSE is:

$\begin{array}{cc}{e}_{\mathrm{rk}}=r_o-r_k=\frac{F^{″}\left(r_k\right)}{F^{\prime }\left(r_k\right)}\frac{{\delta }_r\left({\delta }_r-d_k\right)}{2}.& \left(4\right)\end{array}$

The noise contribution of the k^th bin to the output SNR can be computed using the usual quantizer assumption that δ_r is a random variable uniformly distributed in [0, d_k]. The amplitude mean squared error (MSE) contribution of the k^th bin is:

$\begin{array}{cc}\begin{array}{c}E\left(e_{\mathrm{rk}}^2\right)=\frac{{F^{″}\left(r_k\right)}^2}{4d_k{F^{\prime }\left(r_k\right)}^2}{\int }_0^{d^k}{r}^2\left(r-d_k\right)dr\\ =\frac{{F^{″}\left(r_k\right)}^2}{120{F^{\prime }\left(r_k\right)}^2}{d}_k^4.\end{array}& \left(5\right)\end{array}$

For an arbitrary LUT spacing achieved using a companding function S(r), the bin width is given by:

$\begin{array}{cc}{d}_k\approx \frac{V}{N\times S^{\prime }\left(r_k\right)},& \left(6\right)\end{array}$ where N is the LUT size and V is the maximum amplitude addressable by the LUT. For the special case of uniform spacing S(r)=r and d_k=V/N is constant. Assuming that the number of LUT bins is sufficiently large, the total amplitude MSE at the amplifier output is:

$\begin{array}{cc}{P}_{\rho }=\frac{V^4}{120N^4}{\int }_0^A\frac{{F^{″}\left(r\right)}^2}{{S^{\prime }\left(r\right)}^4{F^{\prime }\left(r\right)}^2}p\left(r\right)dr,& \left(7\right)\end{array}$ where p(r) is the probability density function of the input amplitude and A is the maximum amplitude of the input signal. Similarly, the phase MSE can be obtained as:

$\begin{array}{cc}{P}_{\theta }=\frac{{\tilde{V}}^4}{120N^4}{\int }_0^{\tilde{A}}\frac{{P^{″}\left(r\right)}^2}{{S^{\prime }\left(r\right)}^4}p\left(\tilde{r}\right)d\tilde{r},& \left(8\right)\end{array}$ where {tilde over (r)}=F(r) is the predistorted amplitude, and à is its maximum value. Equations (7) and (8) show that the amplitude and phase MSEs are inversely proportional to N⁴ which is a much faster rate of decrease than a ZOH LUT can attain, resulting in an MSE that is inversely proportional to N². The predistorted signal SNR increases by 12 dB if the LUT size is doubled, as opposed to 6 dB for a ZOH LUT. FIG. 3 compares the two approaches to the ideal. For a WCDMA signal, linear interpolation improves the EVM by 25 dB, ACLR1 by 0.5 dB and ACLR2 by 17 dB.

1.2. Nonuniform Predistorter LUT Spacing

The nonuniform spacing of the LUT can be achieved by applying a companding function S(r) 410 to the input amplitude r as FIG. 4 illustrates. Address calculation 420 is performed on the companded amplitude, and a LUT 430 lookup is then performed.

To simplify the analysis, the linearly interpolated LUT can be viewed as a piecewise linear approximation of a function ƒ(r) sampled at points (r_k, y_k), where y_k=θ(r_k). The companding function then projects a set of N uniformly spaced sampling points

$r_k=r\frac{V}{N}$ to a set of N nonuniformly spaced sampling points {tilde over (r)}_k using the relation: {tilde over (r)}_k=S⁻¹(r_k).

The nonuniform LUT spacing technique described herein can yield a substantially constant SNR across the entire output power dynamic range, or at least a range of interest, such that a single low-resolution, fixed-range LUT can be used for all power levels. If desired, the candidate spacing can be independent from both signal and amplifier characteristics.

μ-law companding was developed to achieve such a goal for the quantization of speech signals. Equation (9) mathematically describes μ-law companding:

$\begin{array}{cc}{S}_{\mu }\left(r\right)=V\frac{\ln \left(1+\mu r/V\right)}{\ln \left(1+\mu \right)}.& \left(9\right)\end{array}$ For speech signal quantization, μ is often chosen to be equal to 256 (eight bits). But for WCDMA, a value between 32 and 64 (five to six bits) appears to provide a better performance balance across all power levels.

The resulting spacing can be derived using Equation (6):

$\begin{array}{cc}d\left(r\right)\approx \frac{V}{{\mathrm{NS}}^{\prime }\left(r\right)}=\frac{V\mu }{N\ln \left(1+\mu \right)}\left(1+\mu r/V\right).& \left(10\right)\end{array}$ Note that the LUT spacing increases linearly with the input amplitude. The resulting amplitude and phase MSEs can be calculated using Equations (7) and (8), respectively:

${{P_{\rho }=\frac{V^4\mu }{120N^4\ln \left(1+\mu \right)}{\int }_0^A\frac{{F^{″}\left(r\right)}^2}{{F^{\prime }\left(r\right)}^2}\left(1+\mu r\right)/V)}^{4}p\left(r\right)dr\mathrm{and}{P}_{\theta }=\frac{{\tilde{V}}^4\mu }{120N^4\ln \left(1+\mu \right)}{\int }_0^{\tilde{A}}{P^{″}\left(r\right)}^2\left(1+\mu r\right)/V)}^{4}p\left(\tilde{r}\right)d\tilde{r}.$

A companding function that yields a substantially constant SNR at all amplitudes can be derived using Equation (5). The sample-based SNR of the amplitude LUT can now be approximated by:

$\begin{array}{cc}\begin{array}{c}\mathrm{SNR}\left(r\right)=\frac{r^2}{E\left(e_r^2\right)}\\ =\frac{120N^4{r}^2{S_{\rho }^{\prime }\left(r\right)}^4{F^{\prime }\left(r_k\right)}^2}{V^4{F^{″}\left(r_k\right)}^2}\end{array}& \left(11\right)\end{array}$ In Equation (11), a constant SNR across all amplitudes can only be obtained if:

$\begin{array}{cc}{S}_{\rho }^{\prime }\left(r\right)={{\lambda }_{\rho }\left(\frac{F^{″}\left(r\right)}{F^{\prime }\left(r\right)}\times \frac{1}{r}\right)}^{1/2},& \left(12\right)\end{array}$ where λ_ρ is a constant. The amplitude and phase LUT compander therefore can be expressed as:

$\begin{array}{cc}{S}_{\rho }\left(r\right)={\lambda }_{\rho }\int {\left(\frac{F^{″}\left(r\right)}{F^{\prime }\left(r\right)}\times \frac{1}{r}\right)}^{1/2}dr\mathrm{and}{S}_{\theta }\left(r\right)={\lambda }_{\theta }\int {\left(P^{″}\left(r\right)\times \frac{1}{r}\right)}^{1/2}dr.& \left(13\right)\end{array}$ λ_ρ and λ_θ are chosen such that S_ρ(V)=V and S_θ({tilde over (V)})={tilde over (V)}. S_ρ and S_θ can also be numerically approximated.

2. WCDMA Transmitter Linearization Budget Analysis

The effect of transmitter nonlinearity on the transmitted WCDMA signal will now be described. A tolerable level of transmitter compression may be determined by experimentation based on a novel AM-AM compression model and a measured amplifier AM-PM profile.

A weakly nonlinear amplifier model is used in the description that follows. The AM-PM profile was simulated by curve fitting an actual amplifier's AM-PM curve. The EVM, ACLR1 and ACLR2 were measured as a function of the compression level at 24 dBm. FIGS. 5A, 5B and 5C are plots showing the degradation caused by transmitter compression nonlinearity in a WCDMA transmitter in terms of EVM, ACLR1 and ACLR2, respectively and summarize the results.

3. Predistortion Calibration

Conventionally, factory predistortion calibration is employed to obtain the nominal behavior of the one or more amplifiers in the transmitter, which can then be used to construct nominal AM-AM and AM-PM predistortion LUTs. Predistortion calibration calls for a ramping signal or a training signal of another profile to be injected into the transmitter that covers the entire expected range of the amplifier input. The ramping signal typically has the same number of steps as the size of the predistortion LUT. Each step typically is of sufficient duration to allow the transmitter and receiver to settle. The transmitted and received data are then used to construct the calibrated predistortion LUTs.

Predistortion calibration also provides valuable information for predistortion compensation. For example, from the measurement data, the order of the polynomial that is adequate for representing the nominal nonlinearity of one or a combination of amplifiers can be determined. Calibrating under varying operating conditions yields a better estimate of the order of the compensation polynomial to be used for incremental predistortion changes due to temperature, frequency, voltage and VSWR.

4. Adaptive Predistortion

An adaptive predistorter suitable for use with a 3G WCDMA transmitter will now be described. FIGS. 6A and 6B are block diagrams of an adaptive indirect closed loop predistorter in a polar 3G WCDMA transmitter and a Cartesian 3G WCDMA transmitter, respectively.

In FIG. 6A, a digital baseband processor TXIQ produces in-phase and quadrature components I and Q. A signal processor 605 conditions I and Q for amplification. A COrdinate Rotation DIgital Computer (CORDIC) 610 rotates I and Q to yield amplitude and phase components ρ and θ. First polar predistortion LUTs 140 (having four LUTs—two calibration LUTs and two compensation LUTs—in the illustrated embodiment) are employed as they were in FIG. 2 to produce predistorted amplitude and phase components ρ_a and θ_a. θ_a is provided to a local oscillator (LO) phase-locked loop (PLL) 160, which drives a digitally controlled oscillator (DCO) 165. Dividers and buffers 630 receive, divide and delay differential I and Q clock signals, which are used to drive the PPA 170. ρ_a is provided to the amplitude signal processor 175, which the PPA 170 amplifies. The PA, which FIG. 6A does not show, yields the WCDMA output signal (ν_o of FIG. 2). ρ_a and θ_a are also provided to a decimator and aligner 645 to be used in temperature adaptation, which will now be described.

A coupler (not referenced) provides a portion of ν_o to the input of an auxiliary receiver. The auxiliary receiver employs a low-noise amplifier (LNA) 650 to yield in-phase and quadrature components I and Q of ν_o, which are downconverted, converted to digital form and filtered as shown and then rotated by another CORDIC 655 into amplitude and phase components ρ and θ. Second polar predistortion LUTs 660 (having four LUTs—two calibration LUTs and two compensation LUTs—in the illustrated embodiment) predistort ρ and θ to yield amplitude and phase components. The differences between these amplitude and phase components and those provided via the decimator and aligner 645 are provided to a predistortion adapter 665 which updates predistortion in the compensation LUTs of the second polar predistortion LUTs 660. The second polar predistortion LUTs 660 are then exchanged with the first polar predistortion LUTs 140 for the next lookup. The first polar predistortion LUTs 660 are updated during that next lookup, the first and second polar predistortion LUTs 140, 660 are exchanged again for the lookup after that, and so on.

In FIG. 6B, the digital baseband processor TXIQ again produces in-phase and quadrature components I and Q. The signal processor 605 again conditions I and Q for amplification. Cartesian predistortion LUTs 610 (having four LUTs—two calibration LUTs and two compensation LUTs—in the illustrated embodiment) are employed to produce predistorted amplitude and phase components I_a and Q_a. I_a and Q_a are converted to analog form, filtered and modulated as shown and provided to the PPA 635, yielding the WCDMA output signal, ν_o. I_a and Q_a are also provided to the decimator and aligner 645 to be used in temperature adaptation.

A coupler (not referenced) provides a portion of the WCDMA output signal to the input of an auxiliary receiver. The auxiliary receiver employs the LNA 650 to yield in-phase and quadrature components I and Q of the WCDMA output signal, which are downconverted, converted to digital form and filtered as shown. Second Cartesian predistortion LUTs 660 (having four LUTs—two calibration LUTs and two compensation LUTs—in the illustrated embodiment) predistort I and Q. The differences between these amplitude and phase components and those provided via the decimator and aligner 645 are provided to a predistortion adapter 665 which updates predistortion in the compensation LUTs of the second Cartesian predistortion LUTs 660. The second Cartesian predistortion LUTs 660 are then exchanged with the first Cartesian predistortion LUTs 140 for the next lookup. The first Cartesian predistortion LUTs 660 are updated during that next lookup, the first and second Cartesian predistortion LUTs 140, 660 are exchanged again for the lookup after that, and so on.

FIGS. 6C and 6D are block diagrams respectively showing direct-mapping predistortion and complex gain predistortion. In FIG. 6B, predistortion may be carried out using either direct-mapping predistortion or complex gain predistortion.

In both FIGS. 6A and 6B, the predistorter employs an auxiliary receiver that feeds back a portion of the transmitted WCDMA signal. The predistorter includes a static correction calibrated for nominal temperature operation and an adaptive compensation that tracks the characteristics variations due to temperature fluctuations. Both the calibrated and compensated portions of the predistorter are implemented using LUTs.

5. Predistortion Implementation Details

Architectural details of one embodiment of a predistorter will now be set forth, including the effects of LUT size, spacing and interpolation order. For purposes of the discussion, although linear spacing and other nonlinear spacing, e.g., A-law, are within the scope of the invention, nonlinear μ-law spacing will be adopted as the LUT spacing technique. Also, second-order interpolation will be assumed, although other orders of interpolation are within the scope of the invention.

5.2. LUT Size/Spacing Selection

The required LUT size for acceptable predistorter performance across all power levels depends on the spacing of the LUT as well as the interpolation order. Only first-order interpolation will be described in this section, with the understanding that interpolations of all order are within the scope of the invention. The effect of LUT interpolation order is described in Section 5.1, below. Uniform spacing results in poor performance at low power levels for reasonably sized LUT.

Nonuniform spacing can be achieved by using a companding function which maps uniformly spaced entries {tilde over (r)}_k to a set of adequately spaced entries r_k. This is illustrated in FIG. 7, which includes an amplifier 710 as its nonlinear element.

Assuming that the input amplitude is normalized to one, the uniformly spaced entries for LUT of size L are given by:

$\begin{array}{cc}\begin{array}{cc}{\tilde{r}}_k=\frac{k}{L-1}& k\in \left\{0,1,\dots ,L-1\right\}\end{array}& \left(14\right)\end{array}$ The corresponding nonuniformly spaced entries are r_k=S⁻¹({tilde over (r)}_k).

For a given companding function S(r) the width of the k^th LUT interval is given by:

$\begin{array}{cc}\begin{array}{cc}{d}_k\approx \frac{1}{L\times S^{\prime }\left(r_k\right)}& k\in \left\{0,1,\dots ,L-1\right\}\end{array}& \left(15\right)\end{array}$

The theoretically optimal companding function that yields constant SNR across all power level depends on the transmitter's nonlinearity as well as the modulated signal's statistics. If an interpolated LUT of size 128 or greater is used, this optimal can be approached by using μ-law spacing or power spacing.

μ-Law Spacing:

Equation (16) gives the companding function for μ-law spacing:

$\begin{array}{cc}S\left(r\right)=\frac{\ln \left(1+\mu \times r\right)}{\ln \left(1+\mu \right)}& \left(16\right)\end{array}$

The parameter μ can be adjusted for the desired dynamic range. For WCDMA, a value of 32 was chosen. The width of the k^th LUT interval is given by:

$\begin{array}{cc}\begin{array}{c}{d}_k=\frac{1}{L\times S^{\prime }\left(r_k\right)}\\ =\frac{\ln \left(1+\mu \right)}{L}\left(1+\mu \times r_k\right)\\ =\frac{\ln \left(1+\mu \right)}{L}{\left(1+\mu \right)}^{k/L-1}.\end{array}& \left(17\right)\end{array}$ From Equation (17), it is apparent that bin width increases linearly with respect to the amplitude and exponentially with respect to the bin index k.

Power Spacing:

Equation (16) gives the companding function for power spacing:S(r)=r^p  (18)

The parameter p should be chosen between ½ and ¼. The resulting bin widths can be calculated as shown above.

For p=½ the bin width is given by:

$\begin{array}{cc}{d}_k=\frac{2k}{L\left(L-1\right)}& \left(19\right)\end{array}$ In this case, the bin width increases linearly with respect to the bin index k. It is noted that:

$\begin{array}{cc}\sum _{K=1}^{L-1}{d}_k=1& \left(20\right)\end{array}$ The μ-law spacing and power spacing result in similar predistorter performance. Different embodiments are appropriate to different applications and different complexities.

FIGS. 8A and 8B are plots showing the effect of LUT size and spacing on EVM using uniform and μ-law spacing, respectively. FIGS. 9A and 9B are plots showing the effect of LUT size and spacing on ACLR1 using uniform and μ-law spacing, respectively. FIGS. 10A and 11B are plots showing the effect of LUT size and spacing on ACLR2 using uniform and μ-law spacing, respectively. The power spacing is compared to uniform for three LUT sizes (64, 128 and 256). The transmitter's output power is varied from −20 dBm to 24 dBm. A 128-entry LUT predistorter with power spacing effectively mitigates transmitter nonlinear effects even at very low output power. A larger size (e.g., 1024) may be required for a uniformly spaced LUT predistorter at output power lower than −40 dBm.

5.3. Nonuniform, Base-2 LUT Spacing

μ-law spacing results in good predistorter performance across all power levels. In some applications, however, the computational complexity of its LUT address calculation (particularly calculating the logarithm) precludes its use. An alternative, lower complexity spacing technique will now be described. This spacing technique is designed to: (1) approach the performance of constant SNR spacing closely, (2) allow relatively fast address calculation and (3) simplify linear interpolation.

For an LUT size L, the proposed spacing divides the signal range into N intervals of exponentially increasing width. The base-2 exponential is chosen for implementation efficiency. Let W_k be the width of the k^th interval with k={0, 1, . . . , N−1}.W_k=α×2^k  (21)

Each interval contains exactly M uniformly spaced entries, viz.,

$M=\frac{L}{N}.$ L, M and N should be powers of two, but do not need to be. In one example, the best performance across power levels has been achieved with N=8 and M=16 for an LUT size of L=128.

The amplitude signal's resolution should be at least N+log₂(M)−1 bits. Therefore for L=128 and N=8 the amplitude's resolution should be at least 11 bits. This new spacing technique will designated as the base-2 spacing in the following.

5.3.1. Example Implementation of Base-2 Spacing

For purposes of this discussion, an amplitude resolution of 12 bits will be considered. The binary representation of the amplitude signal is (b₁₁b₁₀b₉b₈b₇b₆b₅b₄b₃b₂b₁b₀). The LUT is addressed by log₂(N)=7 bits (a₆a₅a₄a₃a₂a₁a₀). The objective is to map the amplitude bits b_k nonlinearly to the address bits a_k.

The position of the most significant nonzero bit (if any) among the N−1=7 left-most bits determines one of the N=8 intervals. The interval number determines the first log₂(N)=3 bits of the LUT address (a₆a₅a₄). The remaining address-bits (a₃a₂a₁a₀) are equal to the log₂(M)=4 amplitude bits immediately following the most significant nonzero bit among the seven left-most bits. If the first seven bits are all equal to zero, then (a₃a₂a₁a₀)=(b₄b₃b₂b₁), and the corresponding interval number is 0: (a₆a₅a₄)=“000.” It should be noted that the first two intervals are of equal width. FIG. 11 is schematic diagram graphically illustrating one embodiment of an LUT entry address calculation technique.

Table 1, below, shows amplitude entries and bin widths for each interval.

TABLE 1
LUT Amplitude Entries
Interval	Amplitude Entries	Bin Width
0	0, 2, 4, 6, . . . , 30	2
1	32, 34, 36, 38, . . . , 62	2
2	64, 68, 72, 76, . . . , 124	4
3	128, 136, 144, 152, . . . , 248	8
4	256, 272, 288, 304, . . . , 496	16
5	512, 544, 576, 608, . . . , 992	32
6	1024, 1088, 1152, 1216, . . . , 1984	64
7	2048, 2176, 2304, 2432, . . . , 3968	128

In the embodiment of Table 1, the spacing between two consecutive entries is a power of two. This facilitates linear interpolation. The calculated address corresponds to the LUT entry immediately below (or equal to) the amplitude value. The LUT address, bin width and interpolation offset can be calculated in a single clock cycle using elementary logic gates. FIG. 12 is a schematic diagram of one embodiment of an address calculation circuit employing elementary logic gates, and FIG. 13 is a schematic diagram of one embodiment of an interpolation offset calculation circuit, also employing elementary logic gates. The operation of these circuits will now be described.

5.3.1.1. Address Calculation in Base-2 Spacing

The LUT address is calculated by deriving a nonlinear mapping between the amplitude bits b_k and address bits a_k. Table 2, below, shows the truth table for this calculation.

TABLE 2

LUT Address Calculation

b11

b10

b9

b8

b7

b6

b5

b4

b3

b2

b1

b0

a0

a0

a0

a0

a0

a0

a0

1

X

X

X

X

X

X

x

x

x

x

x

1

1

1

b10

b9

b8

b7

0

1

X

X

X

X

X

x

x

x

x

x

1

1

0

b9

b8

b7

b6

0

0

1

X

X

X

X

x

x

x

x

x

1

0

1

b8

b7

b6

b5

0

0

0

1

X

X

X

x

x

x

x

x

1

0

0

b7

b6

b5

b4

0

0

0

0

1

X

X

x

x

x

x

x

0

1

1

b6

b5

b4

b3

0

0

0

0

0

1

x

x

x

x

x

x

0

1

0

b5

b4

b3

b2

0

0

0

0

0

0

1

x

x

x

x

x

0

0

1

b4

b3

b2

b1

The address calculation circuit of FIG. 12, which implements the truth table of Table 2, contains 81 elementary gates: 34 OR gates, 40 AND gates and 7 NOT gates.

5.3.2. LUT Interpolation in Base-2 Spacing

The address calculation unit selects the LUT entry (at address n, denoted LUT[n]) immediately below the input amplitude (or exactly equal to it). In the illustrated embodiment, only the interpolation offset, Offset, and bin width, BinWidth, are required for LUT interpolation. In an alternative embodiment, the interpolation factor (which is the ratio of offset to the bin width) is directly computed. The offset is the difference between the input amplitude, Amplitude, and the LUT entry at address n(Offset=Amplitude−LUT[n]). The interpolated LUT output is given by:

$\begin{array}{cc}\mathrm{LUT}\left[n\right]+\frac{\mathrm{Offset}}{\mathrm{BinWidth}}\times \left(\mathrm{LUT}\left[n+1\right]-\mathrm{LUT}\left[n\right]\right)& \left(22\right)\end{array}$ In the embodiment of Table 1, the bin width is always a power of two, which simplifies the calculation.

The bin width and offset can be calculated from the input amplitude bits and intermediate signals c_k. Only a few elementary logic gates are required. The LUT address, offset and bin width can be calculate during the same clock cycle.

Bin width calculation is straightforward. Bin width can be computed from the intermediate signals c₇c₆ . . . c₀ used in FIG. 12 for address calculation. The bin width varies between two and 128 and can therefore be redescribed with eight bits d₇d₆ . . . d₀, viz.: d₇=c₇, d₆=c₆, d₅=c₅, d₄=c₄, d₃=c₃, d₂=c₂, d₁=c₁+c₀, d₀=0. All the bits d_k are readily available from the address calculation circuit of FIG. 12, so no additional gates or other hardware is required.

5.3.2.1. Interpolation Offset Calculation in Base-2 Spacing

The interpolation offset varies between 0 and 127, requiring seven bits (w₆w₅ . . . w₀). The interpolation offset can easily be calculated from the amplitude bits and intermediate signals c₇c₆ . . . c₂. FIG. 13 shows an example circuit for calculating the interpolation offset using elementary logic gates.

5.4. Modified Base-2 Spacing

A slightly modified base-2 spacing technique may be used to improve the performance of the WCDMA transmitter below −40 dBm, as FIGS. 15A, 15B and 15C indicate may be desirable. The original goal was to satisfy specifications with a 128-entry LUT by moving additional entries from higher amplitudes to lower amplitude. To meet this end, the number of base-2 intervals is increased to ten, and the 13 most significant bits of the amplitude are used to compute the LUT address. The obtained logical structure is a little less “uniform,” but achieves a significant performance improvement between −40 dB and −70 dB as FIGS. 16A, 16B and 16C show, at the cost of slightly decreased performance at highest power levels. The results are summarized below.

5.4.1. Example implementation of Modified Base-2 Spacing

The dynamic range covered by the LUT can be increasing the number of intervals and varying the number of entries per interval. In the following example, a 16-bit digital amplitude word (b₁₅ . . . b₀) is considered. The LUT size is still set at 128 entries. The number of intervals is set to 13. The first three intervals contain 16 entries each, and the remaining ten intervals contain eight entries each.

5.4.1.1. Address Calculation in Modified Base-2 Spacing

Table 3, below, sets how address bits (a₆a₅a₄a₃a₂a₁a₀) may be determined.

TABLE 3
LUT Address Calculation
b15	b14	b13	b12	b11	b10	b9	b8	b7	b6	b5	b4	b3	b2	b1	b0	a6	a5	a4	a3	a2	a1	a0
1	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	1	1	1	b14	b13	b12	b11
0	1	X	X	X	X	X	X	X	X	X	X	X	X	X	X	1	1	0	b13	b12	b11	b10
0	0	1	X	X	X	X	X	X	X	X	X	X	X	X	X	1	0	1	b12	b11	b10	b9
0	0	0	1	X	X	X	X	X	X	X	X	X	X	X	X	1	0	0	1	b11	b10	b9
0	0	0	0	1	X	X	X	X	X	X	X	X	X	X	X	1	0	0	0	b10	b9	b8
0	0	0	0	0	1	X	X	X	X	X	X	X	X	X	X	0	1	1	1	b9	b8	b7
0	0	0	0	0	0	1	X	X	X	X	X	X	X	X	X	0	1	1	0	b8	b7	b6
0	0	0	0	0	0	0	1	X	X	X	X	X	X	X	X	0	1	0	1	b7	b6	b5
0	0	0	0	0	0	0	0	1	X	X	X	X	X	X	X	0	1	0	0	b6	b5	b4
0	0	0	0	0	0	0	0	0	1	X	X	X	X	X	X	0	0	1	1	b5	b4	b3
0	0	0	0	0	0	0	0	0	0	1	X	X	X	X	X	0	0	1	0	b4	b3	b2
0	0	0	0	0	0	0	0	0	0	0	1	X	X	X	X	0	0	0	1	b3	b2	b1
0	0	0	0	0	0	0	0	0	0	0	0	X	X	X	X	0	0	0	0	b3	b2	b1

5.4.1.2. Bin Width Calculation in Modified Base-2 Spacing

The bin width varies from 8 to 211. Table 4, below, sets forth how the 12 bits of the bin width d₁₁ d₁₀ . . . d₀ may be determined. The least-significant bits (LSBs) always equal zero.

TABLE 4
LUT Bin Width Calculation
b15	b14	b13	b12	b11	b10	b9	b8	b7	b6	b5	b4	b3	b2	b1	b0	d11	d10	d9	d8	d7	d6	d5	d4	d3	d2	d1	d0
1	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	1	0	0	0	0	0	0	0	0	0	0	0
0	1	X	X	X	X	X	X	X	X	X	X	X	X	X	X	0	1	0	0	0	0	0	0	0	0	0	0
0	0	1	X	X	X	X	X	X	X	X	X	X	X	X	X	0	0	1	0	0	0	0	0	0	0	0	0
0	0	0	1	X	X	X	X	X	X	X	X	X	X	X	X	0	0	1	0	0	0	0	0	0	0	0	0
0	0	0	0	1	X	X	X	X	X	X	X	X	X	X	X	0	0	0	1	0	0	0	0	0	0	0	0
0	0	0	0	0	1	X	X	X	X	X	X	X	X	X	X	0	0	0	0	1	0	0	0	0	0	0	0
0	0	0	0	0	0	1	X	X	X	X	X	X	X	X	X	0	0	0	0	0	1	0	0	0	0	0	0
0	0	0	0	0	0	0	1	X	X	X	X	X	X	X	X	0	0	0	0	0	0	1	0	0	0	0	0
0	0	0	0	0	0	0	0	1	X	X	X	X	X	X	X	0	0	0	0	0	0	0	1	0	0	0	0
0	0	0	0	0	0	0	0	0	1	X	X	X	X	X	X	0	0	0	0	0	0	0	0	1	0	0	0

5.4.1.3. Interpolation Offset in Modified Base-2 Spacing

Table 5, below, sets forth how the 11 bits of the interpolation offset w₁₀ w₉ . . . w₀ may be determined.

TABLE 5
LUT Interpolation Offset Calculation
b15	b14	b13	b12	b11	b10	b9	b8	b7	b6	b5	b4	b3	b2	b1	b0	w10	w9	w8	w7	w6	w5	w4	w3	w2	w1	w0
1	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	b10	b9	b8	b7	b6	b5	b4	b3	b2	b1	b0
0	1	X	X	X	X	X	X	X	X	X	X	X	X	X	X	0	b9	b8	b7	b6	b5	b4	b3	b2	b1	b0
0	0	1	X	X	X	X	X	X	X	X	X	X	X	X	X	0	0	b8	b7	b6	b5	b4	b3	b2	b1	b0
0	0	0	1	X	X	X	X	X	X	X	X	X	X	X	X	0	0	b8	b7	b6	b5	b4	b3	b2	b1	b0
0	0	0	0	1	X	X	X	X	X	X	X	X	X	X	X	0	0	0	b7	b6	b5	b4	b3	b2	b1	b0
0	0	0	0	0	1	X	X	X	X	X	X	X	X	X	X	0	0	0	0	b6	b5	b4	b3	b2	b1	b0
0	0	0	0	0	0	1	X	X	X	X	X	X	X	X	X	0	0	0	0	0	b5	b4	b3	b2	b1	b0
0	0	0	0	0	0	0	1	X	X	X	X	X	X	X	X	0	0	0	0	0	0	b4	b3	b2	b1	b0
0	0	0	0	0	0	0	0	1	X	X	X	X	X	X	X	0	0	0	0	0	0	0	b3	b2	b1	b0
0	0	0	0	0	0	0	0	0	1	X	X	X	X	X	X	0	0	0	0	0	0	0	0	b2	b1	b0
0	0	0	0	0	0	0	0	0	0	1	X	X	X	X	X	0	0	0	0	0	0	0	0	0	b1	b0
0	0	0	0	0	0	0	0	0	0	0	1	X	X	X	X	0	0	0	0	0	0	0	0	0	0	b0
0	0	0	0	0	0	0	0	0	0	0	0	X	X	X	X	0	0	0	0	0	0	0	0	0	0	b0

6. LUT Mapping for Improved Accuracy Under Large Signal Dynamic Range

For signals with large dynamic range, such as a WCDMA amplitude (which has a dynamic range in excess of 110 dB), managing the LUT mapping quantization floor is a daunting task. In this section, only LUTs that use nonlinear spacing for the index lookup process described above will be considered. Linear spacing falls within the scope of the invention, but will not be considered here due to its relatively inferior performance for the input signal dynamic range. The only explored quantity is the number of bits used for each LUT entry, which defines the dynamic range of the LUT output.

6.1 Direct Mapping

FIGS. 17A and 17B are high-level schematic diagrams showing direct mapping and inverse gain mapping, respectively. The LUT in FIG. 17A is a direct-mapped LUT 1710, and the LUT in FIG. 17B is an inverse-gain-mapped LUT 1720.

Brute force, i.e., use of a linear direct mapping as shown in FIG. 17A, results in degraded performance. If ƒ(•) is the nonlinear mapping that is desired in the LUT, and n bits are assumed to be used for each LUT entry, a quantized mapping {tilde over (ƒ)} results:{tilde over (ƒ)}=ƒ+e_q,  (23)where e_q is the mapping quantization introduced. Consequently, the quantized LUT output signal is related to the unquantized output signal by:{tilde over (ρ)}_pred=ρ_pred+e_q.  (24)This results in an output SNR of:

$\begin{array}{cc}\mathrm{SNR}\left(\rho \right)\approx \frac{{\rho }^2}{{\sigma }_q^2}.& \left(25\right)\end{array}$ Clearly the SNR degrades as the amplitude of the signal ρ decreases.

6.2. Inverse Gain Mapping

An alternate to counter the above reduced SNR is to use an inverse gain mapping function g(•), such that the desired LUT mapping ƒ(•) is realized as:ƒ(ρ_in)=ρ_in×g(ρ_in)=ρ_pred.  (26)

In this case the quantization in the LUT output is due to the finite number of bits used for the inverse gain LUT g(•), i.e.:{tilde over (g)}=g+e_q.  (27)The LUT output signal can now be expressed as:{tilde over (ρ)}_pred=ρ_pred+ρ_ine_q  (28)The SNR of this LUT output signal now becomes:

$\begin{array}{cc}\mathrm{SNR}\left(\rho \right)\approx \frac{{g\left(\rho \right)}^2}{{\sigma }_q^2}& \left(29\right)\end{array}$ which is almost constant across its entire range.

The LUT step size as a function of input 10-bit LUT code is graphically shown in FIGS. 18A and 18B.

6.3. Other Approaches

The output signal dynamic range can also be improved using a fixed bit-width floating point (i.e., mantissa, exponent format). However, use of such a format complicates the interpolation computation between successive LUT entries and therefore has not been pursued in this work.

6.4. Simulated Performance

A simulated comparison of the LUT output SNR impact on the WCDMA transmitter performance has been carried out. It is observed that across the >90 dB power dynamic range of the LUT, while direct mapping architecture requires 19 bits, the inverse gain LUT approach requires only ten bits for comparative performance. The results have been summarized in FIGS. 19A, 19B, 20A, 20B, 21A and 21B.

FIG. 22 is a flow diagram of one embodiment of a method of addressing a large-dynamic-range LUT carried out according to the principles of the invention. The method begins in a start step 2210. In a step 2220, an input signal is companded based on a nonlinearity of the nonlinear element to address uniformly spaced entries contained in a LUT. The companding may be μ-law companding. In a step 2230, an output is produced from the LUT based on a linear interpolation involving a value of the input signal and at least two of the entries. In a step 2240, the nonlinear element is caused to produce an output signal having a substantially constant signal-to-noise ratio over an amplitude range of interest. The method ends in an end step 2250.

FIG. 23 is a flow diagram of another embodiment of a method of addressing a large-dynamic-range LUT carried out according to the principles of the invention. The method begins in a start step 2310. In a step 2320, addresses are calculated for base-2-spaced entries in a LUT based on a mapping between an amplitude of an input signal and bits of the addresses. In a step 2330, an interpolated output is produced based on a bin width and an offset derived from the input signal. The step 2330 may include employing a 13 most significant bits of the amplitude to calculate the addresses. The method ends in an end step 2340.

Those skilled in the art to which the invention relates will appreciate that other and further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the scope of the invention.

Claims

1. A predistorter for use with a nonlinear element, comprising: a lookup table having non-uniformly spaced entries therein;a compander configured to compand an input signal based on a nonlinearity of said nonlinear element to address said entries; andan interpolation offset calculation circuit associated with said lookup table and configured to produce an output based on a value of said input signal and a linear interpolation involving at least two entries from said lookup table.

2. The predistorter as recited in claim 1 wherein addressing of said entries is based on amplitude of said input signal.

3. The predistorter as recited in claim 1 wherein values of said entries contain at least one selected from the group consisting of: an output amplitude,a phase,a real gain, anda complex gain for at least one modulation signal.

4. The predistorter as recited in claim 1 wherein said predistorter causes said nonlinear element to produce an output signal having a substantially constant signal-to-noise ratio over an amplitude range of interest.

5. The predistorter as recited in claim 1 wherein said lookup table is an inverse-gain-mapped lookup table.

6. A predistorter for use with a nonlinear element, comprising: a lookup table having non-uniformly spaced entries therein;a compander configured to compand an input signal based on a nonlinearity of said nonlinear element to address said entries, wherein said compander is configured to employ a metric based on a constant signal signal-to-noise ratio (SNR) to compand said input signal; andan interpolation offset calculation circuit associated with said lookup table and configured to produce an output based on a value of said input signal and a linear interpolation involving at least two entries from said lookup table.

7. A predistorter for use with a nonlinear element, comprising: a lookup table having non-uniformly spaced entries therein;a compander configured to compand an input signal based on a nonlinearity of said nonlinear element to address said entries, wherein said nonlinear element is an amplifier contained in a WCDMA transmitter; andan interpolation offset calculation circuit associated with said lookup table and configured to produce an output based on a value of said input signal and a linear interpolation involving at least two entries from said lookup table.

8. A method of predistorting for a nonlinear element, comprising: companding an input signal based on a nonlinearity of said nonlinear element to address non-uniformly spaced entries contained in a lookup table; andproducing an output from said lookup table based on a linear interpolation involving a value of said input signal and at least two of said entries.

9. The method as recited in claim 8 wherein said entries are based on amplitude of said input signal.

10. The method as recited in claim 8 wherein values of said entries contain at least one selected from the group consisting of: an output amplitude,a phase,a real gain, anda complex gain for at least one modulation signal.

11. The method as recited in claim 8 further comprising causing said nonlinear element to produce an output signal having a substantially constant signal-to-noise ratio over an amplitude range of interest.

12. The method, as recited in claim 8 wherein said lookup table is an inverse-gain-mapped lookup table.

13. A method of predistorting for a nonlinear element, comprising: companding an input signal based on a nonlinearity of said nonlinear element to address non-uniformly spaced entries contained in a lookup table; andproducing an output from said lookup table based on a linear interpolation involving a value of said input signal and at least two of said entries, wherein said producing comprises employing a metric based on a constant signal signal-to-noise ratio (SNR) for said companding.

14. A method of predistorting for a nonlinear element, comprising: companding an input signal based on a nonlinearity of said nonlinear element to address non-uniformly spaced entries contained in a lookup table, wherein said nonlinear element is an amplifier contained in a WCDMA transmitter; andproducing an output from said lookup table based on a linear interpolation involving a value of said input signal and at least two of said entries.

15. A predistorter for use with a nonlinear element, comprising: a lookup table containing base-2-spaced entries;an address calculation block associated with said lookup table and configured to calculate addresses for said entries based on a mapping between an amplitude of an input signal and bits of said addresses; andan interpolation circuit associated with said lookup table and configured to produce a selected one of an interpolation factor and an interpolated output based on a bin width and an offset derived from said input signal.

16. The predistorter as recited in claim 15 wherein said bin width is a power of two.

17. The predistorter as recited in claim 15 wherein intervals in said lookup table is at least ten and said address calculation block employs a 13 most significant bits of said amplitude to calculate said addresses.

18. The predistorter as recited in claim 15 wherein said lookup table is an inverse-gain-mapped lookup table.

19. The predistorter as recited in claim 15 wherein intervals in said lookup table contain different numbers of entries.

20. A method of predistorting for a nonlinear element, comprising: companding an input signal based on a nonlinearity of said nonlinear element to address non-uniformly spaced entries contained in a lookup table, wherein said nonlinear element is an amplifier in a WCDMA transmitter; andproducing an output from said lookup table based on a linear interpolation involving a value of said input signal and at least two of said entries.

21. A method of predistorting for a nonlinear element, comprising: calculating addresses for base-2-spaced entries in a lookup table based on a mapping between an amplitude of an input signal and bits of said addresses; andproducing a selected one of an interpolation factor and an interpolated output based on a bin width and an offset derived from said input signal.

22. The method as recited in claim 21 wherein said bin width is a power of two.

23. The method as recited in claim 21 wherein at least ten of said intervals are in said lookup table and said producing comprises employing a 13 most significant bits of said amplitude to calculate said addresses.

24. The method as recited in claim 21 wherein said lookup table is an inverse-gain-mapped lookup table.

25. The method as recited in claim 21 wherein intervals in said lookup table contain different numbers of entries.

26. A method of predistorting for a nonlinear element, comprising: calculating addresses for base-2-spaced entries in a lookup table based on a mapping between an amplitude of an input signal and bits of said addresses; andproducing a selected one of an interpolation factor and an interpolated output based on a bin width and an offset derived from said input signal, wherein said nonlinear element is an amplifier in a WCDMA transmitter.

27. A predistorter for use with a nonlinear element, comprising: a lookup table having non-uniformly spaced entries therein;a compander configured to compand an input signal based on a nonlinearity of said nonlinear element to address said entries, wherein said nonlinear element is an amplifier; andan interpolation offset calculation circuit associated with said lookup table and configured to produce an output based on a value of said input signal and a linear interpolation involving at least two entries from said lookup table.

28. A method of predistorting for a nonlinear element, comprising; companding an input signal based on a nonlinearity of said nonlinear element to address non-uniformly spaced entries contained in a lookup table, wherein said nonlinear element is an amplifier; andproducing an output from said lookup table based on a linear interpolation involving a value of said input signal and at least two of said entries.

29. A method of predistorting for a nonlinear element, comprising: calculating addresses for base-2-spaced entries in a lookup table based on a mapping between an amplitude of an input signal and bits of said addresses; andproducing a selected one of an interpolation factor and an interpolated output based on a bin width and an offset derived from said input signal, wherein said nonlinear element is an amplifier.