Large scale integrated circuit with sense amplifier circuits for low voltage operation

Abstract

Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which serves to a fixed internal voltage for a wide range of power supply voltage, an input/output buffer which can be adapted to several input/output levels, a dynamid RAM(s) which can operate at a power supply voltage of 2 V or less, etc. This one-chip ULSI can be applied to compact and portable electronic devices such as a lap-top type personal computer, an electronic pocket note book, a solid-state camera, etc.

Description

BACKGROUND OF THE INVENTION

The present invention relates to a large scale integrated circuit, and more particularly to a high-density integrated semiconductor device constituted by a voltage converter circuit and miniaturized devices (devices with small dimension) which can keep up with a wide range of an operating power-supply voltage and kinds of power supplies, i.e. a large scale integrated circuit in which integrated on a monolithic chip are a microcomputer, a logic circuit, a dynamic RAM (random access memory), a static RAM, a ROM (read-only memory), etc.

In recent years, onto the market have come portable electronic machines such as a lap-top type personal computer, an electronic pocket notebook, etc., and portable electronic media machines such as a solid-state voice recorder which performs voice recording without using a magnetic medium, a solid-state camera (electronic still camera) which performs image recording without using the magnetic medium. In order for these portable electronic machines to be widely popularized, it is indispensable to realize an ultra large scale integrated circuit (ULSI) which permits a battery based operation or an information (data) retention operation using a battery (battery back-up). On the other hand, there has been increased demand for a semiconductor disk, which can provide higher speed accessing than a magnetic disk, as a large-capacity-file memory system for implementing a computer with higher performance. And this semiconductor disk requires a very large-capacity memory LSI which can perform the information using a battery.

The ULSIs used for these applications must satisfy the following requirements.

(1) The operation in a wide range of operating power supply voltage (1-5.5 V). This requirement permits one-chip ULSI to be adapted for many kinds of power supplies including, e.g. 5 V which is a standard power supply voltage for the present TTL compatible digital LSI, 3.3 V which is one candidate for the standard power supply voltage for the future TTL reversible digital LSI, 3-3.6 V which is a typical output voltage of a primary cell of lithium, etc., 1.2 V which is a typical output voltage of a secondary cell of cadmium and nickel, and so on.

(2) The measures for a secular change or time-dependent fluctuation (for a short period or long period) in the power supply voltage. This requirement removes fear of operation failure due to voltage fluctuation resulting from the secular change in the cell voltage and the switching of power supply in shifting between the operation under a nominal condition and a battery back-up operation.

(3) The power reduction in the standard operation or the battery back-up operation. This requirement permits a small-sized battery to operate the ULSI for a long period.

(4) The reduction in a switching current. This requirement decreases voltage fluctuation caused by switching in the battery voltage, thus preventing the operation failure.

One example of the product of microprocessor which operates in a wide range of the operating voltage is disclosed in the 4-bit microprocessor handbook, p 148 published by NIPPON DENKI Co., Ltd. The product name is μPD7507SC. The range of the power supply voltage in this microprocessor is 2.2-6.0 V. Information in a data memory (static RAM) is retained with a minimum voltage of 2 V. In this memory, the recommendable voltage is generally 5 V for the operating power supply voltage and for 2 V the data retention.

An example of the dynamic memory for battery back-up in which power consumption in the data retention (refresh) is decreased is disclosed in IEEE, Journal of Solid-State Circuits. Vol. 23, No. 1, pp. 12-18, February 1988. The power supply voltage is 5 V for both nominal operation and data retention.

An example in which an external voltage is dropped to be supplied to an internal circuit is disclosed in U.S. Pat. No. 4,482,985.

An example of the battery back-up for a memory is disclosed in U.S. Pat. No. 4,539,660.

A technique for changing the plate voltage of a dynamic RAM is disclosed in Japanese Patent Publication No. 61-61479.

The battery back-up of a static RAM is disclosed in the catalogue published by Hitachi, Ltd., pp. 44-45.

The other relevant references and patent publications will be identified in the following description.

SUMMARY OF THE INVENTION

The present invention intends to lower the operation voltage of a system provided on a monolithic chip so that the operation speed is not affected by changes in the power supply voltage supplied from the outside.

The present invention has been accomplished by devising voltage converter means which is capable of stably supplying a fixed voltage in a wide range of power-supply voltage. The voltage converter means in the present invention is referred to as means including at least one amplifier which generates an output voltage on the basis of an input reference voltage, and is different from means of only dropping voltage using resistors, etc.

In the present invention, it is also critical to improve a dynamic RAM which is the biggest obstacle against lowering the operation voltage. This is because the dynamic RAM requires a refresh operation even during data retention due to its dynamic operation and so does not permit only the operation voltage during data retention to be lowered unlike the static RAM.

The microprocessor and static RAM as mentioned above have a wide range of the operating power-supply voltage of 2-5 V. However, since they are designed around the power supply voltage of 5 V, the operation speed thereof (the highest clock frequency in the case of the microprocessor and access time in the case of the static RAM) is not assured for the operation outside the recommended fluctuation (generally, +10%) in the power supply voltage. Particularly at a low power supply voltage, it is common that the operation speed is greatly lowered. The dependency of the operation speed on the power-supply voltage is different with the products. Therefore, the operation speed of a system must be designed to accord with the lowest one of the operation speeds of LSIs constituting the system. This made it impossible to provide a necessary performance of the system for the operation outside at 5 V and difficult to design the system for the operation at a low power supply voltage.

These LSIs, the lowest operating power supply voltage of which is 2.2 V, are difficult to adapt to all of many power kinds of power supply voltages as mentioned above, which is a restriction to system design. Further, the dynamic RAM to be incorporated in the system, the lowest operating power supply voltage of which is 4.5 V, are further difficult to adapt to the many kinds of power supply voltages. Particularly, the absence of different between the power supply voltage for normal operation and that for data retention made very complicated the arrangement of a power supply switching circuit, thereby making the data retention difficult.

Meanwhile, with rapid development of miniaturization (scaling down) of semiconductor devices, by using the processing technology lower than 0.5 μm, it is possible to constitute a so-called system LSI in which several LSI blocks are integrated on a monolithic chip. In such a system LSI, it is required that the operating power-supply voltage ranges and operating speeds of the respective LSI blocks are aligned with each other. However, as mentioned above, only combining the conventional LSIs could not constitute such a system LSI.

The present invention can be constituted by an LSI circuit block which has a power down mode suited for battery back-up can operate at a low power supply voltage of about 1 V at the minimum; a power supply voltage converter circuit which supplies an internal power supply voltage suitable to the operating mode to the LSI; and an input/output circuit for converting the signal amplitude.

By operating the main LSI block, which performs storage and processing of information, at a substantially fixed low voltage regardless of the external power supply voltage, it is possible to provide substantially constant operation speed performance over a wide range of the power supply voltage. The external power supply voltage can be reduced to the operation voltage of the LSI block as required so that power consumption during data retention can be reduced to a necessary and minimum value and also a battery back-up circuit can be simplified in its constitution. Further, the optimum operation voltage according to the characteristic of miniaturized devices constituting the main LSI block can be set independently of the external power supply voltage so that performances of high integration degree, high operation speed, and low power consumption can be obtained simultaneously.

An object of the present invention is to provide a large scale integrated circuit (LSI) which can operate at a fixed operation speed against wide range fluctuation of an operating power supply voltage.

Another object of the present invention is to provide voltage converter means which can produce a constant output voltage against wide range fluctuation of the operating power supply voltage.

Still another object of the present invention is to reduce power consumption in an LSI and particularly the power consumption during battery based operation.

Yet another object of the present invention is to prevent operation failure of an LSI which performs a low voltage operation.

A further object of the present invention is to provide an LSI with a plurality of input/output levels.

A further object of the present invention is to provide a dynamic RAM which can perform a low voltage operation.

A further object of the present invention is to improve a sense amplifier used for the dynamic RAM which performs a low voltage, and its operation.

These and other objects and many of the attendant advantages of the present invention will be readily appreciated as the same become better understood by reference the following detailed description when considered in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 19 B are views showing the basic idea of the present invention and embodiments relative to improvement of a voltage converter, etc. used in the present invention;

FIGS. 20A to 36 C are views showing embodiments relative to improvement of an input/output buffer, etc. used in the present invention;

FIGS. 37A to 70 D are views showing embodiments relative to improvement of a dynamic RAM, etc. used in the present invention; and

FIGS. 71A to 78 C are views showing embodiments relative to a sense amplifier, etc. used in the dynamic RAM of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention intends to an LSI which can operate at a wide range of an operating power supply voltage (for example 1 to 5.5 V). The following description discloses four techniques roughly classified:

(1) a voltage converter (limiter) which can produce a stabilized internal power supply voltage even in a wide range of the operating power supply voltage,

(2) an input/output buffer which can be adapted to several input/output levels,

(3) a dynamic RAM which can operate at a power supply voltage of 2 V or less, and

(4) a sense amplifier suited for the dynamic RAM operating at a low voltage and its operation.

These techniques enables one (single) chip LSI to perform a stabilized operation by many kinds of power supplies including a battery (e.g. 1.2 V) to a normal power supply (e.g. 5 V). It is apparent that the following embodiments can be combined and also it can be understood by those skilled in the art that only necessary parts may be adopted without aparting from the spirit of the present invention.

EMBODIMENTS

FIGS. 1A and 1B are block diagrams for explaining the basic idea of an LSI chip in accordance with the present invention. In these figures, numeral 1 is an LSI chip which has functions of data storage and/or data processing. This LSI chip may be in any form of an memory LSI including a dynamic or static RAM, a serial access memory (SAM) and read-only-memory (ROM); a logic LSI including a microprocessor (MPU), a memory management unit (MMU) and a floating point operation unit (FPU); and a system LSI in which a plurality of these LSIs are integrated. The individual devices constituting the LSI chip may be bipolar transistors, metal-insulator-semiconductor (MIS) transistors (generally, metal-oxide-semiconductor (MOS) FET), combination of these devices, or devices or material other than Si e.g. GaAs. Numeral 2 is an exemplary power supply circuit which detects a drop of an external power supply voltage (Vext) to shift the LSI chip into a back-up state by a battery. This power supply circuit serves to prevent data stored in the LSI chip from disappearing even when Vext is lowered due to shut-down of the commercially available power source. In this power supply circuit, numeral 3 is a voltage drop detection circuit for the power supply voltage, SW is a switch for preventing current from flowing the battery to an external power supply terminal during data retention, numeral 4 is a control signal for the switch, B is a battery by which the entire LSI chip operates in the data retention mode (Vbt is its voltage), and D is a diode for preventing current from flowing the external power supply into the battery in the normal operation mode. This power supply circuit applies to a power supply terminal Vext during normal operation and Vbt-0.7 V (0.7 V is voltage drop in the forward direction of the diode D) during data retention. Although the voltage Vext for normal operation is now assumed to be 3.3±0.3 V which is proposed as a future TTL standard power supply voltage, it may be 5 V which is the present TTL standard power supply voltage or the other voltage value. Vbt may be 3 V from the primary cell, 2.4 V from two secondary cells connected in series, etc. In the following example, explanation will be given for the case where Vext varies in the range of 3.3±0.3 V and Vbt varies in the range of 1-2 V.

Numerals 5 a and 5 b are a main circuit block, respectively. Numeral 5 is a collection thereof. Numeral 6 is a power supply power converter circuit block for converting a power supply voltage Vcc supplied from the outside of the LSI chip into internal power supply voltages V CL1 , and V CLn for the respective circuit blocks. In the power supply voltage converter circuit, numerals 6 a and 6 c are a converter circuit for normal operation, respectively, and numerals 6 b and 6 d are a converter circuit for data retention.

In the present invention, the external power supply voltage Vext in a wide range (e.g. 1-5.5 V) so that only one power supply voltage can not cover this wide range. This is because the power supply voltage converter circuits in the present invention serve to produce output voltages (V CL1 , V CL2 ) on the basis of an input reference voltage V L . For this reason, a plurality of the power supply voltage converter circuits are provided.

The power supply voltages for the circuit blocks are produced on the basis of the reference voltage as mentioned above. For this reason, if the external power supply voltage Vext or the battery voltage Vbt becomes equal to the reference voltage V L (or the internal voltage V CL1 -V CL2 ), the operation of the voltage converting circuits become unstable. For such a case, a switch 6 a is provided to connect the external power supply voltage with the circuit blocks 5 a and 5 b.

In an example of the present invention, the internal power supply voltages (e.g. V CL1 , V CL2 ) for the main circuit blocks 5 a and 5 b are adapted to be 1.5 V. In this case, if the external power supply voltage varies in a wide range of 1.5 V to 3.6 V, it is difficult to produce the internal power supply voltage using only one voltage converter. For this reason, a plurality of the voltage converter circuits L 1 and L 1 B are provided. The voltage converter circuit L 1 b mainly serves to convert the power supply voltage of 2.5 to 3.6 V into 1.5 V to be supplied to the main circuit 5 a (C 1 ) and the voltage converter L 1 B mainly serves to convert the power supply voltage 1.5 to 2.5 V to be supplied to the main circuit 5 a. Switching of L 1 and L 1 B is controlled by a data retention state signal PD as described later.

Generally, the operation voltage and current required during data retention may be smaller than during normal operation so that even when the current to be consumed in the voltage converter circuits is reduced to lower the driving capability thereof, any trouble does not occur. This enables the current consumed in the entire LSI chip to be remarkably reduced together with reduction in the power consumption in the main circuit blocks. Incidentally, although in this example, switching is made between two voltage converter circuits, three or more voltage converters may be provided. Also, only one voltage converter circuit may be used to vary its output voltage and power consumption.

As mentioned above, SW 6 a and SW 6 c are a switch for directly apply the power supply voltage Vcc to the circuit blocks when Vcc is decreased to a value substantially equal to V CL1 or V CLW . By using this switch to turn off the voltage converter circuits, the consumed current can be further reduced. Although in the above example, the power supply voltage converter circuit 6 is constituted by a plurality of switches and a plurality of voltage converter circuits, only one voltage converter circuit may be used when viewed in a block form as long as the same effect can be obtained.

Numeral 9 is a circuit for generating the reference voltage V on the basis of which the internal power supply voltage V CL1 or V CL2 is created. Numeral 8 is a circuit for generating a signal PD indicative of the data retention operation state. Although the signal PD can be generated through several techniques, there is here adopted a method of comparing the power supply voltage Vcc with a reference voltage Vcx and producing the signal PD when the former is smaller than the latter. Numeral 10 is a circuit for generating a limiter enable signal LM. If the external power supply voltage is higher than the internal power supply voltage, thereby operating the voltage converter circuit (voltage limiter), LM of a high voltage (“1”) is generated whereas if the external power supply voltage is decreased to a value equal to the internal power supply voltage, LM of a low voltage of (“0”) is generated. In the latter case, the external power supply voltage is directly applied to the main circuit block and also the voltage converter is not operated to restrain power consumption. In the example as shown, when the power supply voltage Vcc is compared with the reference voltage Vcx, and LM is generated if the former is larger than the latter. The output voltage and consumed current of the power supply voltage converter circuit 6 can be changed using the above two signals PD and LM.

Numeral 7 is an input/output buffer circuit; numeral 11 is an input/output bus for transmitting/receiving control signals and data between the inside and the outside of the chip; and numeral 12 is an internal bus which is within the chip and serves to transmit/receive control signals and data. The input/output buffer circuit 7 , which also serves as a voltage level converting circuit, can transmit/receive the control signals and data even if the logic swing in the chip does not coincide with that in the outside. In the data retention operation state, the control signals and data are not required to be transmitted/received between the inside and the outside of the chip so that the input/output buffer circuit 7 is turned off by the data retention state signal PD. Thus, the power consumption can be reduced.

FIG. 1B shows an exemplary concrete constructing of the power supply voltage converter circuit 6 . In this figure, L 1 is constituted by a differential amplifier circuit A OA , and NPN bipolar circuit Q O , and resistors R 01 , R 02 . With R 01 =R 02 , and the input reference voltage V L =0.75, 1.5 V which is twice as large as V L is provided at the output of V CL1 . If the power supply voltage V cc is the voltage converter circuit L 1 is decreased to be V cc <V cL1 +V BE (V BE is a base-emitter voltage of the bipolar transistor Q O which is about 0.7 V), the output voltage V CL1 is decreased. Thus, the voltage converter circuit L 1 operates when V cc is 2.2 V. In the example of FIG. 1B , as a voltage converter circuit operating when V cc is lower than 2.2 V, L 1 B is arranged in parallel to L 1 and at the low voltage of V cc , L 1 is switched into L 1 B. The voltage converter circuit L 1 B is constituted by a differential amplifier circuit A OB , a p-channel MOS transistor T OB , and resistors R 03 , R 04 . Also in this case, with R 03 =R 04 and the input reference voltage V L =0.75 V, 1.5 V is provided at the output voltage of V CL1 . This voltage converter circuit L 1 B uses the p-channel MOS transistor as a device for supplying the power supply current, so that it advantageously operates in the range where V cc is close to V CL1 . However, the voltage converter circuit V 1 a disadvantage that it is necessary to make careful consideration for the phase characteristic of a feedback loop since the voltage gain of the MOS transistor itself is larger than 1, thereby making difficult the designing of the voltage converter circuit. Particularly, in the case where the voltage converter circuit is to be operated in a wide range of the power supply voltage of 1.5 to 3.6 V, it is difficult to design the voltage converter circuit so that it can operate over the entire range of the power supply voltage since the p-channel MOS transistor operates in both saturation region and linear region. In this example, by designing L 1 so that it operates in a narrow range of the power supply voltage of 1.5 to 2.5 V, the operation of L 1 B can be stabilized. In the case where the power supply voltage is 1.5 V or less, it is directly supplied to the internal circuit (circuit block 5 a) by making the switch SW 6 a conductive. Here, a p-channel MOS transistor T OS is used as the switch.

Further, as a value of the input reference voltage V L in the power supply voltage converter circuit, 1.5 V itself which is the internal power supply voltage is not adopted. This is due to the following two reasons:

(1) If the power supply voltage is close to the reference voltage level, the voltage stabilizing characteristic of the reference voltage generating circuit is generally deteriorated, thereby reducing the reference voltage level.

(2) The upper limit of the in-phase input range in the differential amplifier circuit is generally slightly lower than the power supply voltage level. Therefore, in order to sufficiently use the characteristic of the differential amplifier circuit, the input reference voltage is desired to be lower than the power supply voltage (1.5 V at the minimum).

By setting the input reference voltage at a level lower than the minimum value of the power supply voltage, the power supply voltage converter circuit can be stably operated in the range where difference between the external power supply voltage and the internal power supply voltage is small. Incidentally, L 1 and L 1 B are activated by a {overscore (PD)} signal and PD signal, respectively.

Further, in the above example, a bipolar transistor is used in L 1 and a p-channel MOS transistor is used in L 1 B. However, a p-channel MOS may be used for L 1 and L 1 B. Also in this case, since the phase characteristic of the circuits can be individually designed, a more stabilized power supply converter circuit can be provided than the case where only one voltage converter is used. Moreover, by means of the combination of the other devices without being limited to that of the above devices, if the voltage condition adapted for the characteristic of the devices is selected, a power supply voltage converter circuit which can operate in a wide range of the power supply voltage.

By means of such a circuit, it is possible to provide an LSI which can operate with the operation speed (response speed) even when a power supply voltage varies in a wide range. The operation speed can be represented by an access time for a memory and a maximum clock frequency for a microcomputer (CPU). The memory access time includes an address access time which is a time from an address change to data output, a chip select (or chip enable) access time which is a time from input of a chip select (or chip enable) signal to data output and a RAS (or CAS) access time in the case of DRAM which is a time from input of an address strobe signal RAS (or CAS) to data output. As these access times are shorter, the amount of data transfer per unit time can be increased, thereby improving the processing performance of a system. In accordance with the present invention, these operation speeds can be made substantially constant and also elements used in the system can operate at a higher speed than the conventional low voltage operating elements through circuit contrivance and contrivance in element designing (e.g. setting of a threshold voltage) so that the performance of the system can be greatly improved. FIG. 1C shows the RAS access time measured when the present invention is applied to a 64 Mbit DRAM. The abscissa represents an external power supply voltage V cc whereas the ordinate represents a RAS access time. In the case of an output load capacitance of 30 pF, the RAS access time does not almost vary in the range of V cc to the lowest V cc of about 1.5 V. Also, in the case of an output load capacitance of 100 pF, it does not almost vary in the range of the lowest V cc of 2.0 V. Any conventional LSI does not have such a characteristic (also for the other SRAM or microcomputer although FIG. 1C relates to DRAM).

FIG. 2A is a graph showing the relation between the power supply voltage V cc and the internal power supply voltage V CL . In this figure, the abscissa represents the power supply voltage V cc and the ordinate represents the internal power supply voltage V CL . The power supply voltage for normal operation is set at the range of 3 to 3.6 V; the power supply voltage for data retention is set at the range of 1 to 2 V; and the reference voltage V cx for switching between the normal operation and the data retention is set at 2.5 V. However, the other setting values may be adopted under the condition:

V BT (max)<V cx −V cc (min)

where V cc (min) is a minimum value of the power supply voltage for normal operation, V BT (max) is a maximum value of the power supply voltage for data retention, and V cx is the reference voltage. Further, although the internal power supply voltage V cL is set at 1.5 V, it may be set at a suitable value corresponding to the operation characteristic of the circuit within a range not exceeding the power supply voltage V cc . Moreover, in this example, in order to directly supply the power supply voltage V cc which is 1.5 V or less to the internal circuit, V LX is set at 1.5 V.

FIG. 2B shows an example of the secular change (time-dependent fluctuation) of the internal power supply voltage V cL , and two control signals LM and PD in the case where the power supply voltage V cc is changed in time lapse in the LSI chip. Now, consideration is made on the case where V cc is decreased from 3.5 to 1 V in the period of t 1 to t 3 and thereafter is increased from 1 to 3.5 V in the period of t 4 to t 7 . In the period of t 1 to t 6 when V cc is lower than V cx =2.5 V, the signal PD becomes a high voltage state (“1”), thereby placing the chip into the data retention state. In the period of t 2 to t 6 when V cc is lower than V cx , the signal LM becomes a low voltage state (“0”), thereby directly supplying the power supply voltage V cc to the chip. The voltage values identified here are exemplary, and combination of the other voltages may be adapted in the same manner.

FIGS. 2C and 2D show an example of the method of generating the limiter enable signal LM and the circuit configuration therefor, respectively. The signal LM may be shifted from the high voltage state (“1”) to the low voltage state (“0”) at the point where it becomes first equal to the internal power supply voltage V cL when the power supply voltage is decreased. In this example, the voltage×V cc (0≦β≦1) which is proportional to V cc and the reference voltage V L are compared in a comparison circuit. And if the former is larger than the latter, the high voltage (“1”) is generated and if the former is larger than the latter, the low voltage (“1”) is generated. In this way, using the voltage proportional to V cc as an input voltage between the high voltage and the low voltage provides an advantage in circuit operation of e.g. of being capable of taking a large voltage amplification factor of the comparison circuit. For example, with β=0.5 and V L =0.75, V LX =1.5 V. Then, if V cc is 1.5 V or more, the limiter enable signal LM becomes the high voltage state (“1”) thereby operating the power supply voltage converter circuit. Incidentally, the voltage proportional to V cc can be generated using resistors.

FIGS. 2E and 2F show an example of the method of generating the data retention state signal PD and the circuit configuration therefor. This circuit configuration can be constituted in the same manner as the above LM generating circuit. In this case, the voltage α×V cc (0≦α≦1) proportional to V cc is applied to an inverting input terminal. For example, with α=0.5 and V L =0.75 V, V cx =2.5 V. Then, if V cc is 2.5 V or less, the data retention state signal PD becomes the high voltage state (“1”), thereby placing the chip into the data retention state. Incidentally, the voltage proportional to V cc is generated by resistor division of R 1 and R 2 . These resistors may be constituted by any of an impurity diffused layer formed in a semiconductor substrate, poly-silicon and a channel resistor of a MIS-FET.

FIG. 3A shows one embodiment in which the present invention is applied to an LSI locally incorporating a static memory. In this figure, 5 c is a memory cell array of the static memory and 5 d is a circuit block such as a logic circuit which does not require data retention. The power supply voltage required for 5 c and 5 d is V CL2 and V CL1 , respectively. The memory cell array 5 c is constituted by four n-channel MOS-FETs T 6 and T 9 , and two resistor elements R 7 and R 8 . Assuming that the resistance value thereof is R, the current value flowing for one memory cell is V CL2 /R. Therefore, it is desired that the voltage value is made as low as possible within a range of being capable of assuring noise margin. In this embodiment, as shown in FIG. 3B , V CL2 for normal operation is set at 1.5 V and V CL2 for data retention is set at 1 V. The logic block 4 d is constituted by inverters, logic gates, etc. T 11 and T 13 with an arrow are p-channel MOS-FET, respectively and T 10 and T 12 are n-channel MOS-FET, respectively. During the data retention, it is not necessary to supply the power supply voltage since these logic circuits are not required to be operated. Therefore, V CL1 for normal operation is set at 1.5 V and V CL2 for data retention is set at 0 V. These internal power supply voltages V CL1 and V CL2 are supplied from a power supply voltage converter circuit 6 e or a p-channel MOS-FET which serves as a switch ( FIG. 1A SW 6 a). The power supply voltage converter circuit 6 a is constituted by a differential amplifier circuit A 1 ; a resistor R 3 and two n-channel MOS-FETs T 3 and T 4 which serve to control the operating current to the differential amplifier circuit; three resistors R 4 to R 6 and a p-channel MOS-FET T 5 which serve to control the feed-back amount to an inverting input of the differential amplifier circuit; and a p-channel MOS-FET T 2 which serves as a switch.

In operation, in the case where V cc is high and so is to be decreased to the internal power supply voltage, the limiter enable signal LM becomes a high voltage (“1”). Then, T 1 is cut off and also T 3 is made conductive, thereby supplying a bias current to the differential amplifier circuit A 1 . Thus, the voltage proportional to V L at a non-inverting input of A 1 is output. On the contrary, when the signal LM is a low voltage (“1”), T 3 is cut off and the bias current is not supplied. Then, V cc is directly output as the internal power supply voltage.

During the data retention operation, the data retention signal PD becomes a high voltage (“1”). Then, T 2 is cut off, thereby stopping the current supply to the circuit block 5 d. On the other hand, T 4 is cut off and so the value of the bias current to the differential amplifier circuit A 1 is defined. The current consumed by the memory cell array in the data retention state is very small and can be regarded as a substantially constant D.C. current in time lapse. Therefore, the load driving capability of the differential amplifier circuit may be much smaller than that in the normal operation so that even if the bias current is remarkably decreased, any difficulty in operation does not occur. Also by making T 5 conductive to increase the feed-back amount in the differential amplifier circuit, the internal power supply voltage for the data retention is decreased. Thus, the consumed current in the entire LSI chip during the data retention can be remarkably decreased. Incidentally, in this embodiment, V L =0.75 V, and R 4 =R 6 =3R 5 . Then, V CL2 is 1.5 V for the normal operation and 1.0 V for data retention.

FIG. 3B shows an example of the relation between the power supply voltage V cc and internal power supply voltages V CL2 and V CL1 . In this figure, the abscissa represents V cc and the ordinate represents V CL . As in the embodiment of FIG. 2A , the power supply voltage for normal operation is set at the range of 3 to 3.6 V; the power supply voltage for data retention is set at the range of 1 to 2 V; and the reference voltage V cx for switching between the normal operation and data retention is set at 2.5 V. Further, the internal power supply voltages V CL2 and V CL1 for the normal operation are 1.5 V and V CL2 for the data retention is 1 V. However, these voltage values may be set at a suitable value corresponding to the operation characteristic of the circuit within a range not exceeding the power supply voltage V cc .

FIG. 3C shows an example of the secular change (time-dependent fluctuation) of the internal power supply voltage V cc , and two control signals LM and PD in the case where the power supply voltage V cc is changed in time lapse in the LSI chip. Now, consideration is made on the case where V cc is decreased from 3.3 to 2 V in the period of t 0 to t 2 and thereafter is increased from 2 to 3.3 V in the period of t 3 to t 5 . In the period of t 1 to t 4 when V cc is lower than V cx =2.5 V, the signal PD becomes a high voltage state (“1”), thereby placing the chip into the data retention state. In this period, V cc is not smaller than 1.5 V so that the signal LM remains a high voltage state (“1”).

In the embodiment mentioned above, there can be realized a static memory which can operate at a high speed during the normal operation and retain data with necessary minimum power during the data retention operation, and an LSI which locally incorporates such a static memory. Incidentally, in this embodiment, the static memory cells with high resistance load are used. However, the present invention can be also applied to the memory array which is constituted by CMOS memory cells each constituting of two CMOS inverters and two selective transistors, or latch circuits consisting of two NAND gates or two NOR gates.

FIG. 4A shows an embodiment in which the present invention is applied to a dynamic memory. In this figure, 5 e is a dynamic memory which operates at a power supply voltage of 1.5 V or less and in which one memory cell is constituted by an n-channel MOS-FET T 18 and a storage capacitor C S1 . Numeral 13 is a memory cell array; numeral 14 is a row address buffer; numeral 15 is a column address buffer; numeral 16 is a row address strobe (RAS) input buffer; numeral 17 is a column address strobe (CAS) input buffer; numeral 18 is a write enable (WE) input buffer; numeral 19 is a data input buffer; numeral 20 is a data output buffer; numeral 21 is a clock generator circuit for generating control clocks on the bias of the row address strobe (RAS) signal; numeral 22 is another clock generator circuit for generating control clocks on the basis of the column address strobe (CAS) signal; numeral 23 is a write clock generator circuit; numeral 24 is a refresh (RFSH) signal generator circuit; numeral 25 is a multiplexer for switching the refresh address and an external input address.

Meanwhile, in the dynamic memory, data are stored by storing charges in the storage capacitors C s1 so that so-called refresh operation in which signal charges are periodically read out and rewritten is required also in the data retention operation and to this end, a part of the peripheral circuit other than the memory cell array must be operated. Further, in order to assure sufficient noise margin, also in the data retention, the signal charge amount equivalent to in the normal operation must be assured. Then, in this embodiment, the internal power supply voltage is fixed at 1.5 V for both data retention and normal operation.

During the data retention, it is not necessary to perform the input/output of data between the inside and outside of the chip, so that all the input/output buffers are cut off by a data retention signal PD. The multiplexer 26 is controlled by the signal PD to switch the memory addresses into the addresses from the refresh address generator circuit 25 in the data retention operation. During the refresh operation, the refresh signal RFSH is at a high voltage level (“1”). This signal is supplied to the refresh address generator circuit 25 to sequentially increase or decrease the refresh address. Also the signal RFSH activates the clock generator circuit 21 to generate clocks for refresh.

The internal power supply voltage V CL is supplied from a power supply voltage converter circuit 6 f of a p-channel MOS-FET T 14 serving as a switch ( FIG. 1B , SW 6 a). The power supply voltage converter circuit 6 f is constituted by a differential amplifier circuit A 2 ; a resistor R 9 and three n-channel MOS-FET's T 15 , T 16 , and T 17 which serve to control the operation current of the differential amplifier circuit; and two resistors R 10 and R 11 which serve to the feed-back amount to an inverting input of the differential amplifier circuit A 2 .

In operation, in the case where Vcc is high and so is to be decreased to the internal power supply voltage, the limiter enable signal LM becomes a high voltage (“1”). Then, T 14 is cut off and also T 15 is made conductive, thereby supplying a bias current to the differential amplifier circuit A 2 . Thus, the voltage proportional to V L at an non-inverting input of A 2 is outputted. On the contrary, when the signal LM is a low voltage (“1”), T 15 is cut off and the bias current is not supplied. Then, V cc , which is at a low voltage level, is directly outputted as the internal power supply voltage.

During the data retention operation, the data retention signal PD is at the high voltage level (“1”). Then, the transistor T 16 is cut off and the bias current for the differential amplifier A 2 is defined by the resistor R 3 . The current consumed in the data retention state and in a period when the peripheral circuit does not operate is small. Therefore, the load driving capability of the differential amplifier circuit may be much smaller than that in the normal operation so that even if the bias current is remarkably decreased, any difficulty in operation does not occur. During the refresh operation, the signal RFSH is fed back to the power supply voltage converter circuit to make the transistor T 17 conductive, thereby making the bias current for A 2 substantially equivalent to that in the normal operation. In this way, during the refresh operation, the power supply current required for charging/discharging of data lines and operation of the peripheral circuit can be supplied. Therefore, also in the data retention operation, the current consumed in the entire chip can be remarkably decreased without lowering the noise margin. Incidentally, in this embodiment, with V L =0.75 V and R 10 =R 11 , the internal power supply voltage V CL 32 1.5 V is obtained, but the other combination of the voltages and resistances may be adopted.

FIG. 4B shows an example of the secular change (time-dependent fluctuation) of the internal power supply voltage V cL , two control signals LM and PD, the refresh signal RFSH, and the bias current for the differential amplifier circuit A 2 in the case where the power supply voltage V cc is changed in time lapse in the LSI chip. Now, consideration is made on the case where V cc is decreased from 3.3 to 2 V in the period of t 0 to t 2 and thereafter A increased from 2 to 3.3 V in the period of t 3 to T 5 . In the period of t 1 to t 4 when V cc is lower than V cx =2.5 V, the signal PD becomes a high voltage state (“1”), thereby placing the chip into the data retention state. In this period, V cc is not smaller than 1.5 V so that the signal LM remains a high voltage state (“1”). In the refresh operation within the data retention period, the bias current I B1 substantially equal to that in the normal operation is caused to flow and in the other period, a sufficiently small bias current I B2 is caused to flow.

In the embodiment mentioned above, a so-called address multiplex system in which a row address and column address are taken in under time exchange is used. However, the present invention can be applied to a general system in which all address are simultaneously taken in. Further, by using a dynamic memory as described later in which the plate is driven to reduce the voltage amplitude in data lines, a memory with further reduced power consumption can be realized.

FIGS. 5A and 5B show an example of the timing of the refresh signal RFSH during the data retention state, respectively. In this case, refresh of the entire memory array is intended in 4096 cycles. By reducing the power supply voltage to e.g. 1.5 V or less, power consumed in the entire memory can be greatly decreased so that the memory with large capacity of 64 Mb or so does not require to increase the number of the refresh cycles to the number exceeding 4096, thereby making it easy to construct the system. In initial 4096 cycles from when the date retention state starts, refresh with a short interval i.e. the signal RFSH with a relatively short period T c1 is generated. This is because the refresh control in the normal operation is not relative to the internal refresh. Such an initialization can obviate danger that the condition of the refresh period will not be satisfied before and after the state shift. In FIG. 5A , the signal RFSH is generated at a fixed period T c2 after the short interval refresh. On the other hand, in FIG. 4B , the short interval refresh is repeated at a period of T c3 . The period of the signal RFSH is set at the same period T c1 as the initial short interval refresh. Although the other period may be used, use of the same period is convenient in the construction of the signal generator circuit.

FIG. 6 is a graph showing an example of dependency of the refresh period (cycle time) T c2 upon the chip temperature in the example of FIG. 5 A. The relation between the chip temperature and data retention time is discussed in e.g. IEEE Transactions on Electron Devices, Vol. 35, No. 9, pp. 1257-1263, August 1987. According to this article, the data retention time varies in about three orders of magnitude when the chip temperature changes in the range of 0° to 100° C. Therefore, if the refresh period T c2 is varied as shown in FIG. 6 , it can accord with the actual data retention characteristic. The power consumed in a chip in a data retention state is very low so that there is not almost a difference between the atmospheric temperature and the chip temperature. Thus, by using the chip in low atmospheric temperature, the refresh period can be extended thereby further reducing the power consumed in the chip. In this way, a dynamic memory which can be suitably incorporated in a portable electronic device using a battery as a power supply source can be realized. Incidentally, an oscillator circuit having the temperature dependency as shown in FIG. 6 is disclosed in U.S. Pat. No. 4,661,929.

FIG. 7 is a graph showing an example of the occurrence of refresh failure in the example of FIG. 5 B. In this figure, the abscissa represents the refresh period and the ordinate represents the number of accumulated fall bits. As seen from the figure, only one bit failure occurs for the refresh period T c3 . If a very small part of the memory is damaged, the damaged memory cells can be restored by means of a so-called redundancy technique in which they are replaced by redundant memory cells previously provided on the chip. This technique is discussed in IEEE Journal of Solid-State Circuit, Vol. 16, No. 5, pp. 479-487, 1981. This technique can be also applied to the refresh failure as shown in FIG. 7 . The conventional redundancy technique, however, a disadvantage of increasing the chip area since it requires redundant memory cells.

FIGS. 8A , 8 B, and 8 C are views for explaining a refresh failure relief technique which does not use redundant memory cells. This technique intends to refresh only the memory cell, which result in failure at the refresh period T c3 in FIG. 7 , at the refresh period e.g. T c4 which is shorter than T c3 . This technique will be explained below with reference to FIGS. 8A , 8 B, and 8 C.

FIG. 8A shows an example of the timing of the refresh signal RFSH during data retention state when using this failure relief technique. Now it is assumed that an address 1 is in refresh failure. As seen from the figure, the address 1 is refreshed at the period T c4 between one short interval refresh and the subsequent short interval refresh. The current consumed in this case can be remarkably reduced as compared with the case where entire addresses are refreshed at the short period T c4 , Incidentally, the condition of 4096×T c1 ≦T c4 ≦T c3 among the respective refresh periods.

FIG. 8B shows an exemplary circuit arrangement for generating the refresh address and the refresh signal RFSH. FIG. 8C shows the operation timing thereof. In FIG. 8B , OSC is an oscillator for generating a clock φ 0 ; DV 1 , DV 4 , and DV 3 are a frequency divider for generating a clock φ 1 , φ 4 and φ 3 having the period that is integer-time as long as the clock φ 0 , respectively; 30 is a synchronous counter with 13 bits; 31 is refresh address generator circuit; 32 is a refresh signal (RFSH) generator circuit; I 1 is an inverter; G 1 , is an AND gate; and G 2 is an OR gate.

In operation, the counter 30 is operated by the clock φ 1 and starts count from the state where a high voltage (“1”) is applied to a reset terminal to reset all of the counter outputs at a low voltage (“0”). When the count becomes 4097, the counter output Q 12 becomes a high voltage (“1”), the counting is stopped. In FIG. 8B , e is a counter enable signal. Since e is at the high voltage level (“1”) while the counter operates, the outputs Q 0 to Q 11 of the counter are outputted at the outputs a r0 to a r11 of the refresh address generator circuit 31 . When the counter stops the count, e becomes the low voltage (“0”) so that failure addresses a s0 to a s11 are output at a r0 to a r 11 . In the same manner, the clock φ 1 is outputted from the refresh generator circuit 31 while the counter operates and the clock φ 4 is output therefrom after the counter has stopped the count. Thus, while the counter operates, the short interval refresh is performed 4096 times at the period T, and after the counter has stopped the count, only the failure address is refreshed at the period T c4 . Incidentally, although in the above example, the relief of only one failure address was explained, the present invention can be applied to the case a plurality of failure addresses are to be relieved.

In the embodiment mentioned above, there can be realized a dynamic memory which can operate at a high speed during the normal operation and retain data with necessary minimum power during the data retention operation, and an LSI which locally incorporates such a dynamic memory. Further, even if the external power supply voltage greatly fluctuates, which is problematic for the conventional dynamic memory, the dynamic memory in accordance with this embodiment can stably operated by operating the internal circuit at a low voltage of e.g. 1.5 V.

Although in the embodiments hereinbefore, a difference between the normal operation state and the data retention state is detected by the detection means provided on the LSI chip, the operation state may be controlled from the exterior of the chip FIG. 9 shows the other embodiment of the present invention in which shift to the data retention state is controlled by a detection circuit provided outside the chip. In this figure, 4 b is a data retention state signal which is generated by a detection circuit 3 and supplied to an LSI chip; IB the LSI chip which has functions of data storage or data processing like the LSI chip of FIG. 1B ; and PAD 3 is a bounding pad for receiving the data retention state signal. The LSI chip of FIG. 9 is different from the LSI chip of FIG. 1 in that it is not necessary to provide detection means and means for generating the data retention state signal. This chip may be designed individually from the LSI chip of FIG. 1 , otherwise one chip, after having been designed, may be divided through exchange of bondings or master slice of aluminum wirings.

FIG. 10 shows the case where the LSI chip of FIG. 9 is operated using a battery as a power supply source and the signal PD is inputted from outside of the LSI chip. The voltage value of the battery is distributed in a wide range of 1 to 3.6 V in accordance with its kind. Thus, this technique, in which the system can be controlled externally, is more convenient than the method in which shift to the data retention state is detected by voltage change.

FIG. 10B shows dependency of the internal power supply voltage V cL upon the power supply voltage V cc . In this example, over the normal operation range of 1 to 3.6 V, V cL =1.5 V for V cL of 1.5 V and V cL =V cc for V cc of 1 to 1.5 V. In this way, a change of the internal power supply voltage can be restrained over a wide range of 1 to 3.6 V. Accordingly, an LSI the operation performance (e.g. operation speed, consumed current, operation margin, etc.) of which does not almost depend on the power supply voltage can be realized. Further, shift to the data retention state can be made as required without varying the power supply voltage so that unnecessary power consumption can be restrained in accordance with the state of the system. Thus, the operation time of an electronic device which operates by a battery can be lengthened.

FIG. 10C shows an exemplary concrete construction of the power supply voltage converter. As in the embodiment of FIG. 1 , L 1 H is designed to perform an optimum operation at a relatively high power supply voltage (e.g. 2.5 to 3.6 V), and L 1 L is designed to perform an optimum operation at a relatively low power supply voltage (1.5 to 2.5 V). The respective voltage converter circuits are controlled to be in an operation state when control signals LH and LL are at a high level. When the data retention state signal PD becomes a high voltage state to place the chip in the data retention state, the bias current for the differential amplifier circuit is reduced to a low level, thereby reducing the current consumed in the voltage converter circuit and so reducing the power consumed in the LSI chip. In the case where both LH and LL are at a low voltage level (external power supply voltage<1.5 V), both voltage converter circuits are turned off and also a switch SW 6 a is switched on, thereby supplying the external power supply voltage to the internal circuit.

In such an arrangement, even when the external power supply voltage varies in a wide range of 1 to 3.6 V, an LSI which can-operate at several power supply voltages can be provided without sacrificing the operation performance of the main circuit. Further, the chip can be switched into a low power consumption mode such as data retention mode as required through external control, thereby reducing the power required during the operation using a battery.

FIG. 11A shows an exemplary construction of an LSI in which the battery back-up circuits as shown in FIGS. 1 A and FIG. 9 are integrated on a chip and switching of power supply sources are performed on the chip. In this figure, 1 C is an LSI chip which has a function of data storage or data processing like the LSI chip of FIG. 1A ; numeral 40 is a power supply switching circuit; numeral 41 is a voltage drop detector circuit; SL and SB are a switching signal generated by the voltage drop detector circuit, respectively; SW 40a and SW 40b are switch for switching the power supply sources by the switching signal S L or S B respectively; and PAD 4 is a bonding pad to which the voltage of a battery is applied. By performing the switching of the power supply voltages on the chip in this way, it is necessary to package a battery back-up circuit on a system (board), thereby reducing the number of components and so improving the production cost and the packaging density. Further, a power supply switching circuit in accordance with the characteristic of the LSI can be incorporated so that a user is not required to think of the voltage fluctuation caused by switching of the power supply sources, thereby providing a very convenient chip.

FIG. 11B shows an exemplary concrete construction of the power supply switching circuit 40 . In this figure, numerals 42 and 43 are a differential amplifier circuit, respectively; numerals 44 and 45 are an output therefor; T 19 and T 20 are P-channel MOS-FETs corresponding to a switch for switching the power supply sources, respectively; and numeral 46 is an output of the power supply switching circuit 40 . Explanation will be given for the operation of this power supply switching circuit 40 . Voltages γV cc and γV BT in proportion to V cc (power supply voltage) and V BT (battery voltage) are applied to the non-inverting input and the inverting input of the differential amplifier circuit 42 respectively, Likewise, voltages γV BT and γ V cc in proportion to V BT and V cc are applied to the non-inverting input and the inverting input of the differential amplifier circuit 43 . Which is a proportion on constant satisfying the condition 0≦γ≦1 is to be desired to be a value capable of providing a sufficient voltage gain and output amplitude in the differential amplifier circuit. The above proportional voltages can be generated using resistors. The outputs 44 and 45 of the differential amplifier circuits 42 and 43 are applied to the gates of the transistors T 19 and T 20 . When V cc >V BT , a high voltage (V cc ) appears at the output 44 and a low voltage (−γV cc −V T ) appears at the output 45 so that the transistor T 19 is made conductive and the transistor T 20 is non-conductive. Thus, V cc is output as an internal power supply voltage V INT Likewise, when V cc <V BT , the low voltage (−γV−V T ) appears at the output 44 and the high voltage (V BT ) appears at the output 45 so that the transistor T 19 is made conductive and the transistor T 20 is made non-conductive. Thus, V BT is output as V INT This circuit operates in the same manner even when either one of V cc and V BT is 0 V so that even when only one of V cc and V BT is supplied, the supplied voltage is output as it is as a power supply voltage for the internal circuit.

FIG. 11C shows a example of the dependency of V INT upon V cc with V BT 1.5 V. As seen from the figure, when V cc=B >1.5 V, V INT =V cc , and when V cc <1.5 V, V INT =1.5 V. Since V INT varies continuously, kink which has adverse effect on the operation of the LSI is not generated. In this way, the voltage switching circuit can be constructed in a relatively simplified circuit so that even when incorporated on an LSI chip, it does not almost increase the chip area. Although MOS-FET's are used in this example, the other devices e.g. bipolar transistors may be used.

With reference to the embodiments mentioned above, the basic idea of the LSI chip in which the main circuit block operates at the voltage of 1.5 V or less has been explained. In the following description, more detailed embodiments will be explained mainly in relation to a dynamic memory. It has been considered generally that the dynamic memory is difficult to operate at a low voltage as compared with a logic LSI or a static memory. The first reason is that the signal charge amount defined by a product of a storage voltage and storage capacitance is reduced due to voltage lowering, thereby decreasing the SIN. Therefore, it has been considered difficult to assure the noise margin for noise charge generated due to irradiation of rays emitted from a small amount of radioelements which are contained in a package and metallic wirings or noise charge due to leakage current, induced by thermal (or non-thermal) carrier generation, flowing into memory cells. These problems can be solved by one of the following two techniques.

(1) Using of a circuit which can provide the memory cell storage signal voltage (e.g. low voltage=0 V and high voltage=3 V) substantially equivalent to the conventional technique also at a low voltage power supply voltage (e.g. 1.5 V). In this case, the storage capacitance of the memory cells may be a value (e.g. 30 to 40 fF) substantially equivalent to the conventional technique.

(2) Increasing the storage capacitance of the memory cells in substantial inverse proportion to a power supply voltage in compensation for using the conventional circuit system. For example, when the power supply voltage is 1.5 V, the memory cell storage capacitance is set at 60 to 80 fF.

In connection with the technique of (1), disclosed in an embodiment described later is a technique in which by driving the plate of the memory cells as well as word lines and data lines, the signal amplitude larger than that in the data lines is stored in the memory cells. And, in connection with the technique of (2), a technique of remarkably increasing the storage capacitance as compared with the conventional technique is disclosed in JP-A-60-26711 and 1988 Symposium on VLSI Technology, Digest of Technical Papers, pp. 29-30, 1988. By means of these techniques, the storage signal charge required for stabilized operation can be assured.

The second problem to be solved for the low voltage operation is to simultaneously realize a high speed operation and low current consumption. The third problem is to realize a device or circuit which permits a low voltage operation circuit and a high voltage operation circuit to be integrated on the same chip. The third problem φ1, particularly problematic when the voltage ratio of a high voltage source to a low voltage source is 2 or more. A technique in which the third problem can be solved by two kinds of devices for low and high voltages are formed on the same chip is disclosed in U.S. Pat. No, 4,482,985. This technique permits the circuits for both the low and high voltage power sources to be constructed using optimized devices but a disadvantage that the production process of an LSI is made complicated. In connection with the embodiment explained below, explanation will be given for means for solving the second problem and operating at a minimum power supply voltage of 1 V and a method for solving the third problem without complicating the production process. By means of these techniques, the operation power supply voltage of the dynamic memory is reduced to 1 to 1.5 V or so, and the high integration degree, high speed, and low power consumption of the dynamic memory or the LSI chip locally incorporating it can be realized simultaneously. Also, the condition required for battery operation or battery back-up operation can be satisfied.

First, the means for solving the second problem will be explained. Although in the following example, a Complementary MOS-FET (CMOS-FET) is used, a bipolar transistor, junction transistor or device of material other than silicon may be used as long as the same effect is obtained.

FIG. 12A shows a relation between the gate-source voltage V GS of an n-channel MOS-FET and the drain current I 0 . This relation is classified into (i) a square root region where the square root of I 0 is substantially proportional to V GS , and (ii) a sub-threshold region where I O is proportional to the exponential function of V GS in a region with a lower V GT . In FIG. 12A , V T1 is a so-called gate threshold voltage at which the drain current start to flow when it is assumed that the current-voltage characteristic can be approximated by the square root disregarding the region of (ii) V T0 is the other definition of the gate threshold voltage at which the drain current can be regarded approximately zero in the circuit operation. With the gate width of 10 μm, the drain current at V GS =V T0 is about 10 nA and the drain current at V GS =V T1 is about 1 μA. The difference between V t1 and V T0 is about 0.2 V (V T1 >V 0 ). The current driving capability of an actual MOS-FET is related with V GS −V T1 and the static current in a stand-by state is related with V T0 . In the following example, the threshold voltage of the devices used in the main circuit of LSI is set at V T1 =0.3 V (and so V T0 is about 0.1 V). Thus, a CMOS sense amplifier or differential amplifier in which MOS-FET must be operated by a voltage (e.g. 0.5 V) half the power supply voltage can be operated, permitting the entire circuits in a range of the power supply voltage to 1 V to be operated. Further, the stand-by current of the entire chip can be limited to about 10 μA. Even if the threshold voltage fluctuates by −0.1 V due to unevenness of several production processes, the circuit operation at the power supply voltage of 1 V can be realized and also the stand-by current of the entire chip can be limited to 100 μA or less. Incidentally, the channel length is set at 0.3 μm, so that a sufficient operation speed can be obtained at the power supply voltage of 1 V.

FIG. 12B shows dependency of the gate threshold voltage V cc upon the channel length in two n-channel MOS-FET's (case 1 and case 2 ). Case 1 is the characteristic of the device fabricated in accordance with the condition in the case where a substrate bias voltage is applied which is common in the dynamic memory (DRAM) based on the conventional concept, and case 2 is the characteristic of the device fabricated in accordance with the condition in the case where the substrate voltage is applied which is used. Since in the present invention, the low voltage operation is a basic premise, the experiment of the case 1 is carried out with V cc =1.5 V and V BB =−1 V considering the ratio of the conventional V cc =5 V and V BB =−3 V. The cases 1 and 2 are adapted so that the gate threshold voltage V T1 is 0.3 V when V BS =−1 V (case 1 ) and V BS =0 V (case 2 ).

The device of the case 1 has the following three problems.

(1) Fluctuation of the gate threshold voltage for variation of the channel length is large so that the case 1 is inferior in the controllability as compared with the case 2 , thus making it difficult to provide a short channel. This is because the substrate voltage is set at −1 V.

(2) The substrate bias voltage, which is generated by a substrate bias voltage generator circuit provided on a chip, fluctuates due to production unevenness and also greatly varies in dine lapse depending on the number of operating circuits. Therefore, the gate threshold voltage, which is strongly modulated by the substrate bias voltage, can not satisfy the condition required for the low voltage operation with high accuracy.

(3) Since the substrate voltage is 0 V while the power supply is active, the gate threshold voltage is placed at a value lower than 0.3 V (e.g. 0 V) due to the body effect (see the broken line in FIG. 12 B). Also, the substrate is substantially in a floating state so that the substrate voltage is transiently increased due to capacitive coupling with V cc thereby making the gate threshold voltage minus. Thus, the MOS-FET in a peripheral circuit is made conductive so that a large transient current flows.

On the other hand, the present invention, in which the substrate voltage is set at V SS =0 V, can provide an LST chip with excellent controllability of the gate threshold voltage and with a small transient current during closure of the power supply source. Further, by externally supplying the ground voltage, variation of the substrate voltage during the circuit operation can be made approximately zero so that capacitive coupling noise from the substrate voltage can be greatly decreased.

The reason why the substrate voltage fluctuates is that the conventional substrate bias generator circuit is formed on the chip and so does not have sufficient driving capability.

The reason why the substrate voltage (−3 V) is conventionally applied is that the case where the input voltage of a signal is decreased is considered. More specifically, when the input voltage is decreased from 0 V, if the substrate voltage is 0 V, the p-n junction is forward-biased, thus injecting minority carriers. The minority carriers, which destroy data stored in the memory, are not very preferable. Then, it has been conventionally permitted that the signal input voltage is decreased.

The embodiment in the present invention, which does not have such margin, requires an improvement as explained with reference to FIGS. 14A and 14B .

FIG. 13 shows the gate oxide film thickness t ox , electric channel length (effective channel length) L dff and gate threshold voltages V T1 and V T0 of the device used in the main circuit of a dynamic memory which is capable of operating at a minimum voltage of 1 V. The values in parentheses mean the range of fluctuation due to production evenness, etc.

FIGS. 14A and 14B show parts of the sectional structure of the dynamic memory in accordance with the present invention. In the conventional dynamic memory, a minus voltage is applied to the substrate for the following three reasons:

(1) If a minus voltage is externally applied to the input or output due to ringing, etc., electrons which are minority carriers are injected into the substrate. The electrons diffuse through the substrate and a part thereof reaches the charge storage portion of the memory cell, thereby deteriorating the refresh characteristic. This injection of minority carriers into the substrate is intended.

(2) By applying a minus voltage to the substrate, the junction capacitance between the n diffused layer and the p substrate is reduced thereby to reduce the load capacitance. This intends the high speed operation and low power consumption of the circuit.

(3) By applying a minus voltage to the substrate, the depiction layer below the channel is extended so that the potential at the channel becomes hard to be dependent on the substrate voltage. Thus, the gate threshold voltage is not almost affected by fluctuation of the substrate voltage. In other words, the body effect coefficient of the gate threshold voltage becomes small. This is convenient in the operation of a partial circuit of the memory.

Among these reasons, the reason of (3) has become weak with tendency of the twin-well structure of CMOS-LSI. Therefore, it is important to solve the problems of (1) and (2). A substrate structure which permits a plurality of substrate voltages to be applied in CMOS-LSI is disclosed in JP-A-62-119958 (corresponding to U.S. patent application Ser. No. 87256). By combining this structure and the low voltage LSI in accordance with the present invention, a low voltage LSI with the performances of high noise resistance, high operation speed and low power consumption can be constructed. An example of such a low voltage LSI using the substrate structure shown in FIGS. 14A and 14B will be explained.

In FIGS. 14A and 14B , the impurity concentration of a p-type Si substrate is about 1×10 15 cm −3 . Formed in the substrate are two kinds of n-wells (N 1 and N 2 ) which are provided through two different steps and one kind of p-well. The impurity concentration of each well is for example about 1×10 16 cm −3 for N 2 well, and 5×10 16 cm −3 for N 1 well and P well (these values may be changed in accordance with the device size). In the figures, numerals 50 are thick oxide about 500 nm for making electric isolation between active regions, respectively; numerals 51 are first polysilicon electrodes for, forming storage capacitors, respectively; 52 's are second polysilicon electrodes serving as gate electrodes of MOS-FET, respectively; numerals 53 and 54 are n-impurity diffused layers having impurity concentration of about 2×10 20 cm −3 which are formed in a self-aligned manner using as a mask these thick oxide film and poly-silicon electrodes, respectively; and numerals 55 , 56 and 57 are p-impurity diffused layers in the same manner. The p-substrate is fixed to ground potential (V SS ) through the diffused layer 56 . The storage capacitor of the memory cell and selecting transistors T N3 and T N4 are formed within the P-well electrically isolated from the substrate through the N 2 Well, Applied to the P-well is a second substrate potential V BN2 through the diffused layer 57 . Applied to the N 2 well is a second well potential V BN2 through the N 1 well electrically adjacent to the N 2 well and the diffused layer 54 . In a peripheral circuit operating at V B5 =0 V, an N-channel MOS-FET T N1 is formed in the P-substrate and a P-channel MOS-FET T P1 is formed in the N 1 well. Also, an N-channel MOS-FET T N2 in the peripheral circuit is formed in the P-well which is distinct from a memory cell array and electrically isolated from the P-substrate. In this way, in the case where a minus voltage in an input/output voltage, etc. or a voltage higher than the voltage in the N-wells may be externally applied, an individual substrate voltage in accordance with the overshoot or undershoot can be applied, To electrically isolate the P-well where the memory cell array is formed from the P-substrate has the other following advantages.

(1) By biasing the P-well of the memory cell array at a minus voltage, the data line capacitance can be reduced to improve the S/N.

(2) The N 2 well covering the memory cell serves as a barrier for the minority carriers diffusing through the substrate. This restrains collection of noise charges into the storage capacitor, thus improving the noise resistance.

As mentioned above, by using the substrate structure as shown in FIGS. 14A and 14B , the stabilized operation of the memory cell array and the high speed operation and low power consumption in the peripheral circuit can be simultaneously realized. Incidentally, although the case of using the P-substrate was explained, using an N-substrate can provide the same effect. However, the battery operation and battery back-up operation to which the present invention is directed must consider use of the apparatus in an atmosphere where the power supply voltage greatly varies. If the N-substrate is used, a maximum voltage (V cc ) of the system is applied to the N-substrate, Therefore, when the power supply voltage greatly varies, the potential of the N-substrate also varies, and noise is induced in respective circuits due to capacitive coupling with the N-substrate. For this reason, a P-substrate as shown in FIGS. 14A and 14B is suitable for the present invention.

FIGS. 15A and 15B show an example of the LSI circuit which has a function of data retention and the voltage lowering of which can be further advanced in accordance with the present invention. FIG. 15A shows an example of the peripheral circuit. In FIG. 15A , numeral 60 is a circuit block operating at a power supply voltage of V cL1 ; numeral 61 is a circuit block operating at a voltage of V CL2 ; V BP1 is a substrate bias voltage for N-channel MOS-FETs in the circuit block 61 ; and V BP2 is a substrate voltage for P-channel MOS-FETs in the circuit block 61 . The circuit block 60 is not required to operate during data retention and so V CL1 =0 during the data retention. On the other hand, the circuit block 61 is required to operate also during the data retention and the value of V CL2 ; is fixed regardless of the operation state. In order to operate the circuit at a range of the power supply voltage to 0.5 V or so, threshold voltage V must be set at a range of 0 to 0.1 V or so. Then, the circuit does not operate and even with the gate-source voltage of 0 V, a current of 1 μA, or so flows through MOS-FET. And a large current of 10 mA flows through the entire chip. In order to reduce the current consumed during the data retention, this static current must be reduced. Generally, the operating speed may be slower during the data retention than during the normal operation. Therefore, in this example, by controlling the substrate voltage, the threshold voltage of MOS-FETs during the data retention is changed toward the direction in which the device is hard to be conductive (the threshold voltage of the N-channel MOS-FET is made high and that of the P-channel MOS-FET is made low) as compared with that during the normal operation.

FIG. 15B shows an example of a circuit for generating the substrate voltage V BP1 , of the N-channel MOS-FET, and FIG. 15C shows the operation timing thereof. Although this circuit will be explained in the case of V INT =1.5 V will be explained, it is particularly efficient for the case of a low power supply voltage of 0.5 to 1 V or so. In FIG. 15B , numeral 62 is a ring oscillator constituted by inverters I 2 to I 3 and an NAND gate; numeral 63 is a charge pumping circuit constituted by two MOS-FETs T 40 and T 41 and a capacitor C; T 42 and T 43 are N-channel MOS-FETs, respectively; and T 44 is a P-channel MOS-FET.

In the normal operation, i.e. when PD is at a low voltage (“1”) level, the ring oscillator and the charge pumping circuit do not operate. Also, MOS-FET T 44 is made conductive and anode N 1 is at a high voltage level (“1”) so that MOS-FET T 42 is made conductive and V BP1 becomes ground potential. On the other hand, in the data retention operation, i.e. when PD is a high voltage (“1”) level, MOS-FET T 43 is made conductive and the node N 1 becomes the same level as V BP1 so that MOS-FET T 42 is cut off. Also, the ring oscillator 62 and the charge pumping circuit 63 operate, thus producing a minus V BP1 . Incidentally, the substrate bias voltage is always applied to the memory cell array. As mentioned above, by controlling the substrate bias voltage in operating the memory by a low voltage power supply of 1 V or less, the high speed operation for the normal operation and low power consumption for the data retention can be realized. It should be noted that the idea mentioned above can be adapted to a circuit for generating V BN1 .

Explanation will be given for a concrete construction of the low voltage operation dynamic memory using the substrate structure as previously mentioned.

FIG. 16A shows the circuit construction of the dynamic memory. In FIG. 16A , MA 1 and MA 2 are memory cell arrays; DA 1 is a dummy cell array; W 0 to Wm are a word line; D 0 , {overscore (D 0 )}, Dn and {overscore (Dn)} are data lines; DW 0 and DW 1 are dummy word lines; XD is a word line selecting circuit; DWD is a dummy word line selecting circuit; T 52 to T 55 are left mat selecting transistors for controlling the connection of a left mat MA 1 with sense amplifiers; SHRL is a selective signal therefor; T 56 to T 59 are right mat selecting transistors for controlling the connection of a right mat MA 2 with the sense amplifiers; SHRR is a selective signal therefor; PR 0 to PRn are precharge circuits for setting the voltage of data lines during non-selection at a potential P; {overscore (φ p +L )} is a precharge signal; SA 0 to SAn are sense amplifiers for amplifying the minute signal voltage on the data lines; CSN and CSP are common source driving signals; CD is common source driving circuit; YG 0 to YGn are Y gates for connecting the data lines with common I/O lines; YDEC is a Y address selecting circuit; Y 0 to Yn are Y selecting circuits; DiB is a data input buffer for driving the common I/O lines in accordance with an input data; and DoB is a data output buffer for amplifying the signal current on the common I/O lines to be outputted. The value of the storage capacitance C is set at 50 to 80 fF or so as previously mentioned, and the value of the data line capacitance is set at 250 to 300 fF. Thus, with the data amplitude of 1.5 V on the data lines, the read-out signal voltage is about 150 mV which is enough to operate the sense amplifiers.

FIG. 16B shows the voltage waveforms at the respective parts at the time of data read-out with the power supply voltage of 1.5 V. The following description relates to the case where the read-out operation from the memory cells is intended and also the word line W 0 is selected. The precharge voltage of the data lines and the voltage at an opposite electrode (plate) of the cell storage capacitor are set at 0.75 V which is half the power supply voltage. In this way, (1) the capacitive coupling noise which is generated in charging/discharging or precharging the data lines is minimized and also (2) with the voltage applied to an insulating film serving as the storage capacitor being minimized, making the insulating thin film realizes to increase the storage capacitance. In order to store a high voltage (1.5 V) in the memory cells, 2.2 V is applied to the word line W 0 and the left mat selecting signal SEARLE so that the transistors T 50 and T 52 operate in their non-saturation region. Also, 1.2 V is applied to the common I/O lines so that MOS-FETs in the Y gates operate in their saturation region. As an amplifier for amplifying the signal on the common I/O lines operating at such a low power supply voltage, a current detection type amplifier as disclosed in U.S. patent application Ser. No. 88/201015 is suitable. If such a type of amplifier is used, (1) the voltage level of the common I/O lines can be increased to the neighborhood of the power supply voltage, and (2) the signal amplitude of the common I/O lines can be decreased (e.g. 50 mV) so that the operation margin in applying the Y selecting signal Y 0 to read a signal can be increased. The write for the memory can be performed by driving the I/O lines with the data input buffer DiB as usual. During data retention, data are not required to be externally so that the Y selecting signal Y 0 remains at a low voltage level (“1”) as indicated by a broken line (FIG. 16 B). Also, the Y address selecting circuit, the data input buffer, the data output buffer, etc. are not required to be operated. Further, the driving capability of the common source driving circuit CD for the sense amplifiers is decreased to decrease the time change coefficient of the data line voltage. Thus, during the data retention, the peak current due to charging/discharging of the data lines is reduced. By means of such control, even when a power source with a high internal impedance such as a battery is used, malfunction of LSI can be prevented through transient reduction of the power supply voltage. In the following description, explanation will be given for the following three circuits which are indispensable to realize the low voltage operation dynamic memory:

(1) a ½ V CL generating circuit

(2) a word line driving circuit and

(3) a common source driving source

FIG. 17A shows a circuit arrangement of the ½ V CL generating circuit. In FIG. 17A , T 60 and T 62 are N-channel MOS-FETs; T 61 and T 63 are P-channel MOS-FETs; and R 20 and R 21 are resistors for setting the bias current. The ratio of R 20 to R 21 in their resistance value is selected so that the voltage at a node N 4 and a node P is substantially half as large as V CL2 . C D1 to C D4 are a speed-up capacitor adapted to follow fluctuation of the power supply voltage. Among these values, the condition of C D1 =C D2 and C D3 =C D4 is satisfied. The substrate and source of each transistor are connected so that its threshold voltage is not increased through the body effect. Then, the absolute value of the threshold value of each transistor is about 0.3 V. If the substrate is connected with the maximum voltage of a system but not the source, the absolute value of the threshold value V T1 exceeds 0.5 V so that the operation at the power supply voltage V CL2 =1 V can not be obtained. In this way, in the circuit operating at a low voltage, the permissible minimum voltage is defined by the manner of providing the substrate voltage. Incidentally, the connection of the substrate with the source can be easily made using the substrate structure as shown in FIGS. 14A and 14B .

FIG. 17B shows a section structure of the N-channel MOS-FETs T 60 and T 62 . In FIG. 17B , numeral 65 is an n-diffused layer for providing the potential at an N 2 well; numeral 66 is a p-diffused layer for providing the potential at a P well; and numerals 67 and 68 are n-diffused layers serving as a source and drain of the N-channel MOS-FETs. The, p-diffused layer 66 which provides the substrate voltage of the MOS-FET is connected with the source thereof through external wiring. Applied to the N 2 well is the maximum voltage of the system i.e. V CL2 . As understood from the above example, the MOS-FET can be formed in the P well electrically isolated from the substrate so that the circuit suited for low voltage operation in which the threshold voltage is not affected by the body effect can be constructed. This example can be applied to a differential amplifier, etc. in which the source is operated at a higher voltage than ground potential.

FIG. 18A shows a circuit arrangement of the word line driving circuit and FIG. 18B shows an operation timing chart thereof. In FIG. 18A , T 82 is a memory cell transistor; C S3 is a storage capacitor; and T 80 and T 81 are N-channel MOS-FETs. The circuit shown in FIG. 18A is generally referred to a self-boost circuit. A selection signal for the word line selecting circuit BLVD of FIG. 16A is applied to a terminal S. This signal is at a high voltage level (e.g. 1.5 V) during selection and is at a low voltage level (0 V) during non-selection. Therefore, V CL −V T0 (V T0 is the threshold voltage of T 81 ) is applied to a node N 7 during the selection and 0 V is applied to the node N 7 during non-selection. After the selection signal has been decided, a higher pulse voltage (e.g. 2.2 V) than the power supply voltage is applied to a terminal X so that the memory transistor can be sufficiently turned on. Although during the non-selection, the MOS-FET T 80 is not conductive, during the selection the node N 7 is boosted to a high voltage through coupling with the gate capacitance of the transistor T 80 . In order for the pulse voltage applied to the terminal X to be outputted to the word line as it is, the voltage at the node N 7 must be boosted to a higher voltage than the pulse voltage applied to the terminal x, e.g. 2.2 V+V T1 (V T1 is the threshold voltage of T 80 ). If the substrate potential of MOS-FET is set at the ground potential, it is difficult to provide a predetermined amplitude in the word line for a low voltage power source with V CL =1.5 V or less since the threshold voltage is increased due to the body effect. In this example, in order to set the threshold voltage of MOS-FET at a sufficiently low value, the substrate voltage is connected the drain on the side of signal driving (by the selection signal S and the pulse voltage X in this example) (for convenience of explanation, the drain is defined as a terminal to which the driving signals are applied).

FIG. 18C shows a sectional structure of such a MOS-FET and FIG. 18D shows the equivalent circuit thereof. Although the sectional structure is the same as that of FIG. 17B , wiring thereof is different from the latter. Since the potential at the P well coincides with the potential at the drain, the wiring is equivalent to that as shown on the left side of FIG. 18D , there is provided a bipolar transistor having a collector and a base connected with the drain and having an emitter connected with the source. The bipolar transistor, in which its collector and base are connected, actually serves as a diode, and the wiring can be expressed as an equivalent circuit as shown on the right side in FIG. 18 D. Thus, if the drain voltage is higher than the source voltage, the MOS-FET in which the substrate voltage is forward-biased for the source and the diode D L are connected in parallel. On the contrary if the drain voltage is lower than the source voltage, the diode D L is reverse-biased to be cut-off and so only the MOS-FET, in which the substrate voltage is connected with the drain on the low voltage side, operates. Therefore, the threshold voltage in the former case is lower than that in the latter case, so that in the former case, the MOS-FET is likely to be conductive. Also, when the voltage difference is equal to 0.7 V or more, the diode is conductive so that in the former case, current is further likely to flow. Accordingly, the threshold voltage of the MOS-FETs T 80 and T 81 in driving the word line can be set at a low voltage so that also at a low power supply voltage the driving signal X can be outputted to the word line as it is. Such asymmetrical characteristic is efficient particularly for a self-boost circuit or the like but permits the low voltage operation to be improved also when it is applied to a rectifier circuit used in a charge pumping circuit for e.g. a pass-gate or a substrate bias voltage circuit.

FIGS. 19A and 19B show an exemplary circuit arrangement of the common source driving circuit, respectively. In FIG. 19A , T 85 and T 86 are N-channel MOS-FETs for driving the common source; and G 5 is an AND gate. During the normal operation, a signal {overscore (PD)} is a high voltage level (“1”) and is synchronized with an input common source driving signal φ cs so that both T 85 and T 86 become conductive. On the other hand, during data retention, {overscore (PD)} is at a low voltage level (“0”) so that only T 85 becomes conductive in response to an input φ cs . Thus, by suitably selecting the conductance of T 85 and T 86 , the operation speed can be preferred during the normal operation whereas the peak current can be reduced in compensation for sacrificing the operation speed.

In FIG. 19B , T 90 is an N-channel MOS-FET for driving the common source; T 91 , T 93 and T 94 are P-channel MOS-FETs; T 92 is a P-channel MOS-FET; G 5 is a NAND gate; G 7 is an AND gate; and R 25 is a resistor for supplying a bias current to T 94 . During the normal operation, a signal PD is at a low voltage level (“0”), thus cutting off T 93 . During the normal operation, a signal PD is at low voltage level (“0”) and so T 93 is cut off. The voltage at a node 8 becomes V CL in synchronization with the input of φ cs , thus driving T 90 . During the data retention, the signal PD is at a high voltage (“1”) and so T 93 is cut off. In synchronization with the input of φ cs , T 93 becomes conductive so that the voltage at the node 8 coincides with the gate voltage of T 94 . Then, a current mirror circuit is constituted by T 90 and T 94 so that the driving current for the common source is proportional to (V CL −V T1 )/R 25 where the proportional coefficient is defined by the ratio of T 90 and T 94 in their channel conductance. By using the driving circuit mentioned above, the common source is driven during the data retention with a constant controlled current so that the transient decrease in the power supply voltage due to the internal impedance of a battery does not occur, thus realizing the stabilized operation. Incidentally, the means other than the above current mirror circuit may be used as long as it can control the driving current during the data retention.

By means of the substrate structure, device constant and circuit arrangement in the embodiments as explained above, a dynamic memory assuring its operation at a minimum power supply voltage of 1 V can be realized. Further, in place of the circuit arrangement of the I/O lines and the Y-gates as shown in FIG. 16A , a technique of individually providing common I/O lines for both read and write whereby the operation margin during the read and write can be further improved may be adopted which is disclosed in JP-A-61-142549 and JA-A-61-170992. This technique permits the memory to be stably operated at a low power supply voltage of 1 V or so without being affected by variations of the devices.

Several arrangement examples of the main LSI circuit block which can operate a low internal power supply voltage of 1.5 V or less have been explained in relation to memories. However, in order to realize the LSI chip as shown in FIG. 1A , the circuits which can operate at a relatively high external voltage are also indispensable. These circuits at least include the following circuit:

(1) a reference voltage generating circuit,

(2) a voltage converting (dropping) circuit,

(3) an input circuit and

(4) an output circuit.

As indicated in the table of FIG. 13 , used in the main circuit block operating at a low internal power supply voltage of 1.5 V or less for the purpose of assuring its operation speed are device (having e.g. the gate length of 0.3 μm or less) fabricated by the up-to-date processing technique. However, these scaled-down devices are reduced in their gate withstand voltage and drain withstand voltage, thus making it difficult to operate the circuit block at a relatively high external voltage (e.g. 3 to 5 V). This is disclosed in IEDM Technical Digest, pp. 386 to 389, 1988. Considering the reliability for a long time, the voltage that can be applied to the gate oxide film having a thickness of 10 nm is about 4 V. Therefore, the maximum electric field intensity E max that can be applied to the gate oxide film is on the order of 4 MV/cm. It may be assumed that the value of E max does not approximately depend on the thickness of the gate oxide film and does not almost vary (actually has a tendency of slightly increasing with the decrease of the thickness of the gate oxide film). If this value is applied to device (gate oxide film thickness t ox =6.5 nm) identified in FIG. 13 , the maximum voltage that is permitted to apply is 2.7 V. Thus, the device can not be operated at a relatively high external voltage (e.g. 3 to 5 V). In order to solve this problem, the following two techniques can be proposed.

(1) As mentioned previously, on the same chip integrated in addition to the devices operated by the internal power supply voltage are the devices, with a relatively thick gate oxide film, operated by the external power supply voltage.

(2) The circuit block is constituted by only the devices operated by the internal power supply voltage. In this case, circuit contrivance is made so that the external power supply voltage is not directly applied to the devices.

The technique of (1) is disclosed in U.S. Pat. No. 4,820,85. This technique, however, complicates the fabricating process of LSI and so increases the production cost. Also this technique includes manly steps in forming gate oxide films which is most important in fabricating the devices so that it provides high possibility of introducing impurities and defects, thus reducing the reliability of the devices. Explanation will be given for the circuit block at a high power supply voltage realized by the technique of (2). Although in the following example, complementary MOS-FETs are used, the other devices e.g. bipolar transistors or junction transistors, combination thereof with MOS-FET and devices made of semiconductor material (e.g. GaAs) other than silicon may be used.

FIG. 20A shows an exemplary arrangement of the inverter circuit in accordance with the present invention. In FIG. 20A , T 100 and T 102 is an N-channel MOS-FET; T 101 and T 103 is a P-channel MOS-FET; in 1 and in 2 are a first and a second in-phase input terminal, respectively; out 1 and out 2 are a first and a second in-phase output terminal, respectively; Out is a third output terminal; and Vn and Vp are bias power supply voltages for the N-channel and the P-channel MOS-FET, respectively. Vn and Vp have dependency on the power supply voltage as shown in FIG. 20 B. In this example, when V cc ≧2 V, Vn=2 V and V p =V cc −2 V. Thus the voltage at the output terminal out 1 is Vn−V TN at the maximum so that the maximum voltage applied to the gate oxide film of the transistor T 100 is limited to V n −V TN . Likewise, the maximum voltage applied to the gate oxide film of the transistor T 101 is limited to V cc −V p +|V TP |. V TN is a gate threshold voltage of T 102 and V TP is a gate threshold voltage of T 103 . The signal levels at two output terminals out 1 and out 2 become 0˜V n −V PN and V cc −V p +|V TP |˜V cc , which drive inputs of the subsequent inverter. 0˜V cc , i.e. full-amplitude can be outputted to the third output.

When an inverter array is constructed using the above inverter (FIG. 20 C), the voltage at each node is as shown in FIG. 20 C. In FIG. 20C , the left side array relates to the case where an input is at an low level and the right side array relates to the case where an input is at a high level. As seen from the figure, when the input is at a low level, the voltage at in 1 is 0 V and the voltage at in 2 is V p +|V TP | so that the transistor T 100 is cut off and the transistor T 101 is turned on. Thus, the high level voltage is produced at the outputs, more specifically, V n −V TN is outputted at out 1 and V cc is outputted at out 2 . Likewise, is V n −V TN and the voltage at in 2 is V cc so that when an input is at a high level, the voltage at in 1 the transistor T 100 is turned on and the transistor T 101 is cut off. Thus, the low level voltage is produced at the outputs, more specifically, 0 V is output at out 1 and V p +|V TP | is output at out 2 . In both cases the maximum voltage applied to the gate oxide film of each transistor is listed on the table of FIG. 20 D.

In accordance with the above arrangement, for example, when V n =V p =½ V cc , in any transistor, the maximum voltage applied to the gate oxide film is limited to ½ V cc and the maximum voltage applied between the drain and the source thereof i limited to ½ V cc +V TN or to ½ V cc +|V TP |. Actually, in order to assure sufficient operation margin of the inverter, V n and V cc −V p are desired to be constant at a low power supply voltage. Further, in order that a large voltage is not applied between the drain and source, the channel conductance of T 102 and T 103 is desired to be larger than that of T 100 an T 101 , respectively. In this way, realized is a circuit which can operate, without deteriorating the device characteristic, at a power supply voltage range reaching about twice as large as the maximum voltage applied to the devices.

Further, in the example shown in FIG. 20A , the substrate potential of the N channel MOS-FET is connected with the minimum voltage of the system, i.e. V ss while the substrate potential of the P channel MOS-FET is connected with the maximum voltage of the system, i.e. V cc . However, if the substrate structure previously mentioned is used to connect the substrate of each transistor with the source, fluctuation of the threshold voltage due to the body effect can be restrained, thus realizing the circuit operating at a lower power supply voltage. Therefore, in accordance with the present invention, using only MOS-FET's with a thin oxide film of 6.5 nm or so can provide an LSI which can stably operate at a power supply voltage of 5 V.

FIG. 21A shows an exemplary arrangement of the inverter array (inverter chain) in which a plurality of stages of the inverters, each with an improved operation characteristic for a low power supply voltage through the connection of the substrate with the source, are connected. Like the conventional C-MOS inverter array, these inverters can be connected without inserting a level converting circuit as they are. Thus, a driver circuit which requires a large load driving capability like an output buffer can be constructed. Assuming that the number of the stages is an even number, the waveforms at the input and output are as shown in FIG. 21 B. In this example, the settings of V cc =4 V, V n −2 V and V p =2 V are made. In this array, the amplitude of the output signal for driving the subsequent inverter stage is almost constant (1.7 V) regardless of the power supply voltage. Therefore, the driving capability of MOS-FET for charging/discharging the gate capability of the subsequent inverter stage does not depend on the power supply voltage so that the delay time (t 1 −t 6 ) from the input to the output is substantially constant regardless of the power supply voltage. Thus, the access time of e.g. a memory LSI does not almost vary even in a wide power supply voltage range of 1.5 to 5 V, thus providing an LSI chip which is convenient for constructing a system.

FIGS. 22A and 22B are exemplary arrangements of the circuit for generating the bias voltage V n and V p shown in FIG. 20 A. In the figures, T 114 to T 117 the channel portion of which are indicated by thick solid lines are N channel MOS-FETs having a high threshold voltage; T 112 and T 113 are MOS-FETs for supplying a bias voltage; numeral 72 is a bias generating circuit for generating the gate voltage for T 112 and T 113 to set an optimum bias current; and C N1 and C P1 are decoupling capacitors. The value of the bias current is set by the resistance of a resistor R 30 and the ratio between T 113 and T 112 in their channel conductance. The N channel MOS-FET's having a high threshold voltage are, after their gate oxide film has been formed, for example, by introducing P type impurities through the ion injection using resist as mask. In this example, threshold voltage is set at 1 V. Further, by using the substrate structure as previously mentioned and connecting the substrate with the source, fluctuation of threshold voltage due to the body effect is removed to enhance the setting accuracy. The MOS-FETs T 112 and T 113 serve as a power supply voltage. In accordance with the above arrangement, when the power supply voltage V cc is 2 V or more, the value of V n is about twice (about 2 V) as large as the above high threshold voltage and when V cc is lower than 2 V, V n is substantially equal to V cc . Likewise, when V cc is 2 V or more, the value of V p is about V cc −2 V and when V cc is lower than 2 V, V p is substantially equal to 0 V.

FIG. 22B shows the other arrangement example of the bias voltage generating circuit. Although only the V n generating circuit is shown, V p generating circuit can be constructed in the same manner. In FIG. 22B , T 123 is an N channel MOS-FET having a high threshold voltage; T 121 is a P channel MOS-FET for supplying a bias current; T 120 and R 31 constitute a bias generating circuit for generating the gate voltage for T 121 to set an optimum bias current; C N1 is a decoupling capacitor; and R 32 and R 33 are resistors. Assuming that the threshold voltage of T 123 is V PE , V n is V TE ×(R 32 +R 33 )/R 33 . By varying the ratio of R 32 to R 33 , V n can be set at any optional value which is equal to V PE or more. Thus, the bias voltage having the characteristic as shown in FIG. 20B can be generated. Incidentally, the resistors in this example may be constituted by any of the channel of MOS-FET, the impurity diffused layer and the wiring layer of polysilicon, etc.

Meanwhile, an aging test is performed for the normal LSI circuit to assure the reliability thereof. Namely, after the final fabrication step, a higher voltage than the voltage used for the normal operation is intentionally applied to each transistor in the circuit hereby to early find out the transistor(s) which is likely to be damaged by nature due to failure of the gate oxide film, etc. FIG. 23A shows an example of the manner of providing the bias voltages V n and V p suitable to the aging test. In this example, in the power supply voltage range exceeding the point (4 V in this example) where the value relation between V n and V p is reversed, the setting V n =V p =½ V cc is made. Thus, during aging test, V p and V n are adapted to increase in proportion to the power supply voltage V cc . Further, by setting the value of V n and V p at a half value of the power supply voltage in this way, the maximum voltages applied to the respective transistors in e.g. FIG. 22C are substantially equal to each other so that stress is prevented from being concentrated to partial transistors.

FIG. 23B shows one embodiment of a circuit arrangement for generating the bias voltages V n and V p . In FIG. 23B , numeral 72 is a maximum value output circuit for comparing the voltages at two nodes N 9 and N 10 to output the maximum voltage; T 140 and T 141 are N channel MOS-FETs having a high threshold voltage; R 36 is a resistor for supplying a bias current to MOS-FETs; and R 38 and R 39 are resistors for dividing the power supply voltage V cc to provide ½ V cc and R 38 ≈R 39 . The maximum value output circuit is constituted by differential amplifier circuits A 10 and A 11 , P channel MOS-FETs T 142 and T 143 , and R 37 which is provided for preventing the impedance of a node N 11 for ground side from being infinite. The operation of the maximum value output circuit is discussed in IEEE Journal of Solid-State Circuits, Vol. 23, No. 5, pp. 1128-1132, October 1988. In operation, a substantially constant voltage (2 V in this embodiment) regardless of the power supply voltage is applied to the node N 9 whereas a voltage half as large as the power supply voltage is applied to the node N 10 . Therefore, when the power supply voltage is lower than 4 V, the maximum value i.e. 2 V between both voltages is outputted to the node N 11 whereas when the power supply voltage is higher than 4 V, ½ V cc is outputted there. The circuit for generating V p can be constructed in the same manner. Incidentally, Although in this embodiment, the voltage at the node 9 has been set at 2 V, it may be set at an optional value in accordance with the maximum applicable voltage for the gate oxide film.

Japanese Patent Application No. 63-125742 discloses a constant voltage generating circuit using a difference between MOS-FETs in their threshold voltage. FIG. 24 shows an exemplary improved arrangement of the constant voltage generating circuit, which is adapted to operate at a higher external power supply voltage than the voltage applicable to the gate oxide film. In FIG. 24 , numeral 75 is a newly provided section to that end. T 151 is an N channel MOS-FET and T 152 is a P channel MOS-FET. In accordance with this arrangement, as in the inverter previously explained, the maximum applicable voltage in any transistor in the circuit can be reduced to about half of the external power supply voltage. The value of the constant voltage generated in this circuit is, as explained in the above Japanese Patent Application No. 63-125742, V T1 (T 149 )−V T1 (T 150 ) which is a difference the threshold voltages of two N channel MOS-FETs T 149 and T 150 . T 149 is a transistor having a high threshold voltage as in FIGS. 22A and 22B . In this example, with V T1 (T 149 )=1.05 V and V T1 (T 150 )=0.03 V, and output voltage V ref =0.75 V is provided.

FIGS. 25A and 25B show an arrangement example of the differential amplifier circuit in accordance with the present invention. In the figures, T 161 and T 162 are an n channel MOS-FET to which a differential signal is supplied; T 160 is an N channel MOS-FET for supplying a bias current to the differential amplifier circuit; B 1 is a signal for setting the bias current; and T 163 and T 164 are P channel MOS-FETs, which constitute current mirror type load. In an ordinary differential amplifier circuit, nodes N 13 and N 15 are connected with each other and a node N 14 is connected with an output out 2 whereas in the differential amplifier circuit in accordance with the present example, circuit blocks indicated by 76 and 77 are provided so that it can also operate at a higher external power supply voltage than the voltage applicable to the gate oxide film. In FIG. 25A , the circuit block 76 is constituted by two N channel MOS-FETs T 165 and T 166 and a P channel MOS-FET T 167 . Thus, the maximum voltage applied to the drains (N 13 and N 14 ) of T 161 and T 162 is limited to V n −V TN1 , and the minimum voltage applied to the drain (out 2 ) T 164 is limited to V p +|V TP1 |. V TN1 and V TP1 are the threshold voltage of the N channel MOS-FET and P channel MOS-FET, respectively. Incidentally, as V p and V n , the bias voltages having the dependency on the power supply voltage as shown in FIGS. 20B and 23B may be used as they are.

Meanwhile, in the case where the differential amplifier circuit of FIG. 25A operates as a small signal amplifier circuit, i.e. there is not a large difference between two input levels and both T 161 and T 162 operate in their saturation region. The voltage at the node 14 is approximately V n −V TN1 . Therefore, even if the transistor T 167 is omitted as shown in FIG. 25B , there is not a large voltage difference between the gate and drain of T 164 . If the differential amplifier circuit is used only as a small signal amplifier, the circuit system of FIG. 26B is suitable because of its simplified construction. The signal level at the output out 2 in the differential amplifiers is equal to the signal level at the output out 2 shown in FIG. 20 A and the input in 2 can be directly driven by the output of the differential amplifier circuit so that they are conveniently combined to construct a circuit. More, specifically, in the differential amplifier circuit of FIGS. 25A and 25B , if the voltage level at the inputs In(+) and In(−) is V n −V TN1 or less, a large voltage gain can be obtained. On the contrary, if the differential amplified circuit is to be operated at an input voltage higher than V p +|V TP1 |, the P channel MOS-FETs and N channel MOS-FETs may be replaced by N channel MOS-FETs and P channel MOS-FETs, respectively so as to provide an output at a low voltage level (the signal level at the output out 1 of the inverter shown in FIG. 20 A). In this case also, the same effect can be obtained. An application of the differential amplifier circuit to an LSI chip will be explained below.

FIGS. 26A and 26B are views for explaining an application of the present invention to a circuit for generating V L (reference voltage) which is a reference for an internal power supply voltage V CL . In FIG. 26A , numeral 80 is a V L (reference voltage) generating circuit corresponding to numeral 9 in FIG. 1 ; A 15 is a differential amplifier circuit; and R 50 and R 51 are resistors for setting the amplification factor thereof. The V L generating circuit is constituted by a constant voltage (V ref ) generating circuit 81 as shown in FIG. 24 , an aging voltage (V A ) generating circuit for generating a higher voltage during an aging test than the voltage during normal operation, a maximum value output circuit 83 for comparing V ref and V A to output a larger voltage, and a switch 84 . During data retention, the voltage characteristic for the aging test is not required so that the maximum value output circuit is placed in the non-operation state and also the switch is closed to directly output V ref . In this example, with V ref =0.75 V and V A =⅕ V cc , the state for aging test is adapted to be provided when the power supply voltage is not lower than 3.75 V. More specifically, when the power supply voltage is lower than 3.75 V, V L =0.75 V is outputted and when it is not lower than 3.75 V, V L =⅕ V cc is outputted. Further, with R 50 =R 52 , the amplification factor is set at 2 so that when V cc is lower than 3.75 V, V CL =1.5 V is applied as an internal power supply voltage and when V cc is not lower than 3.75 V, V CL =⅖ V cc is applied as an internal power supply voltage.

FIG. 26B shows the dependency of the respective voltages upon the external power supply voltage V cc . In this way, as an internal power supply voltage, 1.5 V is provided for the normal operation state (e.g. V cc of 3 to 3.6 V) and 2.1 V is provided for the aging test state (e.g. V cc of 5.3 V).

FIG. 26C shows an further detailed arrangement of the V L (reference voltage) generating circuit. In FIG. 26C , numeral 90 is a maximum value output circuit and T 179 is an N channel MOS-FET serving as a switch. The maximum value output circuit 90 is constituted by two different amplifier circuits 90 a and 90 b; P channel MOS-FETs T 177 and T 178 which are driven by the outputs of the respective amplifiers; a P channel MOS-FET T 1 for relaxing the voltage applied to the gate oxide film of T 177 and T 178 ; and an N channel MOS-FET for reducing the impedance of an output terminal for the ground. The amplifier circuits 90 a and 90 b are the same as that shown in FIG. 25 A. The maximum value output circuit is also basically the same as that shown in FIG. 23 B. This arrangement provides a maximum value output circuit which operates at a higher power supply voltage than the voltage applicable to the gate oxide film. In the data retention state, the transistor T 179 is rendered conductive so that V ref is output as V L as it is, and the maximum value output circuit is placed in non-operation state to reduce consumed current.

FIG. 27A shows an arrangement of the limiter enable signal (LM) generating circuit 10 shown in FIG. 1 A. In FIG. 27A , A 12 and A 13 are single end type differential amplifiers having the same construction as that shown in FIG. 25A ; and numeral 95 is a double end type differential amplifier which has two inputs of the outputs from the differential amplifier circuits and outputs a large signal equal to a power supply voltage difference. The double end type differential amplifier circuit 95 is constituted by P channel MOS-FETs T 180 and T 181 which are driven by two inputs, respectively; P channel MOS-FETs T 184 and T 185 for relaxing the voltage applied to the gate oxide film of T 180 and T 181 ; two N channel MOS-FETs T 182 and T 183 which are cross-coupled with each other; N channel MOS-FETs T 186 and T 187 for relaxing the voltage applied to the gate oxide film of T 182 and T 183 ; and speed-up capacitors C c1 and C c2 for accelerating the inverting speed of outputs. The speed-up capacitors, which decide the response speed of the circuit, may be omitted in accordance with an application whereby the basic operation of the circuit is not injured.

The operation will be explained with reference to an operation timing chart shown in FIG. 27 B. In the following explanation, it is assumed that the internal power supply voltage V CL during normal operation is 1.5 V (V L =0.75 V). As seen from FIG. 27B , the external power supply voltage V cc is lowered from 4 V to 1 V, at the time to when half voltage of V cc crosses 0.75 V, the voltages at the outputs (nodes N 25 and N 26 ) of the differential amplifiers A 12 and A 13 are reversed. Thus, T 180 is cut off and T 181 is turned on and so the voltage at a node N 28 is increased to V cc . In synchronization with this, the potential at a node N 30 is increased to V n −V TN1 (V TN1 is the threshold voltage of T 187 ) and the potential at a node N 29 and further at a node 30 is dropped to the ground potential. Thus, the voltages at the outputs (nodes N 27 and N 28 ) in the double end type differential amplifier 95 are inverted i.e. become 0 V and V cc =1 V, respectively. Although FIG. 27B shows the operation schematically, these series of operations are actually performed in a sufficiently shorter time than the change of the power supply voltage. Therefore, the circuit operation is not badly affected by the change of the power supply voltage. Further, by intentionally providing a capacitor in the wiring of the power supply voltage, the change of the power supply voltage is controlled so that its effect on the circuit operation can be further restrained. Although the above explanation relates to the case where the external power supply voltage is decreased, the same operation is performed also in the case where it is increased.

Meanwhile, in the case where a system is to be constructed using the LSI chip in accordance with the present invention as well as the other LSI's and semiconductor devices, the input/output levels of the signals to be communicated among these components are required to be aligned with each other. The standard input/output level in the LSI operating at a single power supply (generally 5 V) includes the following two items:

(a) a TTL level, and

(b) a CMOS level.

In the case of using the TTL level, the value of a high voltage (“1”) output (V OH ) is required to be 2.4 V or more. Therefore, if the system is to be operated at the power supply voltage of 2.4 V or less, it is necessary to use the CMOS level or newly set a standard of the input/output level. If a system is to be constructed by the conventional LSI and TTL logic circuits, it is important to assure compatibility with the above input/output level. To assure the compatibility makes it unnecessary to provide level converter circuits thereby to reduce the number of components, thus leading to reduction of the production cost. Further, this improves the circuit performance such as noise resistance, operation speed, etc. and provides the most excellent performance of the system. Then, in the following description, explanation will be given for an embodiment of the present invention having an input/output circuit arrangement which can assure compatibility with the conventional input/output level. In accordance with the present invention, the following three product specifications can be realized using a single chip without changing the circuit design.

(1) In the normal operation (e.g. the power supply voltage V cc of 4.5 V-5.5 V or 3-3.6 V), and input/output is made at the TTL level. The reduction of V cc (e.g. 1.0-2.5 V) is detected as required in the chip to carry out the data retention (battery back-up).

(2) The power supply voltage V cc e.g. 1.0-5.5 V is used and an input/output is made at the CMOS level. The reduction of V cc (e.g. 1.0-5.5 V) is detected as required in the chip or an external control signal, etc. is used to carry out the data retention (battery back-up).

(3) The power supply voltage V cc of e.g. 1.0-5.5 V is used and the chip changes the input/output level in accordance with the value of the power supply voltage. For example, when V cc is 2.5-5.5 V, the input/output is made at the TTL level and when V cc is 1.0-2.5 V, the input/output is made at the CMOS level.

FIG. 28A shows an embodiment of two products of (1) and (2) in which the wirings and bondings are exchanged in a single chip and FIG. 28B shows an embodiment of the product in which the value of the power supply voltage is automatically detected to exchange the input/output level. In FIG. 28A , numeral 1 is an LSI chip; numeral 5 is an LSI circuit block operating at an internal power supply voltage (e.g. 1.5 V); PAD is an input/output pad for the TTL level; PAD is an input/output pad for the CMOS level; IB 1 and OB 1 are an input buffer and an output buffer and for the TTL level, respectively; IB 2 and OB 2 are an input buffer and output buffer for the CMOS level, respectively; SW 1 is a switch for selecting which one of the outputs from the two input buffers is to be outputted to a low voltage operating LSI circuit block; and SW 2 is a switch for selecting to which one of the two output buffers an output from the low voltage operating LSI circuit block is to be inputted.

As a technique of making these selections in an actual LSI, there is a “master slice” using wirings of aluminum, etc. In this technique, in forming wiring layers of aluminum, etc. two kinds of masks for duplicating a wiring pattern are prepared in accordance with the above switches and these masks are adopted in accordance with the product to be made. Further, with two kinds of bonding pads in accordance with the input/output levels provided on the LSI chip, the product to be made may be bonded to one of these bonding pads. Otherwise, with one bonding pad provide on the chip, the connection of the product with the input/output buffer may be changed by means of the master slice using the wiring of aluminum, etc.

FIG. 28B shows a technique of changing the input/output level of the input/output buffer in accordance with the value of a power supply voltage in which an input buffer and output buffer are provided. In FIG. 28B , PADx is an input/output pad; IB 3 and OB 3 are an input buffer and an output buffer, respectively; numeral 96 is an input/output level setting circuit for control ling the input/output level in accordance with the power supply voltage. A more concrete arrangement thereof will be described later.

By means of the arrangement mentioned above, the three product specifications can be realized on one chip. This is convenient from the point of view of the production cost and also using convenience for a user. Incidentally, although the above arrangements are directed to a so-called I/O common system in which an input and an output are made at the same terminal, the present invention may be applied to the case of only the input or output of the input/output level. In the following description, a concrete arrangement of each of the output buffer, the input buffer, and an input protection circuit will be explained. Although in the embodiments mentioned below, the circuit is constructed by MOS-FETs having a thin gate oxide film (e.g. 6.5 nm) to be used in internal circuit, the present invention may be applied to the case where the MOS-FETs having two kinds of gate oxide films in accordance with the operating voltage are provided in a single chip.

In constructing the output buffer, it is necessary to convert a signal amplitude from an internal low signal amplitude (e.g. 1.5 V) to an external high signal amplitude (e.g. 2.4 V at the TTL level and 5 V at the CMOS level when V cc is 5 V). First, a circuit arrangement providing for an output signal at the CMOS level will be explained.

FIG. 29A shows an arrangement of an amplitude converter circuit for converting an input of a low signal amplitude in 1 in an internal circuit to an output of a high signal amplitude Out. In FIG. 29A , numeral 98 is an inverter circuit as shown in FIG. 20A ; N 31 and N 32 are two inputs corresponding to in 2 and in 1 in FIG. 20A , respectively; Out is an output on inverter; T 190 is an N channel MOS-FET for driving N 32 ; T 191 is an N channel MOS-FET for limiting the maximum voltage at the node N 32 to relax the voltage applied to the gate oxide film of T 190 ; T 192 is also a P channel MOS-FET for limiting the minimum voltage at the node N 31 ; and R 65 is a resistor. The transistor T 190 and the resistor R 65 provide the inverter circuit with resistor load. Thus, an input on the low voltage side can provide two outputs on the low voltage side and on the high voltage side.

The operation of the circuit of FIG. 29A will be explained with reference to FIG. 29 B. Now it is assumed that V cc is 5 V and both bias voltages V n and V p are 2.5 V. When the input in 1 is 0 V, the transistor T 190 is cut off and the node N 31 is at a voltage level increased to V cc 5 V by the resistor R 65 . And the node N 32 is at a voltage level (2 V) lowered from V n (2.5 V) by threshold value (e.g. 0.5 V) of the transistor T 191 . Therefore, the voltage at the output of Out of the inverter 98 is 0 V. When the input in 1 is increased from 0 V to 1.5 V at the time of t 0 , the transistor T 190 becomes conductive so that the voltage level at the node N 31 is dropped to the level (3 V) higher than V p (2.5 V) by the absolute value (0.5 V) of the threshold voltage of T 192 and the voltage level at the node N 32 is dropped to 0 V. Thus, the output Out is increased to 5 V. When the input in 1 is decreased 1.5 V to 0 V at the time of t 1 , the output Out is changed 5 V to 0 V in the same manner. In this way, by means of the above circuit arrangement, an output signal amplitude of 5 V required for the output buffer can be obtained for an input signal amplitude of 1.5 V. Further, this circuit arrangement, in which a low voltage of 2.5 V or so at the maximum is applied to any transistor, performs a stabilized operation at V cc of 5 V although it is constructed by MOS-FET's with a thin gate film (e.g. 6.5 nm).

FIG. 30A shows the other arrangement of the amplitude converting circuit for converting low signal amplitudes in 1 and in 2 , which are complementary to each other, into a high signal amplitude Out, and FIG. 30B shows the operation timing thereof. In FIG. 30A , numeral 102 is a differential amplifier circuit with double end inputs and double end outputs as shown in FIG. 27A ; and numerals 100 and 101 are the same inverter as shown in FIG. 20 A. Since in the differential amplifier circuit with double end outputs, current does not flow in a normal operation state, a circuit with further reduced power consumption as compared with the circuit of FIG. 29A can be realized. Further, the substrate (back gate) of the respective transistors constituting an inverter at a final stage is biased minus (−2 V) for the N channel MOS-FETs and plus (7 V) for V cc for the P channel MOS-FETs. Thus, for example, even when an undershoot or overshoot due to impedance mismatching appears at the output, the PN junctions can be prevented from being forward biased. Therefore, prevented are the injection of minority carriers into the substrate (diffusing the minority carries into the charge storage nodes of memory cells will deteriorate the refresh characteristic), latch-up due to turn-on of parasitic thyristors, etc. Accordingly, in accordance with the present invention, a circuit for converting a low amplitude signal (e.g. 1.5 V) in an internal circuit into a high amplitude signal (e.g. 5 V) at the CMOS level.

Generally, in constructing a system, the outputs of a plurality of LSIs are connected with a data bus and only the outputs of the selected LSIs are adapted to drive the data bus. In order to carry out such a control, the output impedance of the non-selected are desired to be infinite. The conventional LSI was given by a three-output (tri-state) characteristic of driving the output level into a high voltage, a low voltage or not driving it into either voltage (the output impedance is infinite). In order to provide such a characteristic, it is necessary to perform the control of driving the output (low impedance) or not driving it (infinite impedance). The signal for this control is provided by either one of an output enable (OE) signal, a chip select (CS) signal, etc. which are externally inputted. In the output circuit, the tri-state characteristic was realized in the manner of taking a logic between that signal and an output data and driving the transistors at a final stage by the resultant signal. In the case where the same output circuit is to be constructed in accordance with the present invention, there may be proposed an arrangement in which a logic circuit is operated by a low power supply voltage and the circuit does not include the logic circuit. However, in this case, the following inconveniences will occur. The number of the stages of the amplitude converting circuits and the inverters placed between the logic circuit and the output is increased, thus for example increasing the delay time from the OE signal to the output, and generating a difference between the timing of driving the transistor on high voltage side and the transistor on the low voltage side to cause a large current to transiently flow. On the other hand, if the logic circuit can be constructed by an external power supply voltage, freedom degree of design is increased, which is preferable from the viewpoint of circuit performance. One embodiment of constructing the logic circuit by the external power supply voltage will be explained below. This logic circuit can be efficiently used as means of generating a control signal for several kinds of circuits operated by the external power supply voltage as well as the output buffer.

FIGS. 31A and 31B show an arrangement of a two-input NAND circuit in accordance with the present invention. An A input in FIG. 31A corresponds to in 1 A and in 2 A in FIG. 31B and a B input in FIG. 31A corresponds to in 1 B and in 2 B. As in in 1 and in 2 in FIG. 20A , in 1 A and in 2 A, and in 1 B and in 2 B change in their-in-phase, respectively. In FIG. 31B , transistors T 200 and T 201 are driven by the input signals in 1 A and in 1 B on the low voltage side, respectively and transistors T 202 and T 203 are driven by the input signals in 2 A and in 2 B on the high voltage side, respectively. Transistors T 204 and T 205 are provided, like T 202 and T 203 in FIG. 20A , to allow the operation at a higher voltage than the voltage applicable to the gate oxide film. By means of this arrangement, a function of the NAND gate, in which only when both inputs are at a high level, the output is at a low level, is obtained. In this way, only providing two transistors in addition to the ordinary CMOS NAND circuit permits the scaled-down transistors to be operated at a high power supply voltage. Although a two-input NAND circuit has been taken as an example, the above idea of the present invention can be also applied to, for example, an NOR circuit, an exclusive OR circuit, a composite gate in which several composite logics are outputted using outputs from plural logic circuits as inputs, and further a sequential circuit such as latch circuit and a flip-flop circuit.

FIG. 23A shows an arrangement of a tri-state output buffer using the above logic circuit. FIG. 32B shows a simplified arrangement thereof using logic symbols. In FIG. 32B , G 12 is a two-input NAND circuit; G 13 is a two-input NOR circuit; and T 210 and T 211 are an N channel MOS-FET and a P channel MOS-FET, respectively. When an output enable signal OE is at a high voltage level, the same data as an input do is provided at an output Do from the buffer, and when OE is at a low voltage level, the output Do becomes floating (substantially infinite impedance) since the gate of T 210 is fixed to a low voltage level and the gate of T 210 is fixed to a high voltage level irrespectively of the input data. FIG. 32A shows a concrete circuit arrangement having the same function as the circuit of FIG. 32B , which is constructed by the scaled-down devices (element) having a breakdown voltage lower than the external power supply voltage. In FIG. 32A , numeral 112 is a NAND circuit; numeral 113 is a NOR circuit; numeral 114 is an output circuit; and numeral 110 and 111 are the same amplitude converting circuit as numeral 102 in FIG. 30 A. The amplitude converting circuits generate signals do 2 , oe 2 and {overscore (oe 2 )} on the high power supply voltage side, which are required to operate the circuits 112 and 113 , on the basis of low amplitude signals do 1 , oe 1 and {overscore (oe 1 )} on the low power supply voltage side from an internal circuit. In this way, in accordance with the present invention, a logic circuit using scaled-down devices which operates at the external power supply voltage exceeding their breakdown voltage can be constructed, thus reducing the delay time and transient current of the tri-state output circuit, etc.

An exemplary input circuit for the CMOS level will be explained with reference to FIG. 33 . In FIG. 33 , numeral 115 is the same inverter as that shown in FIG. 20A ; T 220 and T 221 are transistors for limiting the voltage applied to the gate oxide film of transistors T 220 and T 221 to its breakdown voltage or less even when a large amplitude signal is applied to an input of the input circuit; and X is an input signal. In FIG. 33A , even when a high voltage (e.g. 5 V) is applied to the input, the voltage at a node 40 is limited to V n −V T1 (T 220 ), i.e. 2 V or so. Also, even when a low voltage is applied to the input (e.g. 0 V), the minimum voltage at a node 41 is 3 V or so. Thus, the voltage applied to the respective transistors can be deceased to approximately half of the power supply voltage. Further, one {overscore (x 1 )} of the outputs of this input circuit, the signal amplitude of which is about 2 V, can be used as it is as an internal circuit operating at a low power supply voltage.

Thus, examples of the output circuit and input circuit for CMOS level have been explained. FIG. 34A shows an example of the input circuit and output circuit in which the TTL level and CMOS level are exchanged in accordance with the value of a power supply voltage. In FIG. 34A , PAD I is an input pad; PAD O is an output pad; IPD is an input protection device for preventing a junction and a gate from being broken due to static electricity; IB 5 is an input buffer; and OB 5 is an output buffer. The input protection device will be explained in detail later. The input buffer IB 5 is constituted by two MOS-FETs T IN1 and T IP1 serving as a CMOS inverter, an N channel MOS-FET T IN2 for limiting the power supply voltage for the CMOS inverter to a predetermined value decided by a bias voltage V n1 or less, and an N channel MOS-FET T IN0 for limiting the input voltage for the CMOS inverter to a predetermined value or less. The output buffer OB 5 is constituted by an inverter 116 as shown in FIG. 20A , an amplitude conversion circuit 117 for generating driving signals d 1 and d 2 for the inverter 116 on the basis of a low amplitude signal dout, and an N channel MOS-FET T ON2 for limiting the output voltage to the predetermined value decided by the bias voltage V n1 or less. It is needless to say that as in FIGS. 32A and 32B , by taking a logic with the output enable signal, the buffer having a tri-state output characteristic can be constructed.

Meanwhile, if the value of the bias voltage V n1 is suitably varied in accordance with the power supply voltage in these circuits, input/output at the TTL level can be made for a high power supply voltage and input/output at the CMOS level can be made for a low power supply voltage. FIG. 34B shows an example of the dependancy of the bias voltage V n1 on the power supply voltage V cc . In FIG. 34B , V OL and V OH are TTL output levels corresponding to “0” and “1”, respectively, and V IL and V IH are TTL input levels corresponding to “0” and “1” respectively In an ordinary TTL logic gate, V OL =0.4 V, V OH =2.4 V, V IL =0.8 V and V IH =2.0 V. The value of the bias voltage V n is controlled to be 3 V when the power supply voltage V cc is 2.5 V or more, and controlled so that T IN0 operates in its non-saturated region when V cc is lower than 2.5 V, e.g. V cc +0.5 V.

First, the operation of the output buffer circuit OB 5 will be explained. The voltage at a node N 48 is 0 V when a low voltage (“0”) is outputted and V cc when a high voltage (“1”) is outputted. Therefore, when the low voltage is output, 0 V is output at a Dout irrespectively of V cc . On the other hand, when the high voltage is outputted, the voltage level at Dout depends on V cc as seen from FIG. 34 B. Namely, when V cc ≧3 V, it is V n1 −V T1 (T ON2 ) and when V cc <3 V, it is V cc . Thus, when V cc >3 V, the output voltage amplitude satisfying the output characteristic at the TTL level can be obtained. Incidentally, by limiting the output voltage to 2.5 V or less, the power supply current in charging/discharging large load capacitance can be minimized.

The operation of the input circuit IB 5 will be explained. The power supply voltage for the CMOS inverter constituted by T IN1 and T IP1 is supplied from the source terminal of T IN2 . The value thereof is 2.5 V when the power supply voltage V cc ≧3 V and it is 0 V when V cc <3 V. On the other hand, an input voltage for the inverter is limited to 2.5 V or less when V cc ≧3 V and the voltage input to Din is applied to the inverter as it is when V cc <3 V. By means of the circuit arrangement mentioned above, even when the power supply voltage V cc is greatly changed in a range of e.g. 1 V to 5 V, the power supply voltage for the inverter and the input signal have a substantially equal amplitude. If the channel conductances of the transistors constituting the inverter are set at a substantially equal value, the logic threshold voltage of the inverter is ½ of the power supply voltage therefor. Therefore, the logic threshold voltage when V cc ≧3 V is about 1.25 V and it is V cc /2 when V cc <3 V Thus, with the boundary of a certain voltage (3 V in this example), there can be provided an input buffer which operates at the TTL level for V cc of the certain voltage or more and operates at the CMOS level for V cc lower than the voltage.

In accordance with the present invention, LSI having a wide range of operation power supply voltage can operate an optimum input/output level for the power supply voltage used, thus realizing the maximum noise margin by minimum power consumption. Further, in the output buffer OB 5 , the three transistors T ON0 , T ON1 and T ON2 have a common substrate (back-gate). Thus, when a high voltage surge is applied to the output terminal, the charges can be swiftly discharged through a large current. This is, like the operation of a clamping MOS-FET in the input protection device described later, because when the substrate potential is increased due to breakdown, a parasitic bipolar transistor between the substrate potential and the ground potential is likely to be turned on. As a result, even when scaled-down devices are used, the static breakdown voltage can be enhanced. Moreover, although in the above embodiment, the substrate voltage V BP1 of the N channel MOS-FETs is generally set at a minus value (e.g. −3 V) so that the input voltage becomes minus (undershoot), the PN junctions are not forward biased, it may be 0 V as long as the forward current is permitted to flow. Furthermore, the N channel MOS-FETs may be formed in P substrate or may be formed in a P well electrically isolated from the P substrate as shown in FIGS. 14A and 14B . In the latter case, the resistance of the P well is lower than that of the substrate so that the parasitic bipolar transistors is likely to be turned on, thereby enhancing the static breakdown voltage.

In the embodiment mentioned above, it is necessary to generate a bias voltage V n higher than the power supply voltage. FIG. 35A shows an exemplary arrangement of the input buffer constructed without using such as bias voltage. In FIG. 35A , an input buffer IB 6 is constructed by two circuit blocks, i.e. IB 6 a and IB 6 b. IB 6 a has the same circuit arrangement as the input buffer IB 5 in FIG. 34 A. IB 6 b serves to convert the output of IB 6 a into a voltage level which is convenient to drive the internal circuit. In IB 6 b, T 231 and T 232 are MOS-FETs constituting a CMOS inverter; T 232 is a P channel MOS-FET for enhancing the potential at a node N 52 to an internal power supply voltage V CL when din is at a low level; and T 230 is an N channel MOS-FET for preventing the current from flowing Thus, when V cc >3 V, the output voltage amplitude satisfying the output characteristic at the TTL level can be obtained. Incidentally, by limiting the output voltage to 2.5 V or less, the power supply current in charging/discharging large load capacitance can be minimized.

The operation of the input buffer circuit IB 5 will be explained. The power supply voltage for the CMOS inverter constituted by T IN1 and T IP1 is supplied from the source terminal of T IN2 . The value thereof is 2.5 V when the power supply voltage V cc ≧3 V and it is 0 V when V cc <3 V. On the other hand, an input voltage for the inverter is limited to 2.5 V or less when V cc ≧3 V and the voltage input to Din is applied to the inverter as it is when V cc <3 V. By means of the circuit arrangement mentioned above, even when the power supply voltage V cc is greatly changed in a range of e.g. 1 V to 5 V, the power supply voltage for the inverter and the input signal have a substantially equal amplitude. If the channel conductances of the transistors constituting the inverter are set at a substantially equal value, the logic threshold voltage of the inverter is ½ of the power supply voltage therefor. Therefore, the logic threshold voltage when V cc ≧3 V is about 1.25 V and it is V cc /2 when V cc <3 V Thus, with the boundary of a certain voltage (3 V in this example), there can be provided an input buffer which operates at the TTL level for V cc of the certain voltage or more and operates at the CMOS level for V cc lower than that voltage.

In accordance with the present invention, LSI having a wide range of operating power supply voltage can operate an optimum input/output level for the power supply voltage used, thus realizing the maximum noise margin by minimum power consumption. Further, in the output buffer OB 5 , the three transistors T ON0 , T ON1 and T ON2 have a common substrate (back-gate). Thus, when a high voltage surge is applied to the output terminal, the charges can be swiftly discharged through a large current. This is, like the operation of a clamping MOS-FET in the input protection device described later, because when the substrate potential is increased due to breakdown, a parasitic bipolar transistor between the substrate potential and the ground potential is likely to be turned on. As a result, even when scaled-down devices are used, the static breakdown voltage can be enhanced. Moreover, although in the above embodiment, the substrate voltage V BP1 of the N channel MOS-FETs is generally set at a minus value (e.g. −3 V) so that the input voltage becomes minus (undershoot), the PN junctions are not forward biased, it may be 0 V as long as the forward current is permited to flow. Furthermore, the N channel MOS-FETs may be formed in a P substrate or may be formed in a P well electrically isolated from the P substrate as shown in FIGS. 14A and 14B . In the latter case, the resistance of the P well is lower than that of the substrate so that the parasitic bipolar transistor is likely to be turned on, thereby enhancing the static breakdown voltage.

In the embodiment mentioned above, it is necessary to generate a bias voltage V n higher than the power supply voltage. FIG. 35A shows an exemplary arrangement of the input buffer constructed without using such a bias voltage. In FIG. 35A , an input buffer IB 6 is constructed by two circuit blocks, i.e. IB 6 a and IB 6 b. IB 6 a has the same circuit arrangement as the input buffer IB 5 in FIG. 34 A. IB 6 b serves to convert the output of IB 6 a into a voltage level which is convenient to drive the internal circuit. In IB 6 b , T 231 and T 232 are MOS-FETs constituting a CMOS inverter; T 233 is a P channel MOS-FET for enhancing the potential at a node N 52 to an internal power supply voltage V CL when din is at a low voltage level; and T 230 is an N channel MOS-FET for preventing the current from flowing backward from the node N 52 to a node N 51 when the potential at the node N 52 has been increased to a high voltage level. FIG. 35B shows the dependency of the bias voltage V n2 in this circuit arrangement on the power supply voltage V cc . As seen from the figure, the bias voltage V is adapted to be 3 V (constant) when V cc ≧3 V and to be equal to V cc when V cc <3 V.

The operation of this circuit arrangement will be explained in two cases. FIG. 35C shows waveforms at the respective parts in the case where V cc is 5 V and the internal power supply voltage V CL is 1.5 V. When an input voltage Din is a low voltage (e.g. 0.4 V), the voltage at a node N 51 is V n2 −N T1 (T IN5 ) (e.g. 2.5 V) and the voltage at a node N 52 is V CL (1.5 V). Thus, a low voltage (0 V) is outputted to Din. When the input voltage Din is increased from the low voltage (e.g. 0.4 V) to a high voltage (e.g. 2.4 V), the voltage at a node N 50 follows to increase, thus dropping the voltage at the node N 51 to 0 V. The channel conductance of T 231 is set at a larger value than that of T 233 so that the voltage at the node N 52 is dropped to substantially 0 V and the value of din is increased to V CL (1.5 V). On the other hand, when the input voltage Din is decreased from the high voltage (e.g. 2.4 V) to the low voltage (e.g. 0.4 V), the voltage at the node N 50 follows to drop, thus enhancing the voltage at the node N 51 to V n2 −V T1 (T IN5 ) (e.g. 2.5 V). Thus, the voltage at the node N 52 is enhanced to V CL −V T1 (T 230 ) (e.g. 1.2 V), thus dropping din to 0 V. Accordingly, T 233 turns on and so the voltage at the node N 52 is enhanced from V CL −V T1 (T 230 ) to V CL (1.5 V). In this way, because of the feedback to the node N 52 through T 233 , the voltage amplitude at the node N 52 is equal to that of the power supply voltage V cc so that a current does not flow through the CMOS inverter constituted by T 231 and T 232 .

FIG. 35D shows waveforms at the respective parts in the case where both V cc and V CL are 1.5 V. When an input voltage Din is a low voltage (e.g. 0 V), the voltage at a node N 51 is V n2 −V T1 (T IN5 ) (e.g. 1.2 V) and the voltage at a node N 52 is V CL (1.5 V). Thus, a low voltage (0 V) is outputted to din. When the input voltage Din is increased from the low voltage (e.g. 0 V) to a high voltage (e.g. 1.5 V), the voltage at a node N 50 follows to increase to V n2 −V T1 (T IN5 ) (e.g. 1.2 V), thus dropping the voltage at the node N 51 to 0 V. The channel conductance of T 231 is set at a larger value than that of T 233 so that the voltage at the node N 52 is dropped to substantially 0 V and the value of din is increased to V CL (1.5 V). On the other hand, when the input voltage Din is decreased from the high voltage (e.g. 1.5 V) to the low voltage (e.g. 0 V), the voltage at the node N 50 follows to drop to 0 V, thus enhancing the voltage at the node N 51 to V n2 −V T1 (T IN5 ) (e.g. 1.2 V). Thus, the voltage at the node N 52 is enhanced to V CL −V T1 (T 230 ) (e.g. 1.2 V), thus dropping din to 0 V. Accordingly, T 233 turns on and so the voltage at the node N 52 is enhanced from from V CL −V T1 (T 230 ) to V CL (1.5 V). In this way, even V cc comparatively low and the output amplitude of IB 6 a is smaller than that of V cc , the voltage amplitude at the node N 52 is equal to that of V cc . Thus, a current does not flow through the CMOS inverter constituted by T 231 and T 232 . Accordingly, even if the bias voltage which is higher than the power supply voltage V cc is not used, an input/output buffer which changes an input/output level in accordance with the power supply voltage V cc can be realized.

FIG. 36A shows an arrangement of the input protection device for protecting the devices of the internal circuit from input surge in an LSI constructed by scaled-down devices. In FIG. 36A , PAD 1 is a signal input pad; numeral 120 is a first protection device for shifting high voltage surge to the ground potential using punch-through between impurity diffused layers formed in a semiconductor substrate; numeral 121 is a gate clamping device for limiting the voltage at a node N 60 to predetermined voltage or less; and R 70 is a resistor for absorbing a difference between the high voltage applied to the pad and a clamping voltage. The gate clamping device is constructed by two N channel MOS-FETs T PD1 and T PD2 connected in series and a bipolar transistor Q 1 using a parasitic device. As in the previously mentioned circuits, bias voltage V n is applied to the gate of T PD1 to prevent a voltage exceeding the breakdown voltage from being applied to the drain of T PD2 . The gate of T PD2 is connected to ground so that a current does not flow during normal operation.

The plan structure of the gate clamping device 121 is shown in FIG. 36 B and the sectional structure thereof along line A—A′ is shown in FIG. 36 C. In FIG. 36B , numerals 122 and 123 are electrically active regions which are electrically insulated from each other and formed in a semiconductor substrate; numerals 124 and 125 are gate electrodes made of silicon, respectively; numerals 126 to 130 are impurity diffused layers formed in the electrically active region or a contact hole, provided through an insulating film, for making electrical connection of the gate electrode with upper metal wiring; and numerals 131 to 134 are metal wirings made of e.g. aluminum. In FIG. 36C , numeral 50 is a thick insulating film, formed through e.g. the oxidation of the substrate, for electrically insulating the electrically active regions in the substrate from each other; numerals 139 and 140 are poly silicon constituting the gate electrode; numerals 135 to 138 are impurity diffused layers formed in the substrate in a self-aligned manner using as a mask the above insulating film or the gate electrode; and numeral 141 is a thick insulating film for electrically insulating the impurity diffused layers and the gate electrodes from the overlying metal wirings. In the structure as shown, a clamped terminal (node N 60 ) is connected with the wiring 132 , a ground terminal (V ss ) is connected with the wirings 131 and 134 , and a bias voltage V n is connected with the wiring 133 . In FIG. 36C , there are provided three NPN type parasitic transistors Q 1 a, Q 1 b and Q 1 c which use the substrate as a base. Q 1 in FIG. 36A is a representative of these transistors.

The operation of the input protection device will be explained. When the voltage applied to the node N 60 exceeds the breakdown voltage of the PN junction formed between the impurity diffused layer 136 and the substrate, the current due to the breakdown enhances the potential at the substrate (P type), thus turning on the above parasitic bipolar transistors. Thus, a large collector current flows between the diffused layers 136 and 135 (or 138 ) so as to extract charges at the node N 60 , thus clamping its potential. Since Q 1 b and Q 1 c are connected in series, their collector current is smaller than Q 1 a and so they are first effectively broken down. Therefore, the MOS-FET's turn on the parasitic transistor and thereafter the parasitic bipolar transistor Q 1 a passes the large current. In this way, if an impurity diffused layer is provided, in the neighborhood of the node N 60 , independently from the impurity diffused layers of the MOS-FETs and is grounded, the effective length between the collector and emitter of the parasitic bipolar transistor can be shortened so as to cause a large collector current to flow when the parasitic bipolar transistor operates. Also, the above arrangement of placing a grounded impurity diffused layer in the neighborhood of the terminal to be clamped may be used in an output protection device as well as in the input protection device. Further, although in the above embodiment, the gate clamping device is formed in the P substrate, it may be formed in the P well electrically separated from the substrate in such a structure as shown in FIG. 14 . Then, the resistance of the base and the P well is increased and the parasitic transistor is further likely to be turned on so that the clamping effect can be further improved. Moreover, the bias voltage of the P substrate or the P well is generally set a minus value (e.g. −3 V), it may be 0 V as long as a forward current is permitted to flow for input undershoot. Furthermore, although a p-type substrate is employed in the above embodiment, an n-type substrate may be employed as long as the clamping device is formed within the P well.

Although the details of the present invention have been explained in relation to several embodiments, the application field of the present invention should not be limited to these embodiments. For example, although the present invention has been explained mainly in relation to a memory circuit, as mentioned in the beginning of the specification, it can be also applied to a memory LSI, a logic LSI, a composite LSI by combination thereof, or the other any LSI. Further, as regards the kind of the devices (elements) to be used, the present invention can be applied to an LSI including both P and N channel MOS-FETs, an LSI including bipolar transistors, an LSI including junction FETs, a Bi-CMOS type LSI by combination of CMOS transistors and bipolar transistors, and further an LSI in which devices are formed in a substrate of the material other than Si, e.g. GaAs.

In accordance with the embodiments of the present invention as explained above, it is possible to provide an LSI which can use the characteristic of the devices fabricated by the up-to-date scaled-down processing technique, operate with low power consumption and a high speed and also perform normal operation and data retention using a battery through exchange of the operation state.

Explanation will be given for embodiments of the dynamic random access memory (DRAM) in accordance with the present invention which is suited for low voltage operation. In accordance with the embodiments mentioned below, disclosed is the DRAM which can sufficiently assure storage charges of memory cells even when an internal power supply voltage is lowered. The point of these embodiments resides in the following three items:

(1) using a half precharge system,

(2) setting the threshold voltage of the MOS-FETs constituting a CMOS sense amplifier at a value that is about one-third of the potential difference between data lines D and {overscore (D)} (hereinafter referred to as data line voltage amplitude), and

(3) boosting the potential of a memory cell signal at a higher potential using a terminal of a capacitor constituting the memory cell which is not connected with the MOS-FET for a transfer gate.

Setting the data line voltage amplitude in amplifying the memory cell signal at a small value permits the internal power supply voltage to be lowered and also the data line charging/discharging current to be greatly reduced, thus reducing power consumption. Also, though reducing the data line voltage amplitude decreases the voltage to be written from the data line into the memory cell, the memory cell signal can be increased by boosting that voltage from one terminal of the capacitor constituting the memory cell. Thus, the characteristics of data retention time, α ray-resistance soft error and S/N can be improved.

In FIG. 37A , a memory cell array MA is composed of plural data line pairs D 0 , {overscore (D0+L )} to Dn, {overscore (Dn)}, word lines W 0 to Wn, and memory cells MCs. XD is an X decoder which selects one of the plural word lines. YD is a Y decoder which selects one pair of the plural data line pairs. Y 0 is a data line selection signal line which conduct an output from the Y decoder. PD is a plate driving circuit for controlling the voltage at each of the one terminals P 0 to Pm (plates) of the capacitors each constituting the memory cell (the plate wirings P 0 -Pm are arranged correspondingly to the respective the word lines). SA 0 to SAn is a sense amplifier which amplifies the signal read from the memory cell, respectively. Numeral 1 is a signal line for conducting a data line precharge signal V DP . Numeral 2 is a signal line which conducts a data line precharge signal {overscore (φ P +L )}. Numerals 3 and 4 is a sense amplifier driving line which conducts sense amplifier driving signals φ SP and {overscore (φ SN +L )}, respectively. I/O and {overscore (I/O)} is a data input/output line which conducts the write signal in the memory cells and the read signal therefrom, respectively. Although not shown here, the data input/output lines are provided with a precharge circuit IOP and a bias circuit IOB as shown in FIG. 37 E. AMP is an output amplifier which amplifies the signal read from the memory cell to provide an output signal Dout. Dib is a data input buffer which converts an input signal (write signal) from the exterior into a signal level in the chip is a write control signal.

The read operation of the circuit shown in FIG. 37A will be explained with reference to a waveform chart shown in FIG. 37 B. It should be noted that for convenience of explanation, an example of the voltage value of each waveform is illustrated.

While the data line precharge signal {overscore (φ P +L )} is at a high potential level (4 V), the data lines D 0 , {overscore (D0+L )} (Dn, {overscore (Dn)}) are at a precharge potential (1 V). Then, the sense amplifier driving signals φ SP , {overscore (φ SN +L )} are 1 V and the sense amplifier is in an OFF state. After {overscore (φ P +L )} has been changed to a low potential level (0 V), one of the word lines is selected. Now it is assumed that the word line W 0 has been selected. When W 0 is changed from a low potential level (0 V) to a high potential level (4 V), a memory cell signal appears at each data line. Now it is assumed that the memory cells connected with the data lines D 0 , Dn have stored a signal at a high potential level. Therefore, the potential at the data line Do (Dn) becomes slightly higher than that at the data line {overscore (D0+L )} ({overscore (Dn)}). Next, when φ sp is changed from 1 V to 2 V, and φ SN is changed from 1 V to 0 V, the sense amplifiers SAo to SAn operate to amplify the memory signals. Thus, the data line D 0 becomes 2 V and the data line {overscore (D0+L )} becomes 0 V. Thereafter, a pair of the data lines is selected by the Y decoder YD. It is now assumed that D 0 and {overscore (D0+L )} are selected. Thus, the potential at the data line selection line Y 0 becomes high (4 V) so that the memory cell signal is read out to the data input/output lines I/O and {overscore (I/O)}. This signal is amplified by the output amplifier AMP to provide the Dout.

The rewrite operation of a signal into a memory cell will be explained. After the sense amplifier has been operated, the potential at a storage terminal 10 , which is one terminal of the capacitor constituting a memory cell, is 2 V like D 0 (case where the potential at the terminal is at a high potential). Then, the potential at the plate P 0 is changed from 4 V to 0 V. However, the potential on the word line W 0 is 4 V so that the potential on the data line and at the storage terminal are held by the sense amplifier. Thereafter, the potential on the word line W 0 is lowered from 4 V to 2 V. Then, assuming that the threshold voltage of a transistor constituting the memory cell is 1 V, both potentials of at the storage terminal and on the data line D 0 are 2 V so that the transistor T 0 is in an OFF state. Therefore, when the potential on the plate P 0 is changed from 0 V to 4 V, the potential at the storage terminal is enhanced from 2 V to about 6 V. Thus, 6 V is written in the memory cell.

On the other hand, the rewrite operation in the case where a signal at a low potential has been stored in the memory will be explained with reference to the waveform in the case where the terminal 10 in FIG. 37B is at a low potential. After the sense amplifier has been operated, both potentials on the data line D 0 and at the storage terminal 10 are 0 V. Therefore, even if the potential on the word line W 0 is subsequently lowered from 4 V to 0 V, the transistor T 0 constituting the memory cell is an ON state. Thus, even if the potential at the plate P 0 is subsequently changed from 0 V to 4 V, the potential at the storage terminal 10 is held 0 V. Accordingly, 0 V is written in the memory cell.

Thereafter, the potential on the word line W 0 becomes 0 V to complete the rewrite operation. Subsequently, φ SP and {overscore (φ SN +L )} become 1 V. Further, φ P becomes 4 V to precharge the data line to 1 V.

The write operation in the circuit shown in FIG. 37A will be explained with reference to the waveform chart of FIG. 37 C. After memory cell signals have been amplified by the sense amplifiers as in the read operation, a write signal Din (not shown in FIG. 37C ) is fetched into a data input buffer DiB. When a write control signal φ W (not shown in FIG. 37C ) becomes 4 V, the potentials on the input/output lines I/O and {overscore (I/O)} are separated into a high potential and a low potential in accordance with Din. It is now assumed that I/O and {overscore (I/O)} have become 0 V and 2 V, respectively. Thereafter, a pair of data lines are selected by the Y decoder YD. It is now assumed that D 0 and {overscore (D0+L )} have been selected. Thus, the potential on the data line selection line Y O becomes 4 V so that D 0 and {overscore (D0+L )} become 2 V and 0 V, respectively. Accordingly, a low potential of 0 V is written at the storage terminal 10 of the memory cell (see the waveform in the case where the terminal 10 is rewritten from the high potential to the low potential).

On the other hand, the operation of writing a high potential signal in the memory in which a low potential signal has been stored in the memory is as follows. After the sense amplifier has been operated, the potentials on D 0 and {overscore (D0+L )} are 0 V and 2 V, respectively. The potentials on I/O and {overscore (I/O)} are 2 V and 0 V, respectively, in accordance with Din. Thereafter, the potential on Y 0 is enhanced to 4 V so that the potentials on D 0 and {overscore (D0+L )} are 2 V and 0 V. Accordingly, the high potential of 2 V is written at the storage terminal of the memory cell (see the waveform in the case where the terminal 10 is rewritten from the low potential to high potential).

The operation after the signal has been written in the memory cell in the above manner is the same as the read operation as previously mentioned. Namely, the high potential signal in the memory cell is boosted and stored at about 6 V whereas the low potential is stored at 0 V.

As explained above, in accordance with this embodiment, the voltage amplitude of the data lines and that of the voltage to be written into the memory cells can be determined independently from each other. Therefore, by decreasing the voltage amplitude of the data lines, which affects the power consumption of the memory, and also increasing the voltage amplitude of the plates, which is relative to memory cell signals, reduced power consumption and increased S/N of the memory can be simultaneously realized. In this embodiment, the voltage amplitude of the plate is set to be larger than that of the data lines. In this way, most of the memory cells signals can be stored through the plates so that the voltage amplitude of the data lines can be decreased to the neighborhood of the operation limit of the sense amplifiers. Thus, the power consumption can be remarkably reduced while assuring a sufficient signal voltage for the memory cells. In this embodiment, the potential on the data lines during its precharge is set at an intermediate value between the high and low potentials of the voltage amplitude of the data lines. This permits the power consumption to be further reduced.

Further, although the amplitude of the data line voltage can be decreased to the neighborhood of the threshold voltage of the MOS-FETs constituting the sense amplifier, it is desired to be slightly larger than a sum of the absolute values of the respective threshold values of N channel MOS-FETs and P channel MOS-FETs which constitute the sense amplifier. This will be explained with reference to FIG. 37 D. FIG. 37D shows the charging/discharging time of the sense amplifier when the amplitude of the data line voltage is set at 0.5 V, 1.0 V, 1.5 V and 2.0 V. Three kinds of threshold voltages of 0.2 V, 0.35 V and 0.5 V in the MOS-FETs are used as parameter, t r represents a charging time (raising-up time) and t f represents a discharging time (falling-down time). As seen from the figure, unless the threshold voltage is one-third of the voltage amplitude of the data line or less, excess time is required for charging/discharging. Particularly, the charging time in the case of the data line voltage amplitude of 0.5 V and the threshold voltage of 0.2 V, which is close to 60 ns, is considered to a limit to be actually adopted in the DRAM.

With respect to power consumption, the charging/discharging current in the case of the data line voltage amplitude of 2 V can be decreased to {fraction (1/2.5)} of the case of 5 V assuming that the respective threshold voltage of the N channel MOS-FETs and the P channel MOS-FETs are 0.7 V and −0.7 V. Incidentally, the power consumption may be increased due to driving the plates. But, in an array of 256 words lines * 1024 data pair lines, the capacitance charged at one time is 15 to 30 pF for plates, which is negligibly small whereas it is 200 to 300 pF for the data lines.

In accordance with this embodiment, the voltage amplitude of the data lines can be decreased while assuring a sufficient voltage to be written into the memory cells so that low power consumption and high S/N in the memory can be simultaneously realized. Additionally, if the plate potential is set at an intermediate value between two potentials of the memory cells during the stand-by of the memory as shown in FIGS. 37B and 37C , an electric field applied to the capacitor constituting the memory cell can be decreased, thus improving the reliability of the capacitor.

Further, in accordance with this embodiment, the signal stored in the memory cell is larger on the high potential side than on the low potential side. Since the memory cell signal on the high potential side is required to be large in order to increase the margin for data retention time and ray soft error, in accordance with this embodiment, a memory with large margin for them can be provided.

Another embodiment of the present invention will be explained with reference to FIGS. 39A and 38B . In this embodiment, the voltage amplitudes of both data line and plate are set at the same value. The other operation and circuit arrangement are the same as the embodiment shown in FIG. 37 A. FIG. 38A shows the read operation of the memory and FIG. 39B shows the write operation thereof. In this embodiment, the voltage amplitudes of both data line and plate are set at the same value and the plate potential during the stand-by time of the memory is set at an intermediate value two storage potentials in the memory cell. Therefore, the voltage applied to the capacitor of the memory cell is the same in both cases where the potential of the signal to be stored in the memory cell is a high level and a low level, which can improve the reliability of the capacitor.

FIGS. 39A and 39B show an embodiment of the memory cell array in the case where a plate wiring is arranged for each word line. FIG. 39A shows the equivalent circuit thereof and FIG. 39B shows the plan structure thereof. The conventional memory cell is disclosed in e.g. ISSCC86, Digest of Technical Papers, p. 263 and ISSCC85. Digest of Technical Papers, P. 245. In the memory cell array using these memory cells, the plate is not separated for each word line. On the other hand, in this embodiment, as seen from FIG. 39B , the plate is separated for each word line on the basis of the conventional memory cell. In FIG. 39B , numeral 1 is an n + diffused layer which serves as the source (drain) terminal of the transistor of a memory cell and is connected with a data line through a through-hole 4 (although the data line is not shown here for simplicity of the illustration, using an aluminum layer, it may be provided perpendicularly to a word line). Numeral 2 is a plate of a first poly-silicon layer which is separated for each word line as seen from the figure. 5 is a capacitor portion. Numeral 3 is a word line of second poly-silicon layer. Numeral 6 is a transistor portion. As seen from the arrangement shown in FIG. 39B , if the plate is provided for each word line, certain space is required between the plates, thereby increasing the memory chip size. Next, a system of commonly using a plate for plural word lines will be explained.

Another embodiment of the present invention will be explained with reference to FIGS. 40A , 40 B and 40 C. The memory constitution shown in FIG. 40A is the same as that of FIG. 37A except the plate line constitution. Whereas in the embodiment of FIG. 37A , a plate is provided for each word line, in this embodiment, one plate is commonly provided for two word lines. Then, there are some memory cells in which the plate potential varies among the memory cells connected with the non-selected word line so that contrivance will be made for potential relations.

The read operation of the circuit shown in FIG. 40A will be explained with reference to a waveform chart shown in FIG. 40 B.

While the data line precharge signal {overscore (φ P +L )} (not shown in FIG. 40B ) is at a high potential level, the data lines D 0 , {overscore (D0+L )} (Dn, {overscore (Dn)}) are precharged at 4 V. Then, the sense amplifier driving signals φ SP , {overscore (φ SN +L )} are 4 V and so the sense amplifier is in an OFF state. After φ P has ben changed to 0 V, one of the word lines is selected. Now it is assumed that the word line W 0 has been selected. When W 0 is changed from 0 V to 7 V, a memory cell signal appears on each data line. Now it is assumed that the memory cells connected with the data lines D 0 , Dn have stored a signal at a high potential level. Therefore, the potential at the data line D 0 (Dn) becomes slightly higher than that at the data line {overscore (D0+L )} ({overscore (Dn)}). Next, when φ sp is changed from 4 V to 5 V, and {overscore (φ SN +L )} is changed from 4 V to 3 V, the sense amplifiers SAo to SAn operate to amplify the memory signals. Thus, the data line D 0 becomes 5 V and the data line {overscore (D0+L )} becomes 3 V. Thereafter, a pair of the data lines is selected by the Y decoder YD. It is now assumed that D 0 and {overscore (D0+L )} are selected. Thus, the potential at the data line selection line Y 0 (not shown in FIG. 40B ) becomes high so that the memory cell signal is read out on the data input/output lines I/O and {overscore (I/O)} (not shown in FIG. 40 B). This signal is amplified by the output amplifier AMP to provide the Dout (not shown in FIG. 40 B).

The rewrite operation of a signal into a memory cell will be explained. After the sense amplifier has been operated, D 0 is at a high potential of 5 V and {overscore (D0+L )} is a low potential of 3 V. Then, the storage terminal 10 of the memory cell is at the high-potential of 5 V like D 0 (case where the potential at the terminal is at a high potential in FIG. 40 B). Then, the potential at the plate P 0 ′ is changed from 6 V to 3 V. However, the potential on the word line W 0 is 4 V so that the potential on the data line and at the storage terminal are held by the sense amplifier and not varied. Thereafter, the potential on the word line W 0 is lowered from 7 V to 5 V. Then, assuming that the threshold voltage of a transistor constituting the memory cell is 1 V, both potentials of at the storage terminal 10 and on the data line D 0 are 5 V so that the transistor T 0 is in an OFF state. Therefore, when the potential on the plate P 0 ′ is changed from 3 V to 6 V, the potential at the storage terminal is enhanced from 5 V to about 8 V. Thus, the high potential about 8 V is written in the memory cell.

On the other hand, the rewrite operation in the case where a signal at a low potential has been stored in the memory will be explained with reference to the waveform in the case where the terminal 10 in FIG. 40B is at a low potential. After the sense amplifier has been operated, both potentials on the data line D 0 and at the storage terminal 10 are 3 V. Therefore, even if the potential on the word line W 0 is subsequently lowered from 7 V to 5 V, the transistor T 0 constituting the memory cell is an ON state. Thus, even if the potential at the plate P 0 ′ is subsequently changed from 3 V to 6 V, the potential at the storage terminal 10 is held 3 V. Accordingly, the low potential of 3 V is rewritten in the memory cell.

Meanwhile, in this embodiment, the plate of the memory cell connected with a non-selected word line is varied in its potential. Then, the behavior of a storage terminal 11 of the memory cells connected with a non-selected word line W 1 will be explained. The operation in the case where a high potential has been stored at the storage terminal 11 is as follows. During the stand-by time of the memory; the plate P 0 ′ is at 6 V and the storage terminal 11 is at 8 V. After the sense amplifier has amplified the memory signal, P 0 becomes 3 V and then the storage terminal becomes 5 V. Then, the word line W 1 becomes 0 V and the data line {overscore (O0+L )} becomes 3 V or 5 V so that a transistor T 1 is never in the ON state and so the signal in the memory cell is not destroyed. Thereafter, the plate P 0 ′ becomes 0 V and the storage terminal 11 returns to 8 V.

The operation in the case where a low potential has been stored at the storage terminal 11 is as follows. During the stand-by time of the memory, the plate P 0 ′ is at 6 V and the storage terminal 11 is at 3 V. After the sense amplifier has amplified the memory signal, P 0 ′ becomes 3 and then the storage terminal 11 becomes 0 V. Then, the word line W 1 becomes 0 V and the data line {overscore (O0+L )} becomes 3 V or 5 V so that a transistor T 1 is never in the ON state and so the signal in the memory cell is not destroyed. Thereafter, the plate P 0 becomes 6 V and the storage terminal 11 returns to 3 V.

Thereafter, the potential on the word line W 0 becomes 0 V to complete the rewrite operation. Subsequently, φ SP and {overscore (φ SN +L )} become 4 V. {overscore (φ P +L )} becomes the high potential to precharge the data line to 4 V.

In this way, if the plate voltage amplitude (6−3=3 V) is equal to the low potential level of the data line, the lowest potential of the storage terminal 11 is 0 V. Therefore, the transistor T 1 is never turned on.

The write operation in the circuit shown in FIG. 40A will be explained with reference to the waveform chart of FIG. 40 C. After memory cell signals have been amplified by the sense amplifiers as in the read operation, a write signal Din is fetched into a data input buffer DiB. When a write control signal φ W (not shown in FIG. 40C ) becomes a high potential, the potentials on the input/output lines I/O and {overscore (I/O)} are separated into a high potential and a low potential in accordance with Din. It is now assumed that I/O and {overscore (I/O)} have become 3 V and 5 V, respectively. Thereafter, a pair of data lines are selected by the Y decoder YD. It is now assumed that D 0 and {overscore (D0+L )} have been selected. Thus, the potential on the data line selection line Y 0 becomes 4 V so that D 0 and {overscore (D0+L )} become 5 V and 3 V, respectively. Accordingly, a low potential of 3 V is written at the storage terminal 10 of the memory cell (see the waveform in the case where the terminal 10 is rewritten from the high potential to the low potential).

On the other hand, the operation of writing a high potential signal in the memory in which a low potential has been stored in the memory is as follows. After the sense amplifier has been operated, the potentials on D 0 and {overscore (D0+L )} are 3 V and 5 V, respectively. The potentials on I/O and {overscore (I/O)} are 5 V and 3 V, respectively, in accordance with Din. Thereafter, the potential on Y 0 is enhanced to 6 V so that the potentials on D 0 and {overscore (D0+L )} are 5 V and 3 V. Accordingly, the high potential of 5 V is written at the storage terminal of the memory cell (see the waveform in the case where the terminal 10 is rewritten from the low potential to high potential.

The operation after the signal has been written in the memory cell in the above manner is the same as the read operation as previously mentioned. Namely, the high potential signal in the memory cell is boosted and stored at about 8 V whereas the low potential is stored at 3 V.

As mentioned above, in accordance with this embodiment, the data line voltage amplitude during the operation of the sense amplifier is decreased so that the charging/discharging current of the data line can be decreased, thus reducing the power consumption. Further, a sufficiently large voltage is written into the memory cell through the plate so that the characteristics of data retention time and α ray soft error resistance can be improved. Moreover, one plate is commonly used for two word lines so that space is not required between the plates, thus reducing the memory chip size. Incidentally, in the case where one plate is commonly used for plural word lines, if the low potential of the data line is set at a higher level than the low potential of the word line by a plate voltage amplitude or more, the signal in the memory cell connected with the non-selected word line is never destroyed.

A still another embodiment of the present invention will be explained with reference to FIGS. 41A and 41B .

In this embodiment, the voltage amplitudes of both data line and plate are set at the same value. The other operation and circuit arrangement are the same as the embodiment shown in FIG. 40 A. FIG. 41A shows the read operation of the memory and FIG. 41B shows the write operation thereof. In this embodiment, the voltage amplitudes of both data line and plate are set at the same value and the plate potential during the stand-by time of the memory is set at an intermediate value two storage potentials in the memory cell. Therefore, the voltage applied to the capacitor of the memory cell is the same in both cases where the potential of the signal to be stored in the memory cell is a high level and a low level, which can improve the reliability of the capacitor.

FIG. 42 shows an embodiment of the memory cell arrangement in the case where one plate in commonly provided for two word lines. In FIG. 42 , numeral 1 is an n + diffused layer which serves as the source (drain) terminal of the transistor of a memory cell and is connected with a data line through a through-hole 4 (although the data line is not shown here for simplicity of the illustration, using an aluminum layer, it may be provided perpendicularly to a word line). Numeral 2 is a plate of a first poly-silicon layer which is commonly provided for two word lines as seen from FIG. 42 . Numeral 3 is a word line of a second poly-silicon layer. By commonly providing one plate for two word lines in accordance with this embodiment, the number of spaces between the plates can be decreased, thus reducing the memory chip size.

FIG. 43 shows an embodiment of the memory cell arrangement in the case where one plate is commonly provided for four word lines. In accordance with this embodiment, the number of spaces between the plates can be further decreased, thus further reducing the memory chip size. In FIG. 43 , like reference numerals refer to like elements in FIG. 42 .

Meanwhile, it should be noted that in the embodiments mentioned above, the plate is made of a poly-silicon layer. The poly-silicon layer has a larger resistance than a metallic layer of e.g. aluminium so that the rising time and falling time in pulse-driving the plate are very long. This increases the operation cycle time of a memory and hence the use efficiency. In order to obviate such a disadvantage, it is proposed to shunt the plate by an aluminium (Al) wiring. This will be explained with reference to FIGS. 44A and 44B . In a memory array MA shown in FIG. 44A , the plate is divided into two plate sections PL 1 and PL 2 , which are shunted by plate wirings P 0 and P 1 of Al layers, respectively. This shunting is made at the end portions of the plate section as shown in FIG. 44 B. In FIG. 44B , numeral 2 is the plate section of a poly-silicon layer and numeral 6 is the plate wiring of an Al layer; they are connected with each other through a through-hole 5 . In this way, shunting the plate of a poly-silicon layer by the plate wiring of an Al layer permits the driving speed for the plate to be increased.

FIG. 45 shows an embodiment of the memory cell arrangement in the case where a plate (wiring) is provided for each word line. In FIG. 45 , numeral 1 is an n diffused layer which serves as the source (drain) terminal of the transistor of a memory cell and is connected with a data line through a through-hole 4 (although the data line is not shown here for simplicity of the illustration, using an aluminium layer, it may be provided perpendicularly to a word line as in the embodiments mentioned above). Numeral 2 is a plate of a first poly-silicon layer which is provided for each word line. Numeral 3 is a word line of a second poly-silicon layer.

Two data line arrangements are proposed for the memory cell arrangement of FIG. 45 A. One is an open-type data line (bit line) arrangement and the other is a two-cell/bit type data line arrangement. FIG. 45B shows the open-type data line arrangement in which neighboring data lines are connected with different sense amplifiers. FIG. 45C shows the two-cell/bit type data line arrangement in which neighboring data lines are connected with the same sense amplifier. In the latter arrangement, if one word line is selected, memory cells connected with the data lines to be a pair are selected. This means a one-bit two-cell memory cell array which provides memory cell signals, at the data lines, twice those in the one-bit one-cell memory cell array of FIG. 45 B.

A further embodiment of the present invention will be explained with reference to FIG. 46 . FIG. 46 shows the operation waveforms representing a plate driving system which is different from that in the memory circuit shown in FIG. 40 A. In. FIG. 46A , the read operation of an output signal Dout is the same as that in FIG. 41A but the rewrite operation is different from that in FIG. 41 A.

The rewrite operation is performed as follows. After the sense amplifier has been operated. D 0 is at a high potential of 4 V and {overscore (D0+L )} is a low potential of 2 V. Then, the storage terminal 10 of the memory cell is at the high potential of 4 V like D 0 (case where the terminal 10 is at a high potential in FIG. 46 ). Then, the potential at the plate P 0 is changed from 5 V to 4 V. Then, assuming that the threshold voltage of a transistor constituting the memory cell is 1 V, both potentials of at the storage terminal 10 and on the data line D 0 are 4 V so that the transistor T 0 is in an OFF state. Therefore, when the potential on the plate P 0 ′ is changed from 2 V to 4 V, the potential at the storage terminal is enhanced from 4 V to about 6 V.

On the other hand, the rewrite operation in the case where a signal at a low potential has been stored in the memory is as follows. After the sense amplifier has been operated, both potentials on the data line D 0 and at the storage terminal 10 are 2 V. Therefore, even if the potential on the word line W 0 is subsequently lowered to 5 V, the transistor T 0 constituting the memory cell is an ON state. Thus, even if the potential at the plate P 0 ′ is subsequently changed from 2 V to 4 V, the potential at the storage terminal 10 is held 2 V. Thereafter, after the word line W 0 has become 0 V, the plate P′ is changed from 4 V to 2 V. Thus, the potential at the storage terminal 10 is changed from about 6 V to 4 V when a high potential has been stored at the terminal, whereas it is changed from 2 V to 0 V when a low potential has been stored there. Accordingly, stored in the memory cell is 4 V on the high potential side and is 0 V on the low potential side.

Next, the behavior of a storage terminal 11 of the memory cells connected with a non-selected word line W 1 will be explained. The operation in the case where a high potential has been stored at the storage terminal 11 is as follows. During the stand-by time of the memory, the plate P 0 is at 2 V and the storage terminal 11 is at 4 V. After the sense amplifier has amplified the memory signal, P 0 ′ becomes 3 V and then the storage terminal becomes about 6 V. Then, the word line W 1 becomes 0 V and the data line becomes 3 V or more so that a transistor T 1 is never in the ON state and so the-signal in the memory cell is not destroyed. Thereafter, the plate P 0 ′ becomes 2 V and the storage terminal 11 returns to 4 V.

The operation in the case where a low potential has been stored at the storage terminal 11 is as follows. During the stand-by time of the memory, the plate P 0 ′ is at 2 V and the storage terminal 11 is at 0 V. After the sense amplifier has amplified the memory signal, P 0 ′ becomes 4 V and then the storage terminal becomes about 2 V. Then, the word line W 1 becomes 2 V and the data line becomes 2 V or more so that a transistor T 1 is never in the ON state and so the signal in the memory cell is not destroyed. Thereafter, the plate P 0 ′ becomes 2 V and the storage terminal 11 returns to 0 V.

Also in accordance with this embodiment, the voltage amplitude of the data lines can be decreased so that reduced power consumption of a memory chip can be realized. Further, in this embodiment, the memory cell signal on the low potential side can be made larger than that on the high potential side.

A further embodiment of the present invention will be explained. FIG. 47 shows the connection between the data lines and I/O lines in the memory circuit (the remaining circuit arrangement is the same as that of FIG. 40 A). The circuit of FIG. 47 serves to receive the signals on data lines D 0 , {overscore (D0+L )} by the gates of MOS-FETs T 2 and T 3 and conduct them as drain currents to data input/output lines I/O, {overscore (I/O)}. In order to increase the signals conducted to the data input/output lines, it is important to use T 2 and T 3 in the range of a large g m . In the embodiment of FIG. 40A and 40B , the potential of the data line is set at a high level so that T 2 and T 3 are operated in the high g m range, thus increasing the signals conducted to the input/output lines. Thus, the memory operated with a raised potential of the data lines can realize its high S/N through the circuit of this embodiment.

A further embodiment of the present invention will be explained with reference to FIG. 48 . In this embodiment, the voltage of the data lines is binary. The other operation and circuit arrangement are the same as those of FIG. 37 A. In operation, while a data line precharge signal {overscore (φ P +L )} is 4 V, the data lines are precharged to 1 V. After p has become 0 V, the word line W 0 is raised to 2 V+Vt (Vt is the threshold voltage of MOS-FET). Thus, a memory cell signal is read out to the data lines. Next, the sense amplifier driving signal φ sp varies from 1 V to 2 V and the same amplifier signal {overscore (φ SN +L )} varies from 1 V to 0 V, thus amplifying the memory signal read out. Now it is assumed that the signal at a high potential has been stored in the memory cells connected with the word line W 0 . Then, the data line D 0 (Dn) becomes 2 V and the data line D 0 (Dn) becomes 0 V. Also, the word line W 0 is 2 V+Vt, the data line D 0 is 2 V and the storage terminal 10 so that the transistor T 0 constituting the memory cell connected with the data line D 0 is turned off. Next, when the potential at the plate P 0 is lowered from 4 V to 0 V, the potential at the terminal 10 is slightly lowered, thus turning on the transistor T 0 . The potential 2 V at the terminal 10 is held in the sense amplifier. Thereafter, when the potential at the plate P 0 is boosted from 0 V to 4 V, the transistor T 0 is turned off, thus raising the potential at the terminal to about 6 V.

On the other hand, the operation in the case where a signal at a low potential has been stored in the memory cells is as follows (see the waveform in the case where the terminal 10 is at a low potential in FIG. 48 ). After the memory cell signal has been amplified by the sense amplifier, the data line D 0 is at 0 V, the storage terminal 10 is at 0 V and the word line W 0 is at 2 V+Vt so that the transistor T 0 constituting the memory cell is turned on. Therefore, even when the potential at the plate P 0 varies from 4 V to 0 V or from 0 to 4 V, the potential at the terminal 10 is held 0 V.

After the signal has been stored in the memory cell in the above manner, the word line becomes 0 V. Subsequently, φ p becomes 4 V and φ sp , and {overscore (φ SN +L )} become 1 V, thus precharging the data lines to 1 V.

As mentioned above, in accordance with this embodiment, the same operation as the embodiment of FIG. 37A can be performed even when the word voltage is binary. This simplifies the control circuit and so makes easy the designing thereof.

Meanwhile, in the memory in accordance with the present invention, as understood from the embodiment shown in FIGS. 37A and 37B , the voltage in a memory cell is larger on the high potential signal side than on the low potential signal side. For example, assuming that the voltage amplitude of a data line is V d and that of a plate is V p , the voltage stored in the memory cell is ½ V d +V p on the high potential signal side and ½ V d on the low potential side. Therefore, if the memory cell signal is read to the data lines with the potential on the word line being high, the low potential signal is too small so that sufficient noise margin may not assured. In order to obviate such a disadvantage, it is proposed to increase the low potential signal using capacitive coupling as explained with reference to FIGS. 47A and 47B .

The embodiment shown in FIG. 49A is different from the embodiment shown in FIG. 37A only in that dummy word line WD 0 , WD 1 are provided and a capacitor is provided between each of the dummy word lines and each of the data lines. Other circuit constitution and operation are the same as those of the embodiment shown in FIG. 37 A. The read operation of a memory cell signal in the circuit of FIG. 49A will be explained with reference to the operation waveform shown in FIG. 49B , in which the voltage waveforms on the data line in reading both low potential and high potential are illustrated. The low potential read is performed as follows. When a selected word line W 0 is boosted to a high potential of 4 V, the memory cell signal appearing on the data line D 0 is slightly lower than the precharge voltage of 1 V. Then, a dummy word line WD 0 is boosted from a low potential of 1 V to a high potential of 4 V. This potential change is conducted to the data line D 0 through the capacitor. Thus, the potential on the data line becomes higher than the precharge voltage of 1 V by ΔV. In this way, the signal voltage in reading the low potential is increased so that sufficiently large noise margin can be assured. Incidentally, the value of ΔV can be set at an optional value by adjusting the capacitance of the capacitor and the voltage amplitude of the dummy word line, thus making it easy to control the noise margin. On the other hand, if a high potential has been stored in the memory cell, the read memory cell signal is reduced by ΔV. However, this signal is originally high so that this reduction of ΔV does not W m is selected, a dummy word line WD 1 is boosted from completely eliminate. Incidentally, when a word line the low potential to the high potential.

FIG. 50A shows an exemplary circuit for generating sense amplifier driving signals φ sp and {overscore (φ SN +L )}. In FIG. 50A , A 1 is a differential amplifier circuit which decides the high potential level of φ sp together with a transistor T 211 and resistors R 211 and Vr 1 . A 2 is also a differential amplifier circuit which decides the low potential level of {overscore (φ SN +L )} together with a transistor T 212 and resistors R 212 and Vr 2 . The operation of the circuit of FIG. 50B will be explained with reference to the operation waveform shown in FIG. 50 . While {overscore (φ 1 +L )} is 5 V, transistors T 261 . T 262 and T 263 are in the ON state thereby to place φ sp and {overscore (φ SN +L )} at 3 V. Then, φ 2 is 5 V and φ 3 is 0 V so that transistors T 22 and T 24 are in the OFF state. After {overscore (φ 1 +L )} has become 0 V, φ 2 becomes 0 V and φ 3 becomes 5 V. Thus, φ sp becomes 4 V which is the same potential as that at the resistor Vr 1 and {overscore (φ SN +L )} becomes 2 V which is the same potential as that at the resistor Vr 2 . Thereafter, φ 2 becomes 5 V and φ 3 becomes 0 V so that the transistors T 22 and T 24 are turned off. Next, {overscore (φ 1 +L )} becomes 5 V so that the transistors T 261 , T 262 and T 263 are turned on thereby to place φ sp and {overscore (φ SN +L )} at 3 V.

As understood from the above description, in accordance with the circuit shown in FIG. 50A , the high potential level of φ sp and the low potential level of {overscore (φ SN +L )} can be optionally decided.

FIG. 51A shows an exemplary circuit for generating a word line voltage. In FIG. 51A , numeral 33 is a word line; numeral 36 is an X decoder; and numeral 34 is an address signal line. A 3 is a differential amplifier circuit which serves to decide the intermediate potential level of a word line voltage together with a transistor T 30 and resistors R 30 and Vr 3 . The operation of the circuit of FIG. 51A will be explained with reference to the operation waveform shown in FIG. 51 B. During the stand-by time of a memory, an output terminal (node) 35 is at a high potential level of 5 V/ Then, a signal φ 4 is at a low potential level of 0 V. Therefore, transistors T 311 and T 352 are in the ON state while transistors T 312 and T 351 are OFF state. Thus, the voltage of the word line W 0 becomes 0 V. When the word line is selected, the potential of the terminal 35 becomes 0 V. Then, the transistor T 351 is turned on and the transistor T 352 is turned off so that the voltage of the word line is boosted to 5 V. Next, when φ 4 has becomes 5 V, the transistor T 311 is turned off and the transistor T 312 is turned on so that the voltage of the word line becomes 4 V like the resistor Vr 3 . Thereafter, when the potential at the terminal 35 has become 5 V, the voltage of the word line becomes 0 V.

In this way, three value levels of the word line voltage can be provided by means of the circuit as shown in FIG. 51 A.

An embodiment of another read operation for the circuit shown in FIG. 37A will be explained with reference to the operation waveforms as shown in FIG. 52A in which only one example of the voltage of each of the operation waveforms is illustrated for convenience of explanation.

While the data precharge signal {overscore (φ D +L )} is 4 V, the data lines D 0 , {overscore (D0+L )} (Dn, {overscore (Dn)}) are at a precharge potential level of 1 V. Then, the sense amplifier driving signals φ sp and {overscore (φ SN +L )}, are 1 V and the sense amplifiers SA 0 to SAn are in the OFF state. It is assumed that after {overscore (φ p +L )} has become 0 V, a plate (wiring) P 0 is selected from a plural plate wirings. When P 0 varies from 4 V to 0 V, a memory cell signal appears on each data line. Now it is assumed that a signal at a low potential of 0 V has been stored in the memory cell connected with the data line D 0 . When P 0 varies from 4 V to 0 V, 0 V in the memory cell is reduced toward −4 V. Then, since the word line W 0 is at 0 V, if the reduction amount exceeds the threshold voltage of the MOS-FET T 0 , the storage terminal (node) 10 of the memory cell is communicated with the data line D 0 . Thus, a current flows from the data line D 0 to the memory cell so that the memory cell signal appears on the data line D 0 . Then, a dummy word line {overscore (WD0+L )} varies from 4 V to 0 V. Thus, a reference signal appears on the data line {overscore (D0+L )}. Incidentally, in the case where a signal at a high potential of 6 V has been stored at the storage terminal 10 , the potential at the terminal is 2 V in accordance with the voltage change of P 0 . In this case, the potential on the data line D 0 does not vary since the MOS-FET T 0 constituting the memory cell in the OFF state.

After the memory cell signal and the reference signal have appeared on the data lines D 0 (Dn) and {overscore (D0+L )} ({overscore (Dn)}), respectively, φ SP varies from 1 V to 2 V and {overscore (φ SN +L )} varies from 1 V to 0 V. Thus, sense amplifiers SA 0 to SAn operate to amplify the corresponding memory cell signals. Therefore, the data line D 0 becomes 0 V and the data line {overscore (D0+L )} becomes 2 V. Thereafter, when the word line W 0 varies from 0 V to 4 V, 0 V (2 V in the case of reading the high potential) is stored in the memory cell. Next, a pair of data lines are selected by the Y decoder YD. Now it is assumed that the data lines D 0 , {overscore (D0+L )} are selected. Thus, the potential on the data line selection line Y 0 becomes 4 V and the memory cell signal is read out to data input/output lines I/O and {overscore (I/O)}. This signal is amplified by the output amplifier AMP to provide an output signal Dout. Next, the word line W 0 is lowered from 4 V to 2 V. Thereafter, the plate P 0 is boosted from 0 V to 4 V. Then, since the low potential of 0 V has been stored in the memory cell, the transistor T 0 constituting the memory cell is in the ON state. Therefore, the voltage of 0 V in the memory does not vary. Incidentally, in the case where the high potential of 2 V has been stored in the memory cell, the transistor T 0 is in the OFF state. Therefore, 2 V in the memory cell is boosted to 6 V. Thereafter, the word line W 0 becomes 0 V thereby to complete the rewrite operation mentioned above. Also the dummy word line {overscore (WD0+L )} varies from 0 V to 4 V. Thereafter, φ SP and {overscore (φ SN +L )} become 1 V and {overscore (φ P +L )} becomes 4 V thereby to precharge the data lines to 1 V.

The write operation will be explained with reference to the waveform chart of FIG. 52 B. After memory cell signals have been amplified by the sense amplifiers as in the read operation, a write signal Din is fetched into a data input buffer DiB. When a write control signal becomes 4 V, the potentials on the input/output lines I/O and {overscore (I/O)} are separated into a high potential and a low potential in accordance with Din. It is now assumed that I/O and {overscore (I/O)} have become 2 V and 0 V, respectively. Thereafter, a pair of data lines are selected by the Y decoder YD. It is now assumed that D 0 and {overscore (D0+L )} have been selected. Thus, the potential on the data line selection line Y 0 becomes 4 V so that D 0 and {overscore (D0+L )} become 2 V and 0 V, respectively. Accordingly, a high potential of 2 V is written at the storage terminal 10 of the memory cell (see the waveform in the case where the terminal 10 is at a low potential). On the other hand, the operation of writing a high potential signal in the memory in which a low potential signal has been stored in the memory is as follows. After the sense amplifier has been operated, the potentials on D 0 and {overscore (D0+L )} are 2 V and 0 V, respectively. The potentials on I/O and {overscore (I/O)} are 0 V and 2 V, respectively, in accordance with Din. Thereafter, the potential on Y 0 is enhanced to 4 V so that the potentials on D 0 and {overscore (D0+L )} are 0 V and 2 V. Accordingly, the low potential of 0 V is written at the storage terminal of the memory cell (see the waveform in the case where the terminal 10 is at a high potential).

The operation after the signal has been written in the memory cell in the above manner is the same as the read operation as previously mentioned. Namely, the high potential signal in the memory cell is boosted and stored at about 6 V whereas the low potential is stored at 0 V.

As explained above, in accordance with this embodiment, the voltage amplitude of the data lines and that of the voltage to be written into the memory cells can be determined independently from each other. Therefore, the voltage amplitude of the data lines (voltage amplitude when the sense amplifiers operate), which affects the power consumption of the memory, can be decreased, and also the voltage amplitude of the plates, which decides the high potential level of the memory cells relative to the data retention time for the memory cell, is increase. In this embodiment, the voltage amplitude of the plate is set to be larger than the that of the data lines. In this way, the power consumption can be remarkably reduced while assuring a sufficient signal voltage for the memory cells. Therefore, reduced power consumption and high S/N can be simultaneously realized. Further, in this embodiment, the potential on the data lines during its precharge is set at an intermediate value between the high and low potentials of the voltage amplitude of the data lines. This permits the power consumption to be further reduced. Moreover, the voltage amplitude of the data line can be decreased to the neighborhood of a sum of the absolute values of the threshold voltages of the N channel MOS-FET and P channel MOS-FET. Since the threshold voltage is generally 0.5 V to 1 V, the charging/discharging current in the case of the data line voltage amplitude of 2 V can be decreased to {fraction (1/2.5+L )} in the case of that of 5 V. Further, in this embodiment, the memory cell signal is read by reducing the potential on the plate P 0 from a high potential of 4 V to a low potential of 0 V. In the case where a signal line is driven using a MOS-FET, the discharging operation is performed at a higher speed than the charging operation. Therefore, the read operation in this embodiment can be performed at a higher speed than the read operation by boosting the word line from a low potential to a high potential.

FIGS. 53A and 53B show an embodiment of the word line driving circuit in accordance with the present invention. In FIG. 53A , MA is a memory cell array; D 0 , {overscore (D0+L )} is a data line; W 0 , Wm is a word line; and P 0 , Pm is a plate. WD is a word line intermediate potential setting circuit which serves to set an intermediate value of the word line together with a differential amplifier A 20 , a transistor T 60 , a resistor R 60 and a reference voltage Vr 10 .

The operation of the circuit of FIG. 53A will be explained with reference to the waveform chart of FIG. 53 B. During the stand-by time of a memory, a signal φ 20 is 0 V, a signal φ 21 is 4 V and plate driving signals φ p10 and φ p1m are 4 V. Therefore, transistors T 611 , T 63 and T 65 are in the ON state while transistors T 612 , Tp 63 and Tp 65 are in the OFF state. Then, the word line W 0 , Wm is 0 V and a terminal 64 is 4 V. Thereafter, the signal φ 21 becomes 0 V so that the transistors T 63 and T 65 are turned OFF. Next when the signal φ p10 becomes 0 V, the transistor Tp 63 is turned ON so that the word line W 0 becomes 4 V. When the signal φ 20 becomes 4 V, the transistor T 611 is turned OFF and the transistor T 612 is turned ON. Thus, the terminal 64 and the word line W 0 become 2 V. Thereafter, when φ p10 becomes 4 V and further φ 21 becomes 4 V, the word line W 0 becomes 0 V.

In accordance with this embodiment, the word line can be selected by selecting the plate so that a selection circuit for the word line is not required. Also, since the plate and the word line can be substantially, simultaneously selected, the high speed of a memory can be realized.

A further embodiment of the present invention will be explained with reference to FIGS. 54A , 54 B and 54 C. The memory cell shown in FIG. 54A is the same as the circuit of FIG. 37A except that the memory cell arrangement of two cells/one bit is adopted and the dummy word line is not provided. Due to the memory cell arrangement of two cells/one bit, two memory cell signals are simultaneously read out on the data lines to be a pair. Since the two signals are always complementary, any dummy cell is not required.

The operation of the memory circuit will be explained with reference to the waveform chart of FIG. 54 B. While the data precharge signal {overscore (φ p +L )}is 4 V, the data lines D 0 , {overscore (D0+L )} (Dn, {overscore (Dn)}) are at a precharge potential level of 1 V. Then, the sense amplifier driving signals φ sp and {overscore (φ SN +L )} are 1 V and the sense amplifiers SA 0 to SAn are in the OFF state. Next, the plate P 0 is selected and varies from 4 V to 0 V. Thus, the signal in each of the memory cells connected with the plate P 0 is read out on the corresponding data line. Now it is assumed that a high potential of 6 V has been stored at the storage terminal (node) 10 and a low potential of 0 V has been stored at the storage terminal (node) 11 . When the plate 0 varies from 4 to 0 V, the potential at the terminal 10 varies from 6 V to 2 V. Then, the data line D 0 is 1 V and the word line W 0 is 0 V so that a transistor T 01 in the OFF state whereby the voltage on the data line D 0 is not varied. On the other hand, the potential at the terminal 11 is reduced from 0 V toward −4 V. Then, the data line {overscore (D0+L )} is 1 V and the word line W 0 is 0 V so that when the potential at the terminal 11 becomes lower than the threshold voltage Vt of MOS-FET (T 02 ), the transistor T 02 is turned ON, whereby a current flows the data line D 0 to the terminal 11 . Thus, the potential on the data line {overscore (D0+L )} is slightly lowered. Accordingly, the memory cell signal is read out on both data lines D 0 and {overscore (D0+L )}.

Thereafter, the sense amplifier driving signal φ SP varies from 1 V to 2 V and {overscore (φ SN +L )} varies from 1 V to 0 V thereby to operate the sense amplifiers. Thus, the data line D 0 becomes 2 V and the data line {overscore (D0+L )} becomes 0 V. Next, when the word line W 0 becomes 4 V, 2 V is rewritten at the terminal 10 and 0 V is rewritten at the terminal 11 . Thereafter, the data lines D 0 and {overscore (D0+L )} are selected by the Y decoder YD and so the data line selection line Y 0 becomes 4 V. Thus, the memory cell signal is read out on the data input/output lines I/O and {overscore (I/O)}. This signal is amplified by the output amplifier AMP to provide an output signal Dout. Next, the word line W 0 is lowered from 4 V to 2 V. Then, D 0 is 2 V, {overscore (D0+L )} is 0 V, the storage terminal 10 is 2 V and the storage terminal 11 is 0 V so that the transistor T 01 is turned OFF and the transistor T 02 is turned ON. Next, when the plate P 0 is boosted from 0 V to 4 V, the potential at the storage terminal 10 is boosted about 6 V whereas the potential at the storage terminal 11 is held 0 V. Thereafter, the word line becomes 0 V thereby to complete the rewrite operation mentioned above. Accordingly, about 6 V is rewritten at the storage terminal 10 whereas 0 V is rewritten at the storage terminal 11 . Thereafter, the data line precharge signal {overscore (φ P +L )} is 4 V, and the sense amplifier driving signals φ SP and {overscore (φ SN +L )} become 1 V thereby to precharge the data lines to 1 V.

The write operation will be explained with reference to the waveform chart of FIG. 54 C. After memory cell signals have been amplified by the sense amplifiers as in the read operation, a write signal Din is fetched into a data input buffer DiB. When a write control signal becomes 4 V, the potentials on the input/output lines I/O and {overscore (I/O)} are separated into a high potential and a low potential in accordance with Din. It is now assumed that I/O and {overscore (I/O)} have become 0 V and 2 V, respectively. Thereafter, a pair of data lines are selected by the Y decoder YD. It is now assumed that D 0 and {overscore (D0+L )} have been selected. Thus, the potential on the data line selection line Y 0 becomes 4 V so that D 0 and {overscore (D0+L )} become 0 V and 2 V, respectively. Accordingly, 0 V is written at the storage terminal 10 of the memory cell whereas 2 V is written at the storage terminal 11 .

The operation after the signal has been written in the memory cell in the above manner is the same as the read operation as previously mentioned. Namely, the potential at the storage terminal 11 is boosted to 6 V which is stored there whereas the potential of 0 V at the storage terminal 10 is stored as it is.

As understood from the description, also in accordance with this embodiment, the voltage amplitude of the data lines and the voltage to be written into the memory cells can be determined independently from each other. Therefore, the charging/discharging current for the data lines can be decreased and so power consumption of the memory can be reduced. Further, reduction of the voltage to be written into the memory cells due to decreasing of the voltage amplitude of the data lines is compensated for by the write operation from the plates. Therefore, the characteristics of data retention time and α-ray resistance soft error can be improved. Moreover, since the memory cell arrangement of two cells/bit provides memory cell signals twice those in the memory cell arrangement of one cell/bit, high S/N in the memory can be realized. Also, any dummy cell is not required.

A further embodiment of the present invention will be explained with reference to FIGS. 55A , 55 B and 55 C. The memory circuit shown in FIG. 55A is different from the circuit of FIG. 37A in that bipolar transistors are used to read out the memory cell signals from the data lines. To this end, there are provided, as data input/output lines, two kinds of signal read lines O, {overscore (O)} and signal write lines I, {overscore (I)}. Although only the relation between the data lines and the input/output lines, the remaining circuit arrangement is the same as that of FIG. 37 A. The operation of the circuit of FIG. 55A is also the same as that as shown in FIGS. 37B and 37C except that the potentials of the data lines and their relative potentials are different for the reason why the bipolar transistors are used to read out the memory signals.

The read operation of the circuit of FIG. 55A will be explained with reference to the operation waveforms as shown in FIG. 55 B. Now it is assumed that the forward voltage between the base and emitter of the bipolar transistor is VBE. While the precharge signals {overscore (φ p +L )} of the data lines are 4 V, the data lines D and {overscore (D)} are precharged at 2 VBE. Then, the sense amplifier driving signals φ sp and {overscore (φ SN +L )} are 2 VBE so that the sense amplifier(s) is in the OFF state. Next, when the plate P varies from 4 V to 0 V, the signal(s) in the memory cell(s) is read out on the data lines. Now it is assumed that a low potential of VBE has been stored at the storage terminal 10 of the memory cell. In this case, when the plate P varies from 4 V to 0 V, the potential at the storage terminal 10 lowers from VBE to −(4−VBE). Then, the data line D is 2 VBE and the word line W is 0 V so that when the potential at the terminal 10 becomes lower than −Vt, the transistor T constituting the memory cell is turned ON, whereby a current flows from the data line D to the storage terminal 10 . Thus, the memory cell signal is read out on the data line D. On the other hand, at this time, the dummy word line WD varies from 4 V to 0 V so that a reference signal appears on the data line {overscore (D)} (For simplicity of explanation, only the dummy word line for D is illustrated but that for D is also provided in an actual memory). In the case where a high potential of 3 VBE+4 V has been stored at the storage terminal 10 , when the plate P varies from 4 V, the potential at the storage terminal 10 becomes 3 VBE. Then, the data line D is 2 VBE and the word line W is 0 V so that the transistor T is in the OFF state and so the potential of the data line D remains unchanged.

After the memory cell signal and the reference signal have appeared on the date lines D and {overscore (D)}, the sense amplifier driving signal φ sp varies from 2 VBE to 3 VBE and the sense amplifier driving signal {overscore (φ SN +L )} varies from 2 VBE to VBE. Thus, the sense amplifier(s) operates so that D becomes VBE and {overscore (D)} becomes 3 BVE. Subsequently, when the potential of the word line W becomes 4 V, VBE is rewritten at the storage terminal 10 . Thereafter, when a data line selection signal Yr becomes 4, the memory cell signal is read out on the signal read lines O and {overscore (O)}. This signal is amplified by the output amplifier AMP to provide an output signal Dour. Thereafter the potential of the word line W lowers from 4 V to 3 VBE. Then, the potential of the data line D is VBE and the potential at the storage terminal is also VBE so that the transistor T is in the ON state. Therefore, even when the plate P is boosted from 0 V to 4 V, the potential at the storage terminal 10 remains VBE. In the case where the high potential of 3 VBE+4 V has been stored at the storage terminal 10 , when the potential of the word line W becomes 3 VBE, the potential of the data line is 3 VBE and that at the storage terminal 10 is also 3 VBE so that the transistor T is in the OFF state. Thus, when the plate P is boosted from 0 V to 4 V, the potential at the storage terminal 10 is also boosted to 3 VBE+4 V.

Thereafter, the potential of the word line becomes 0 V thereby to complete the rewrite operation for the memory cell(s). The dummy word line WD varies from 1 V to 4 V. Thereafter, the data line precharge signal becomes 4 V and the sense amplifier driving signals φ SP and {overscore (φ SN +L )} become 2 VBE thereby to precharge the data lines at 2 VBE.

The write operation will be explained with reference to the waveform chart of FIG. 55 C. After memory cell signals have been amplified by the sense amplifiers as in the read operation, a write signal Din is fetched into a data input buffer DiB. When a write control signal becomes 4 V, the potentials on the signal write lines I and {overscore (I)} are separated into a high potential and a low potential in accordance with Din. It is now assumed that I and {overscore (I)} have become 3 VBE and VBE, respectively. Thereafter, a data line selection signal Yw is placed at 4 V by the Y decoder YD. Thus, the data line D becomes 3 VBE and the data line {overscore (D)} becomes VBE thereby to store 3 VBE at the storage terminal 10 .

The operation after the signal has been written in the memory cell in the above manner is the same as the read operation as previously mentioned. Namely, the potential at the storage terminal 11 is boosted to 3 VBE+4 V which is stored there.

As understood from the above description, also in accordance with this embodiment, the voltage amplitude of the data lines can be decreased while assuring a sufficient memory cell signal so that power consumption of the memory can be reduced. Further, the potential of the data lines is decided using as a standard the forward voltage between the base and emitter of the bipolar transistor so that a memory LSI in which MOS-FETs and bipolar transistors are mixedly provided can be easily designed.

A further embodiment of the present invention will be explained with reference to FIG. 36 . This embodiment relates to another operation for the circuit shown in FIG. 40 A. FIG. 56A shows the operation waveforms in the case where a write instruction signal from the outside of a memory chip is input to the chip in the manner greatly delayed from an address strobe signal. The operation waveforms of FIG. 56 are the same as those of FIG. 40C except that the potential at the storage terminal of a memory cell is twice boosted from a plate. In FIG. 56 , {overscore (RAS)} is a row (X) address strobe signal, {overscore (CAS)} is a column (Y) address strobe signal, and {overscore (WE)} is a write instruction signal.

The operation from the read of a memory cell signal to boosting of the potential at a storage terminal through a plate is the same as that shown in FIG. 40 B. In this embodiment, after the boosting by the plate, the {overscore (WE)} signal varies from a high potential to a low potential thereby to provide a write operation. Thus, the potential of the word line W 0 is boosted again from 5 V to 7 V. On the other hand, when the data line selection signal Y 0 varies from 0 V to 6 V, signals are written on the data lines D 0 and {overscore (D0+L )} through the data input/output lines I/O and {overscore (I/O)}. It is now assumed that 3 V is written on D 0 and 0 V is written on {overscore (D0+L )}. Thus, 3 V is stored at the storage terminal 10 of the memory cell. Next, the plate P 0 ′ varies from 6 V to 3 V again. Then, the potential of the word line W 0 is 7 V so that the potential at the storage terminal 10 is held by the sense amplifier. Thereafter, the potential of the word line W 0 lowers to 5 V. Next, the plate P 0 ′ varies from 3 V to 6 V. Then, the potential of the word line W 0 is 5 V and that of the data line D 0 is 3 V so that the transistor T 0 constituting the memory cell is the ON state, whereby the potential of 3 V at the storage terminal 10 is held by the sense amplifier. Further, in the case where a high potential of 5 V has been stored at the storage terminal 10 , when the potential of the word line W 0 becomes 5 V, the transistor T 0 is turned OFF. Thus, when the plate P 0 ′ varies 3 V to 6 V, the potential at the storage terminal 10 is boosted 5 V to about 8 V (see the waveform in the case where the terminal 10 is at a high potential level). After the above operation, the potential of the word line W 0 becomes 0 V thereby to complete the write of signals into the memory cell. Thereafter, the data lines D 0 and {overscore (D0+L )} are precharged at 4 V and also φ sp and {overscore (φ SN +L )} become 4 V.

In accordance with this embodiment, the voltage amplitude of the data lines can be decreased also in the operation mode in which a write instruction is inputted with delay so that power consumption in a memory can be reduced.

A further embodiment of the present invention will be explained with reference to FIG. 57 . The operation waveforms shown in FIG. 57 are the same as those of FIG. 56 except that the potential of the word line is binary. In this case, as explained in connection with the embodiment of FIG. 48 , if the higher potential is set at a value higher than the high potential of the data line D 0 by the threshold value of MOS-FET, the potential at the storage terminal 10 can be boosted. Thus, in accordance with this embodiment, even when the write instruction signal is inputted with delay, only the boosting of the potential at the storage terminal is carried out again without changing the potential of the word line through the plate. Accordingly, it is not necessary to boost the potential of the word line in writing signals so that circuit-designing of a memory can be easily implemented.

A further embodiment of the present invention will be explained with reference to FIGS. 58A , 58 B and 58 C. In FIG. 58A , MA is a memory cell array which is composed of plural data lines D 0 , {overscore (D0+L )} to Dn, {overscore (Dn)}, word lines W 0 , W 1 to Wn, dummy word lines WD 0 , WD 1 , plates (plate wirings) P 0 , P 1 to Pm, dummy cells DMCs and memory cells MCs. MC is composed of a MOS-FET T 0 and a storage capacitor Cs. DMC which serves to generate a reference voltage is composed of MOS-FETs T 3 , T 4 and a storage capacitor Cs. 8 is a signal line which conducts a dummy cell write signal to write a storage voltage DV in the dummy cell(s). XD is an X decoder which serves to select one of the word lines and the dummy word line in accordance with an external address signal. The relation between the word line and dummy word line is such that when the word line W 0 where the memory cell is connected with the data line D 0 is selected, the dummy word line DW 1 where the dummy cell is connected with the data line D 0 is selected. YD is a Y decoder which serves to select a pair of data lines from the plural pairs of data lines D 0 , {overscore (D0+L )} (Dn, {overscore (Dn)}). Y 0 to Yn are a data line selection signal line which serves to conduct an output signal from the Y decoder, respectively. PD is a plate driving circuit which serves to control the voltage at one (plates P 0 to Pm) of the terminals of the capacitor constituting each memory cell. This circuit also, like the X decoder, selects one of the plate wirings in accordance with the external address signal. SA 0 to SAn are ordinary sense amplifiers each of which is a flip-flop composed of P channel MOS-FETs and N channel MOS-FETs and serves to the signal read out from each memory cell. Numeral 1 is a signal line for conducting a data line precharge voltage Vdp. Numeral 2 is a data line precharge signal line for conducting a precharge signal {overscore (φ p +L )}. Numerals 3 and 4 are sense amplifier driving signals which conduct sense amplifier signals φ sp and {overscore (φ SN +L )}, respectively. I/O and {overscore (I/O)} are data input/output lines which serve to conduct a signal to be written into each memory cell and a signal read out therefrom (Although not shown here, a precharge circuit is actually provided for the data input/output lines). AMP is an output amplifier which serves to amplify the signal read out from the memory cell to provide an output signal Dout. Dib is a data input buffer which serves to convert an input signal (write signal) from an external device into the corresponding signal level in the memory chip. φ w is a write control signal.

The read operation of the circuit shown in FIG. 58A will be explained with reference to the operation waveforms shown in FIG. 58 B. It should be noted that for convenience of explanation, an example of the voltage value of each waveform is illustrated.

While the data line precharge signal {overscore (φ p +L )} is 4 V, the data lines D 0 , {overscore (D0+L )} (Dn, {overscore (Dn)}) are at a precharge potential level of 2 V BE (1.6 V). Then the sense amplifier driving signals φ sp and {overscore (φ SN +L )} are 2 V BE and the sense amplifier is in an OFF state. It is assumed that after {overscore (φ p +L )} has become 0 V, one word line W 0 has selected from the plural word lines. Then, when W 0 varies from 0 V to 5 V BE (4 V), a memory cell signal appears on each data line. Now it is assumed that a high potential of 3 V BE +5 V BE =8 V BE (6.4 V) has been stored at the storage terminal (node) of the memory cell connected with the data line D 0 . When the word line W 0 varies from 0 V to 5 V BE (4 V), a read-out signal voltage corresponding a data line capacitance C o and a storage capacitance C s appears on the data line D 0 . The amount Vs of the read-out signal voltage is expressed by

ΔVs(‘1’)=Cs/(C D +Cs)×Vs(‘1’)

where

Cs: storage capacitance

C D : data line capacitance

V BE : forward voltage (0.8 V) between the base and emitter of a bipolar transistor

Vs(‘1’): storage voltage (8 V BE −2 V BE =6 V BE (4.8 V)) The amount Vs (‘0’) of the read-out signal voltage in the case where a low potential has been stored in expressed by

Vs(‘0’)=Cs/(Cp+Cs)×Vs(‘0’)

where Vs (‘0’): storage voltage (2 V BE −V BE =V BE (0.8 V))

If such a voltage relation is set, as understood from the above equations, the read-out signals are greatly different for the stored ‘1’ and ‘0’. In order to eliminate such a difference, the dummy cells are provided. The dummy cells are selected in such a way that selected is a dummy cell connected with the data line opposite to the data line with which a memory cell is connected. Namely, when the word line W 0 is selected, the dummy word line WD 1 is selected so that a reference read-out signal voltage ΔVs D appears on the data line {overscore (D0+L )}. The value of ΔVs D is decided by the voltage DV to be stored in the dummy cell. The value of DV is set at an intermediate value between ‘1’ and ‘0’, i.e. 4.5 V BE (3.6 V) If it is desired that the margin on the side of ‘1’ is made large in view of α-ray soft error and refresh, the voltage of VD may be decreased.

After the memory cell signal and the reference signal have appeared on the data line respectively, φ sp varies from 2 V BE (1.6 V) to 3 V BE (2.4 V) and {overscore (φ SN +L )} varies 2 V BE . Thus, the sense amplifiers SA 0 to SAn operate to amplify the corresponding memory cell signals. Therefore, the data line D 0 becomes 3 V BE and the data line {overscore (D0+L )} becomes V BE . Next, the plate P 0 is lowered from 5 V BE (4 V) to 0 V. Then, the word line W 0 is 5 V BE (4 V) so that even when the plate voltage varies, the potential on the data line D 0 remains 3 V BE . Thereafter, a pair of data lines are selected by the Y decoder YD. Now it is assumed that the data lines D 0 and {overscore (D0+L )} are selected. Thus, the potential on the data line selection Y 0 becomes 4 V and the memory cell signal is read out to the data input/output lines I/O and {overscore (I/O)}. This signal is amplified by the output amplifier AMP to provide an output signal Dout. Next, the word line W 0 is lowered from 5 V BE (4 V) to 3 V BE (2.4 V). Thereafter, the plate P 0 is boosted from 0 V to 5 V BE (4 V). Then, since a high potential of 3 V BE has been stored at the storage terminal 10 of the memory cell, the transistor T 0 constituting the memory cell is in the OFF state. The potential at the storage terminal 10 is boosted from 3 V BE to 3 V BE +5 V BE (6.4 V). Incidentally, in the case where a low potential of V BE has been stored at the storage terminal 10 of the memory cell, the transistor T 0 is in the ON state. Therefore, the potential at the storage terminal 10 remains V BE . Thereafter, the word line W 0 becomes 0 V thereby to complete the rewrite operation mentioned above. Also, φ sp and {overscore (φ SN +L )} become 2 V and {overscore (φ p +L )} becomes 4 V thereby to precharge the data lines to 2 V BE .

The write operation will be explained with reference to the waveform chart of FIG. 58 C. After memory cell signals have been amplified by the sense amplifiers as in the read operation, a write signal Din is fetched into a data input buffer DiB. When a write control signal φ w becomes 4 V, the potentials on the input/output lines I/O and {overscore (I/O)} are separated into a high potential and a low potential in accordance with Din. It is now assumed that I/O and {overscore (I/O)} have become V BE and 3 V BE , respectively. Thereafter, a pair of data lines are selected by the Y decoder YD. It is now assumed the D 0 and {overscore (D0+L )} have been selected. Thus, the potential on the data line selection line Y 0 becomes 4 V so that D 0 and {overscore (D0+L )} become V BE and 3 V BE , respectively. Accordingly, a low potential of V BE is written at the storage terminal 10 of the memory cell (see the waveform in the case where the terminal 10 is at a high potential). On the other hand, the operation of writing a high potential signal in the memory in which a low potential signal has been stored in the memory is as follows. After the sense amplifier has been operated, the potentials on D 0 and {overscore (D0+L )} are V BE and 3 V BE , respectively, in accordance with Din. Thereafter, the potential on Y 0 is enhanced to 4 V so that the potentials on D 0 and {overscore (D0+L )} are 3 V BE and V BE . Accordingly, the low potential of 3 V is written at the storage terminal of the memory cell (see the waveform in the case where the terminal 10 is at a low potential).

The operation after the signal has been written in the memory cell in the above manner is the same as the read operation as previously mentioned. Namely, the high potential signal in the memory cell is boosted to 3 V BE +5 V BE =8 V BE (6.4 V) which is stored whereas the low potential signal of V BE is stored as it is. Further, the constant voltage DV is written in the dummy cell by the dummy cell write signal DC through MOS-FET T 3 .

As explained above, in accordance with this embodiment, the voltage amplitude of the data lines and that of the voltage to be written into the memory cells can be determined independently from each other. Therefore, the voltage amplitude of the data lines (voltage amplitude when the sense amplifiers operate), which affects the power consumption of the memory can be decreased, and the voltage amplitude of the plates, which decides the high potential level of the memory cells relative to the data retention time for the memory cell. In this embodiment, the voltage amplitude of the plate is set to be larger than that of the data lines. In this way, the power consumption can be remarkably reduced while assuring a sufficient signal voltage for the memory cells. Therefore, reduced power consumption and high S/N can be simultaneously realized. Further, in this embodiment, the potential on the data lines during its precharge is set at an intermediate value between the high and low potentials of the voltage amplitude of the data lines. This permits the power consumption to be further reduced. Moreover, the voltage amplitude of the data line can be decreased to the neighborhood of a sum of the absolute values of the threshold voltages of the N channel MOS-FET and P channel MOS-FET. Since the threshold voltage is generally 0.5 V to 1 V, the charging/discharging current in the case of the data line voltage amplitude of 2 V BE (1.6 V) can be decreased to about {fraction (1/3+L )} in the case of that of 5 V. Further, in this embodiment, dummy cells are provided so that the storage voltage can be freely controlled. Therefore, the read-out signal amount of ‘1’ or ‘0’ can be controlled so that a memory having the characteristics of high α-ray soft error resistance, unvaried refresh and low power consumption can be designed. Moreover, the respective operation voltages such as the potential on the data lines are decided using as a standard the forward voltage between the base and the emitter of the bipolar transistor so that a memory LSI in which MOS-FETs and bipolar transistors are mixedly provided can be easily designed.

FIG. 59 shows an exemplary arrangement of a circuit for generating the dummy cell write voltage DV which is composed of a bipolar transistor Q 0 and resistors R 1 , R 2 and R 3 . The voltage value of DV at a terminal 21 is expressed by

DV=V (R2+R3)/R3

where V is the base-emitter voltage of the transistor Q 0 . Thus, the value of DV can be optionally set in accordance with the resistances of the resistors R 2 and R 3 .

A further embodiment of the present invention will be explained with reference to FIG. 60 . The memory circuit shown in FIG. 60 is the same as that of FIG. 58A except that a plate for the storage capacitor of a memory cell is commonly provided for two word lines, which permits the memory to be integrated with higher degree than the arrangement of FIG. 58 A.

The read operation of the circuit shown in FIG. 60A will be explained with reference to a waveform chart shown in FIG. 60 B. While the data line precharge signal {overscore (φ p +L )} is 4 V, the data lines D 0 , {overscore (D0+L )} (Dn, {overscore (Dn)}) are precharged at 4 V BE (3.2 V). Then, the sense amplifier driving signals φ SP and {overscore (φ SN +L )} are 4 V and the sense amplifiers SA 0 and SAn are in the OFF state. After {overscore (φ p +L )} has been changed to 0 V, one of the word lines is selected. Now it is assumed that the word line W 0 has been selected. When W 0 is changed from 0 V to 5.5 V, a memory cell signal appears at each data line. Now it is assumed that the memory cells connected with the word line W 0 have stored a signal at a high potential level (8 V BE ). Therefore, read from the dummy cells is ‘1’ information on D 0 , Dn and is ‘0’ information of {overscore (D0+L )}, {overscore (Dn)}. Next, when φ sp is changed from 4 V to 5 V, and {overscore (φ SN +L )} is changed form 4 V to 3 V, the sense amplifiers SA 0 to SAn operate to amplify the memory signals. Thus, the data line D 0 becomes 5 V and the data line {overscore (D0+L )} becomes 3 V. Thereafter, a pair of the data lines is selected by the Y decoder YD. It is now assumed that D 0 and {overscore (D0+L )} are selected. Thus, the potential at the data line selection line Y 0 becomes high so that the memory cell signal is read out to the data input/output lines I/O and {overscore (I/O)}. This signal is amplified by the output amplifier AMP to provide the Dout.

The rewrite operation of a signal into a memory cell will be explained. After the sense amplifier has been operated, D 0 is at a high potential of 5 V BE and {overscore (D0+L )} is a low potential of 3 V BE . Then, the storage terminal 10 of the memory cell is at the high potential of 5 V BE like D 0 since the word line W 0 is at the high potential level. Then, the potential at the plate P 0 ′ is changed from 5.5 V BE (4.4 V) to 2.5 V BE (2 V). However, the potential on the data line and at the storage terminal are held 5 V BE by the sense amplifier and not varied. Thereafter, the potential on the word line W 0 is lowered from 5.5 V to 5 V BE . Then, assuming that the threshold voltage of a transistor substituting the memory cell is 1 V, both potentials of at the storage terminal 10 and on the data line D 0 are 5 V BE and also that on the word line W 0 is 5 V BE so that the transistor T 0 is in the OFF state. Therefore, when the potential on the plate P 0 ′ is changed from 2.5 V BE to 5.5 V BE , the potential at the storage terminal 10 is boosted from 5 V BE to about 8 V BE (6.4 V). Thus, the high potential of about 8 V BE is written in the memory cell.

On the other hand, the rewrite operation in the case where a signal at a low potential has been stored in the memory will be explained with reference to the waveform in the case where the terminal 10 in FIG. 40B is at a low potential. After the sense amplifier has been operated, both potentials on the data line D 0 and at the storage terminal 10 are 3 V BE . Therefore, even if the potential on the word line W 0 is subsequently lowered from 5.5 V to 5 V BE (4 V), the transistor T 0 constituting the memory cell is an ON state. Thus, even if the potential at the plate P 0 ′ is subsequently changed in any fashion, since the data line potential is fixed, the potential at the storage terminal 10 is held 3 V BE . Accordingly, the low potential of 3 V BE is rewritten in the memory cell.

Meanwhile, in this embodiment, the potential of the memory cell connected with a non-selected word line is varied in its potential. Then, the behavior of a storage terminal 11 of the memory cells connected with a non-selected word line W 1 will be explained. The operation in the case where a high potential has been stored at the storage terminal 11 is as follows. During the stand-by time of the memory, the plate P 0 is at 5.5 V BE and the storage terminal 11 is at 8 V BE . After the sense amplifier has amplified the memory signal, P 0 ′ becomes 2.5 V BE and then the storage terminal 11 becomes 5 V BE . Then, the word line W 1 becomes 0 V BE and the data line {overscore (D 0 )} becomes 3 V BE so that a transistor T 1 is never in the ON state and so the signal in the memory cell is not destroyed. Thereafter, the plate P 0 ′ becomes 5.5 V BE and the storage terminal 11 returns to 8 V.

The operation in the case where a low potential has been stored at the storage terminal 11 is as follows. During the stand-by time of the memory, the plate P 0 ′ is at 5.5 V BE and the storage terminal 11 is at 3 V BE . After the sense amplifier has amplified the memory signal, P 0 ′ becomes 2.5 V BE and then the storage terminal 11 becomes 0 V. Then, the word line W 1 becomes 0 V BE and the data line {overscore (D 0 )} becomes 5 V BE so that a transistor T 1 is never in the ON state and so the signal in the memory cell is not destroyed. Thereafter, the plate P 0 becomes 5.5 V BE and the storage terminal 11 returns to 8 V BE .

Thereafter, the potential on the word line W 0 becomes 0 V to complete the rewrite operation. Subsequently, φ SP and {overscore (φ SN +L )} become 4 V. {overscore (φ p +L )} becomes the high potential to precharge the data line to 4 V.

The write operation in the circuit shown in FIG. 60A will be explained with reference to the waveform chart of FIG. 60 C. After memory cell signals have been amplified by the sense amplifiers as in the read operation, a write signal Din is fetched into a data input buffer DiB. When a write control signal becomes a high potential, the potentials on the input/output lines I/O and {overscore (I/O)} are separated into a high potential and a low potential in accordance with Din. It is now assumed that I/O and {overscore (I/O)} have become 3 V BE and 5 V BE , respectively. Thereafter, a pair of data lines are selected by the Y decoder YD. It is now assumed that D 0 and {overscore (D 0 )} have been selected. Thus, the potential on the data line selection line Y 0 becomes 4 V so that D 0 and {overscore (D 0 )} become 3 V BE and 5 V BE , respectively. Accordingly, a low potential of 3 V BE is written at the storage terminal 10 of the memory cell. The operation after the signal has been written in the memory cell in the above manner is the same as the read operation as previously mentioned.

As understood from the description, also in accordance with this embodiment, the voltage amplitude of the data lines and that of the voltage to be written into the memory cells can be determined independently from each other. Therefore, the charging/discharging current for the data lines can be decreased and so power consumption of the memory can be reduced. Further, reduction of the voltage to be written into the memory cells due to decreasing of the voltage amplitude of the data lines is compensated for by the write operation from the plates. Therefore, the characteristics of data retention time and (x-ray resistance soft error can be improved. Further, in this embodiment, dummy cells are provided so that the storage voltage can be freely controlled. Therefore, the read-out signal amount of ‘1’ or ‘0’ can be controlled so that a memory having the characteristics of high a-ray soft error resistance, unvaried refresh and low power consumption can be designed. Moreover, the respective operation voltages such as the potential on the data lines are decided using as a standard the forward voltage between the base and the emitter of the bipolar transistor so that a memory LSI in which MOS-FETs and bipolar transistors are mixedly provided can be easily designed. Furthermore, since one plate is commonly provided for two word lines W 0 and W 1 , the areas of the memory chip can be decreased.

In accordance with this embodiment, the voltage amplitude of the data lines in operating the sense amplifiers can be greatly decreased so that the data line charging/discharging current can be decreased, thereby reducing the power consumption in a memory cell array to {fraction (1/2+L )} to ⅓l of the conventional memory cell array. Further, the memory cell signal at a high potential is boosted from the plate so that the memory cell signal can be increased. Accordingly, the present invention is efficient to implement the low power consumption in a memory and the high S/N thereof. More specifically, the present invention can improve the characteristics of data retention time, α-ray soft error resistance, noise reduction and reliability.

A further embodiment of the present invention will be explained with reference to FIG. 61 which shows a low power consumption memory chip and a power source for operating it. It should be noted that a battery is used as the power source.

In FIG. 61 , numeral 1 is a memory chip. MA is a memory array which is composed of memory cells MCs, data lines D, {overscore (D)}, word lines W, plate wirings P, sense amplifiers SA, etc. CC is a peripheral circuit which is composed of an input/output interface circuit and a circuit for generating a driving signal for the memory array. This peripheral circuit also include a voltage limiting circuit as disclosed in U.S. Pat. No. 4,482,985. RV is a reference voltage generating circuit which generate several kind of voltages between the power supply voltage and 0 V. This voltage is sent to the voltage limiting circuit which current-amplifies the voltage to provide a voltage to be used in me memory array. The reference voltage generating circuit is also disclosed in e.g. the above U.S. Pat. No. 4,482,985. PAD 1 and PAD 2 are bonding pads (only those for power sources (V cc , V ss ) are shown). BW 1 and BW 2 are bonding wires, and L 1 and L 2 represent the schematic of package pins. B is a battery.

The peripheral circuit uses the voltage generated by the voltage limiting circuit and the voltage input from the outside of the chip. Decreasing the voltage amplitude of the pulse signals by the voltage limiting circuit intends to reduce power consumption in the memory chip. The memory array provides very large charging/discharging current on the data lines. The voltage amplitude of the data lines is set at a relatively large value for the purpose of assuring the charges to be stored in the memory cell. However, the charges stored in the memory cell is about {fraction (1/10+L )} or less of the charge on the data line. Namely, most charges are not employed but consumed as useless charging/discharging current. Meanwhile, if the charges stored in the memory cell can be increased irrespectively of the voltage amplitude of the data lines, the voltage amplitude of the data lines may be decreased. Then, in accordance with this embodiment, the stored charges are increased irrespectively of the voltage amplitude of the data lines so as to decrease the voltage amplitude of the data lines, thereby reduce the power consumption in the memory. As a technique of increasing the stored charges, there are proposed a method of increasing the capacitance of the capacitor in the memory cell and a method of writing a memory cell signal into the memory cell selected by the word line from a plate thereby to increase the stored charges, By means of these methods, reduced power consumption can be realized while assuring sufficient stored charges.

In accordance with this embodiment, power consumption of DRAM can be greatly reduced. Thus, the characteristic of data retention can be improved and also noise can be reduced so that malfunction of DRAM can be obviated. Further, DRAM can be operated using a battery so that it can be widely applied to a portable device. Incidentally, although in this embodiment, a battery is used as a power source, the voltage produced from a commercially available power supply may be employed.

A further embodiment of the present invention will be explained with reference to FIGS. 62A and 62B . This embodiment is directed to a method of writing a memory ell signal from a plate thereby to decrease the data line voltage amplitude. FIG. 62A shows a memory chip in the case where 5 V is applied as a power supply voltage from the outside. Of MOS-FETs shown in FIG. 62 , the MOS-FET with an arrow is a P channel MOS-FET (PMOS) and the MOS-FET with no arrow is an N channel MOS-FET (NMOS). It is assumed that the threshold voltage of MOS-FET is 10.5 Vl. In FIG. 62A , numeral 1 is a memory chip. MA is a memory array which is composed of plural data lines D 0 , /D 0 to Dn, /Dn, plural word lines W 0 , W 1 , . . . , a plate (plate wiring) P 0 , memory cells one MC 0 of which is shown, sense amplifiers SA 0 to SAn, data line precharging transistors Tp 0 to Tp 3 , and switching transistors Ty 0 to Ty 3 . Although only one plate wiring is shown, plural plates wirings are actually provided one for several to several tens word lines and selectively driven. XD is an X decoder which serves to select one of the plural word lines. YD is a Y decoder which serves to select one pair of the plural pairs of data lines. Y 0 to Yn are output signal lines which conduct the corresponding output signals from the Y decoder. PD is a plate driving circuit which serves to selectively drive the plural plate wirings. Numeral 2 is a data line precharging voltage generating circuit which serves to generate a data line precharging voltage using a reference voltage produced by a reference voltage generating circuit. CD is a sense amplifier driving signal generating circuit which serves to drive the sense amplifiers through sense amplifier driving signal lines CSP and CSN. I/Os are data input/output lines each of which conducts the signal to be written into the corresponding memory cell and the signal read out from the corresponding memory cell. DOB is an output amplifier which serves to amplify the signal read out from the memory cell to provide an output signal Do. DiB is a data input buffer which serves to receive an input signal Di from the chip outside to produce the signal to be written into the memory cell. PC is a timing pulse generating circuit which serves to generate signals for controlling the above memory array, X decoder, Y decoder, sense amplifier driving signal generating circuit, etc. Numeral 3 is a reference voltage generating circuit which serves to generate several kinds of reference voltages to be used within the chip on the basis of a power supply voltage applied from the outside of the chip (In this embodiment, three kinds (4 V, 3 V and 2 V) of reference voltages are generated). This reference voltage generating circuit is disclosed in e.g. U.S. Pat. No. 4,482,985. Numerals 4 and 5 are bonding pads (only bonding pads for power supplies (V cc , V ss ) are shown).

The read operation of the circuit shown in FIG. 62A will be explained with reference to the operation waveforms shown in FIG. 62 B. Now, the read operation of a memory cell MC 0 will be mainly explained.

While the data line precharge signal {overscore (φ p +L )} is 5 V, the data lines are precharged at a data line precharge voltage Vdp (=4 V). Then, the sense amplifier signal lines CSP and CSN are also 4 V. Therefore, the sense amplifiers are in the OFF state. After {overscore (φ p +L )} has been changed to 0 V). one of the word lines is selected by the X decoder. It is assumed that the word line W 0 has been selected. When W 0 becomes 7 V, a memory cell signal appears on each data line. Now, it is assumed that a signal (1) at a high potential level has been stored in the memory cell MC 0 . Therefore, the potential of the data line D 0 becomes slightly higher than 4 V. Next, CSP and CSN are changed from 4 V to 5 V and to 3 V, respectively by the sense amplifier driving signal generating circuit CD. Thus, the sense amplifiers SA 0 to SAn operate to amplify the memory signals. Then, the data line D 0 becomes a high potential level of 5 V and the data {overscore (D 0 )} becomes a low potential of 3 V. Thereafter, the potential at the plate P 0 is changed from 5 V to 2 V by the plate driving circuit PD. Then, the potential at the storage node NO of each selected memory cell or that of the data line thereof varies through capacitive coupling, but the potential at each node is recovered to its previous level since it is held by the sense amplifier. Next, a pair of data lines are selected from the plural pairs of data lines by the Y decoder YD. It is now assumed that D 0 and {overscore (D 0 )} are selected. Thus, the potential of the data line selection line Y 0 from the Y decoder becomes 5 V so that the memory cell signal is read out on the data input/output lines IOs. This signal is amplified by the output amplifier DOB to provide an output signal D 0 . Incidentally, on the contrary, in a write operation, an input signal taken by the data input buffer DiB is written in the memory cell by the data input/output lines and the data lines when Y 0 becomes 5 V.

After the input and output of the memory cell signal has been performed in the above manner, the potential of the word line W 0 becomes 5 V. Then, the storage node NO of the memory cell MC 0 is 5 V and the data line D 0 is also 5 V so that the transistor T 0 is in the OFF state. Next, the potential of the plate P 0 varies from 2 V to 5 V. Thus, the storage node N 0 of the memory cell MC 0 is boosted from 5 V to about 8 V. Next, when the word line WO becomes 0 V, 8 V is stored in the memory cell MC 0 . Thereafter, φ p becomes 5 V thereby to precharge the data lines. Also, CSP and CSN become 4 V.

In the case where a signal at a low potential level (“0”) has been stored in the memory cell MC 0 after the sense amplifier has been operated, D 0 and {overscore (D 0 )} become 3 V and 5 V, respectively. Therefore, even when the potential of the word line W 0 has become 5 V, the transistor T 0 in the memory cell MC 0 remains ON. Thereafter, when the plate P 0 varies from 2 V to 5 V, the potential at the storage node N 0 of the memory cell MC 0 is slightly increased, but it is returned to 3 V since it is held by the sense amplifier. Thereafter, when the word line W 0 becomes 0 V, 3 V is stored in the memory cell MC 0 .

Meanwhile, in this embodiment, the plate potential of a non-selection memory cell is also varied, whereby the potential at the storage node of the non-selection memory cell is varied. This will be explained with respect to the potential change at a node N 1 . Assuming that the signal at the high potential level (‘1’) has been stored at the storage node N 1 , during the stand-by time of the memory, N 1 is 8 V. Thereafter, when the plate P 0 varies in the sequence of 5 V-2 V-5 V, N 1 varies in the sequence of 8 V-5 V-8 V. Then, W 1 is 0 V and D 0 is 5 V or 3 V and so the transistor T 1 of the memory cell is in the OFF state so that any problem does not occur. On the other hand, assuming that the signal at the low potential level (0) has been stored at the storage node. N 1 ; during the stand-by time of the memory, N 1 is 3 V. Thereafter, when the plate P 0 varies in the sequence of 5 V-2 V-5 V, N 1 varies in the sequence of 3 V-0 V-3 V. Then, W 1 is 0 V and D 0 is 5 V or 3 V and so the transistor T 1 of the memory cell is in the OFF state so that any problem does not occur. In this way, by boosting the lower potential level of the memory cell, erroneous selection of the non-selection memory cell due to the potential change of the plate can be prevented.

As understood from the above description, also in accordance with this embodiment, the voltage amplitude of the data lines and that of the voltage to be written into the memory cells can be determined independently from each other. Therefore, by decreasing the charging/discharging current for the data lines which provide a large parasitic capacitance and also a large charging/discharging current and increasing the voltage amplitude of the plates which provide a small parasitic capacitance, power consumption in the memory can be reduced while assuring a sufficient memory cell signal. In this case, setting the voltage amplitude of the data lines at a larger value than that of the plates is efficient to realize them. In this embodiment in which the data line voltage amplitude is 1 V, the charging/discharging current can be decreased to {fraction (1/5+L )} of the conventional case where it is 5 V. The data line voltage amplitude may be decreased to the neighborhood of the threshold voltage of the MOS-FETs which constitute the sense amplifier, but it is desired to satisfy, in view of the stability of the operation, the condition, |V tn |÷|V tp |<ΔVd (Vtn: threshold voltage of NMOS, Vtp: threshold voltage of PMOS, Vd; data line voltage amplitude). The power consumption in driving the plate may be neglected in e.g. a memory array of 256 word lines×1024 data line pairs since the capacitance charged/discharged at a time is as small as 200 to 300 pF for the data line and 2 to 3 pF for the plate.

Further, in accordance with this embodiment, the precharging potential of the data line is set at an intermediate level between the high potential and the low potential of the data line voltage amplitude. Thus, the power consumption can be further reduced. Moreover, a capacitor in each memory cell is generally made using a thin oxide film. Correspondingly, in this embodiment, the plate potential is set, during the stand-by time of the memory, at an intermediate level between two storage potential level used in the memory cell. Therefore, the electric field applied to the capacitor of the memory cell is made small, thereby improving the reliability of the memory. Further, in this embodiment, the memory cell signal is larger on the high potential side than the low potential side so that the characteristics of data retention and a-ray soft error resistance can be improved.

A further embodiment of the present invention will be explained with reference to FIGS. 63A and 63B . This embodiment is also directed to a method of writing a memory cell signal from a plate thereby to decrease the data line voltage amplitude. FIG. 63A shows a memory chip in the case where 1.5 V is applied as a power supply voltage (V cc ). Although the circuit arrangement of FIG. 63A is the same as that of FIG. 62A , the operation voltages therein are different from the latter. Therefore, three kinds of reference voltages of 1.2 V, 0.9 V and 0.6 V which are generated from the reference voltage generating circuit 3 are used. Like reference symbols in FIG. 63A refer to like elements in FIG. 62 A. The threshold voltage of MOS-FET is set at 10.15 Vl.

The read operation of Ie circuit shown in FIG. 63A will be explained with reference to the operation waveforms shown in FIG. 63 B. Now, the read operation of a memory cell MC 0 will be mainly explained.

While the data line precharge signal {overscore (φ p +L )} is 1.5 V, the data lines are precharged at a data line precharge voltage Vdp (=1.2 V). Then, the senser amplifier signal lines CSP and CSN are also 1.2 V. Therefore, the sense amplifiers are in the OFF state. After {overscore (φ p +L )} has been changed to 0 V, one of the word lines is selected by the X decoder. It is assumed that the word line W 0 has been selected. When W 0 becomes 2 V, a memory cell signal appears on each data line. Now, it is assumed that a signal (‘1’) at a high potential level has been stored in the memory cell MC 0 Therefore, the potential of the data line D 0 becomes slightly higher than 1.2 V. Next, CSP and CSN arc changed from 1.2 V to 1.5 V and to 0.9 V, respectively by the sense amplifier driving signal generating circuit CD. Thus, the sense amplifiers SA 0 to SAn operate to amplify the memory signals. Then, the data line D 0 becomes a high potential level of 1.5 V and the data line D 0 becomes a low potential of 0.9 V. Thereafter, the potential at the plate P 0 is changed from 1.5 V to 0.6 V by the plate driving circuit PD. Then, the potential at the storage node N 0 of each selected memory cell or that of the data line thereof varies through capacitive coupling, but the potential at each node is recovered to its previous level since it is held by the sense amplifier. Next, a pair of data lines are selected from the plural pairs of data lines by the Y decoder YD. It is now assumed that D 0 and {overscore (D 0 )} are selected. Thus, the potential of the data line selection line Y 0 from the Y decoder becomes 1.5 V so that the memory cell signal is read out on the data input/output lines IOs This signal is amplified by the output amplifier DOB to provide an output signal D 0 . Incidentally, on the contrary, in a write operation, an input signal taken by the data input buffer DiB is written in the memory cell by the data input/output lines and the data lines when Y 0 becomes 1.5 V.

After the input and output of the memory cell signal has been performed in the above manner, the potential or the-word line W 0 becomes 1.5 V. Then, the storage node N 0 of the memory cell MC 0 is 1.5 V and the data line D 0 is also 1.5 V so that the transistor T 0 is in the OFF state. Next, the potential of the plate P 0 varies from 0.6 V to 1.5 V. Thus, the storage node N 0 of the memory cell MC 0 is boosted from 1.5 V to about 2.4 V. Next, when the word line W 0 becomes 0 V, 2.4 V is stored in the memory cell MC 0 . Thereafter, {overscore (φp)} becomes 1.5 V thereby to precharge the data lines. Also, CSP and CSN become 1.2 V.

In the case where a signal at a low potential level (‘0’) has been stored in the memory cell MC 0 after the sense amplifier has been operated, D 0 and {overscore (D 0 )} become 0.9 V and 1.5 V, respectively. Therefore, even when the potential of the word line W 0 has become 1.5 V, the transistor T 0 in the memory cell MC 0 remains ON. Thereafter, when the plate P 0 varies from 0.6 V to 1.5 V, the potential at the storage node N 0 of the memory cell MC 0 is slightly increased, but it is returned to 0.9 V since it is held by the sense amplifier. Thereafter, when the word line W 0 becomes 0 V, 0.9 V is stored in the memory cell MC 0 .

Meanwhile, also in this embodiment, the plate potential of a non-selection memory cell is also varied, whereby the potential at the storage node of the non-selection memory cell is varied. This will be explained with respect to the potential change at a node N 1 . Assuming that the signal at the high potential level (1) has been stored at the storage node N 1 , during the stand-by time of the memory, N 1 is 2.4 V. Thereafter, when the plate P 0 varies in the sequence of 1.5 V-0.6 V-1.5 V, N 1 varies in the sequence of 2.4 V-1.5 V-2.4 V. Then, W 1 is 0 V and D 0 is 1.5 V or 0.9 V and so the transitor T 1 of the memory cell is in the OFF state so that any problem does not occur. On the other hand, assuming that the signal at the low potential level (‘0’) has been stored at the storage node N 1 , during the stand-by time of the memory, N 1 is 0.9 V. Thereafter, when the plate P 0 varies in the sequence of 1.5 V-0.6 V-1.5 V, N 1 varies in the sequence of 0.9 V-0 V-0.9 V. Then, W 1 is 0 V and D 0 is 1.5 V or 0.9 V and so the transistor T 1 of the memory cell is in the OFF state so that any problem does not occur. In this way, by boosting the lower potential level of the memory cell, erroneous selection of the non-selection memory cell due to the potential change of the plate can be prevented.

As understood from the description, also in accordance with this embodiment, the voltage amplitude of the data lines and that of the voltage to be written into the memory cells can be determined independently from each other. Therefore, by decreasing the charging/discharging current for the data lines which provide a large parasitic capacitance and also a large charging/discharing current and increasing the voltage amplitude of the plates which provide a small parasitic capacitance, power consumption in the memory can be reduced while assuring a sufficient memory cell signal. In this case, setting the voltage amplitude of the data lines at a larger value than that of the plates is efficient to realize them. In this embodiment in which the data line voltage amplitude is 1 V, the charging/discharging current can be decreased to {fraction (1/5+L )} of the conventional case where it is 5 V. The data line voltage amplitude may be decreased to the neighborhood of the threshold voltage of the MOS-FETs which constitute the sense amplifier, but it is desired to satisfy, in view of the stability of the operation, the condition, |V tn |÷|V tp <Vd (Vtn: threshold voltage of NMOS, Vtp: threshold voltage of PMOS, Vd: data line voltage amplitude).

Further, in accordance with this embodiment, the precharging potential of the data line is set at an intermediate level between the high potential and the low potential of the data line voltage amplitude. Thus, the power consumption can be further reduced. Moreover, a capacitor in each memory cell is generally made using a thin oxide film. Correspondingly, in this embodiment, the plate potential is set, during the stand-by time of the memory, at an intermediate level between two storage potential level used in the memory cell. Therefore, the electric field applied to the capacitor of the memory cell is made small, thereby improving the reliability of the memory. Further, in this embodiment, the memory cell signal is larger on the high potential side than the low potential side so that the characteristics of data retention and α-ray soft error resistance can be improved.

Further, in accordance with this embodiment, DRAM with a power supply voltage of 1.5 V and reduced power consumption can be realized. Therefore, DRAM which can be operated during, both the stand-by and operation of a memory can be realized. Also, DRAM can be operated with a power supply voltage so that exchange between a normal power supply source and battery can be easily made. Thus, the application of DRAM can be extended.

A further embodiment of the present invention will be explained with reference to FIGS. 64A and 64B . This embodiment is also directed to a method of writing a memory cell signal from a plate thereby to decrease the data line voltage amplitude. This embodiment is different from the embodiment of FIG. 63A in only that a plate wiring is provided for each word line. The other circuit arrangement and operation are the same as the embodiment of FIGS. 64A and 64B . In this embodiment, the plate wiring is provided for each word line so that even when the plate potential varies, the potential at the storage node of each memory cell connected with a non-selected word line does not vary. Namely, even when the voltage amplitude of the plate is made laerger than the voltage difference between the lower level side potential of a memory cell signal and 0 V, a non-selected memory cell will be not in the selection state. Therefore, the voltage to be written from the plate can be larger than in the embodiment of FIGS. 63A and 63B and so the voltage to be written in the memory cell is made larger than the power supply voltage. In this way, in accordance with this embodiment, the storage voltage in the memory cell can be further increased so that the characteristics of date retention and a-ray soft error resistance can be further improved. Thus, the power supply voltage can be easily decreased, which is efficient to operate a memory at a low voltage.

Incidentally, in the waveform shown in FIG. 64B , the low level side potential on the data line is set at a level higher than 0 V, but the low and high level potentials may be set at 0 V and 0.6 V, respectively. In this case, the intermediate level of the word line voltage is required to be decreased correspondingly.

FIGS. 65A to 69 B show concrete examples of several controlling circuits for the memory arrays used in the embodiments of FIGS. 61A to FIG. 64 B. Although these are directed to the case of a power supply voltage of 5 V, they may be applied to the case of a power supply voltage of 1.5 V as long as the voltage relation is correspondingly changed.

FIG. 65A shows a concrete circuit configuration of the X decoder. In FIG. 65A , XD 1 is a decoder section which serves to select one word line in response to an address signal; W is a word line; numeral 54 is a node to which a voltage VCR of 7 V is applied; and x is a word line driving signal.

The operation of the circuit shown in FIG. 65A will be explained with reference to the operation waveforms shown in FIG. 65 B. During the stand-by time of a memory, an output node of the decoder XD 1 is 0 V. Then, a signal {overscore (φ 1 +L )} is 5 V and a node 55 is 7 V. Therefore, a transistor T 51 is the OFF state whereas a transistor T 52 is the ON state, and so the word line W is 0 V. Now, it is assumed that after the signal {overscore (φ 1 +L )} has become 0 V, an address signal is applied to the memory whereby the output node of the decoder XD 1 becomes 5 V. Thus, the node 55 becomes 5 V, and so T 51 and T 52 are turned ON and OFF, respectively. Thus, the signal φ x appears on the word line W. Then, φ x is 7 V so that the word line becomes also 7 V. Thereafter, x lowers to 5 V so that the word line W becomes also 5 V. Further, when the node 52 of the decoder XD 1 becomes 0 V and then the signal {overscore (φ 1 +L )} becomes 5 V, the node 55 becomes 7 V so that the word line W returns to 0 V.

FIG. 66A shows a concrete configuration of the circuit for generating the word line driving signal used in the circuit of FIG. 65 A. The operation of this circuit will be explained with reference to FIG. 66 B. While a signal φ 2 is 0 V, a transistor T 62 is ON and a transistor T 61 is OFF so that an output node 62 is 5 V. When φ 2 becomes 5 V, T 62 and T 61 are turned ON and OFF, respectively so that the output node 62 is boosted to 7 V by a capacitor C 61 . Thereafter, when φ 2 returns to 0 V, the node 62 also returns to 5 V. In this way, the φ x signal is generated.

FIG. 67 shows a concrete configuration of the circuit for generating the voltage VCR a 7 V. As seen from the figure, this voltage is generated by rectifying a pulse signal 3 through capacitor C 71 and transistors T 71 and T 72 . The value of this voltage is decided by the threshold voltages of transistors T 73 , T 74 and T 75 .

FIG. 68A shows a concrete configuration of the circuit for generating the sense amplifier driving signal. In FIG. 68A , CSP and CSN are a sense amplifier driving signal line, respectively. A 81 is a differential amplifier. Vr 1 is a reference voltage (3 V) generated by the reference voltage generating circuit (not shown). Vdp is a data line percharge voltage (4 V) which is generated on the basis of the reference voltage as mentioned previously.

The operation of this circuit will be explained with reference to FIG. 68 B. During the stand-by time of a memory, φ p is 5 V, φ sap is 5 V and φ san is 0 V so that CSP and CSN are precharged at 4 V. When {overscore (φ p +L )} becomes 0 V, a word line is selected whereby a memory cell signal appears on a data line. Thereafter, φ sap and φ san become 0 V and 5 V, respectively. Thus, transistors T 81 and T 82 are turned ON so that CSP and CSN become 5 V and 3 V, respectively. Thereafter, φ sap becomes 5 V, φ san becomes 0 V and {overscore (φ p +L )} becomes 5 V so that CSP and CSN are precharged at 4 V.

FIG. 69A shows a concrete configuration of the plate driving circuit. In FIG. 69A , A 91 is a differential amplifier; Vr 2 is a reference voltage (2 V) generated by the reference voltage generating circuit; and numeral 93 is an output node. The operation of this circuit will be explained referring to FIG. 69 B. While φ 4 is 0 V, a transistor T 91 is ON and a transistor T 92 is OFF so that the output is 5 V. When φ 4 becomes 5 V, T 91 and T 92 are turned OFF and ON, respectively so that the output becomes 2 V. Thereafter, when φ 4 becomes 0 V, the output returns to 5 V.

FIGS. 70A to 70 D show embodiments of a memory chip which permits DRAM operating at a power supply voltage of 1.5 V to be operated also at the power supply voltage of 3 V.

FIG. 70A shows a memory chip which permits DRAM to be exchanged between for 1.5 V and 3 V through the selective bonding of the chip in packaging it. In FIG. 70A , numeral 101 is a memory chip; and numeral 102 is a peripheral circuit which is composed of an input/output interface circuit and a circuit for generating timing pulses for controlling the memory array. The input/output interface circuit is disclosed in e.g. the data book for a 4-bit single chip microcomputer published by Nippon Electric Co., Ltd., pages 997-999. L is a voltage limiter which serves to drop the voltage input from the outside to 1.5 V (Vc 1 ) for internal use. Numerals 104 to 106 are bonding pads (numerals 105 and 106 are for power supplies and numeral 104 is for control of the voltage limiter).

The manner of operating such a chip at a power supply voltage of 1.5 V is as follows. The bonding pad 106 is connected with a power supply pin for the package. It is assumed that when a node 107 is at a low level, the voltage limiter L is OFF to provide an output terminal with high impedance, and when a node 107 is at a high level, it is ON thereby to operate. Therefore, the bonding pad 104 is not connected with anywhere but is placed in the open state. Also the bonding pad 105 is placed in the open state. Thus, the voltage of 1.5 V is applied to the memory array 103 and the peripheral circuit 102 . On the other hand, the manner of operating the chip at a power supply voltage of 3.3 V is as follows. The bonding pad 105 is connected with the power supply pin for the package. The bonding pad 104 is also connected with the power supply pin thereby to place the node 107 in the high level. Thus, the voltage limiter L becomes ON, The bonding pad 106 is placed in the open state. Thus, the voltage lowered to 1.5 V by the voltage limiter is applied to the peripheral circuit 102 and memory array 105 .

In this way, in accordance with this embodiment, the circuits in the chip other than the input/output interface circuit are always operated at a fixed voltage so that the operation speed and power consumption can be held substantially constant. Such a memory chip is convenient to use for a user. Further, two kinds of products can be made from one chip so that the production cost of the memory chip can be reduced. Moreover, the products are classified according to the bondings so that the number of the products can be easily adjusted. Further, in this embodiment, the ON/OFF is switched according the bonding, but is may be switched by using fuse provided on the chip. Also, it may be controlled by using the result of a logic gate provided in the memory chip to which plural input signals to the memory chip are applied. Incidentally, the idea of this embodiment may be also applied to the other chip in which the circuits indicated by numerals 102 and 103 are a combination of a memory circuit and a logic circuit or only logic circuits.

FIG. 70B shows an embodiment in the case where the above switching is carried out through the master-slice of aluminium (Al). In FIG. 70B , At master-slice portions are represented by SW 1 and SW 2 . In the case where the chip shown in FIG. 70B is to be operated at a power supply voltage of 1.5 V, both switches SW 1 and SW 2 are connected with their “b” side. Thus, the power supply voltage of 1.5 V is directly applied from the bonding pad of the power supply to the memory array 103 and peripheral circuit 102 . The voltage limiter is OFF since the input node 107 is at the low level. On the other hand, in the case where the chip is to be operated at a power supply voltage of 3.3 V, both switches SW 1 and SW 2 are connected with their “a” side (as shown in FIG. 70 B). Thus, the input node 107 is at the high level so that the voltage limiter becomes ON. Therefore, the voltage lowered to 1.5 V by the voltage limiter is applied to the memory array and peripheral circuit.

In this way, also in accordance with this embodiment, the circuits in the chip other than the input/output interface circuit are always operated at a fixed voltage so that the operation speed and power consumption can be held substantially constant. Such a memory chip is convenient to use for a user. Further, two kinds of products can be made from one chip so that the production cost of the memory chip can be reduced. Moreover, the products are classified according to the Al master-slice so that a small number of bonding pads are required thereby reducing the chip area.

FIG. 70C shows an embodiment of the memory chip which can be used even when the power supply voltage is continuously varied in the range of 1.5 V to 3.3 V. In this embodiment, the characteristic of the voltage limiter as shown in FIG. 70D is adopted. Specifically, the output is fixed to 1.5 V even when the power supply voltage is varied from 1.5 V to 3.3 V. Also the memory array and the peripheral circuit are adapted to operate at 1 V.

In accordance with this embodiment, when the power supply voltage is varied in the range of 1.5 V to 3.3 V, the memory array and the peripheral circuit ate operated at 1 V. Therefore, with any optional power supply voltage between 1.5 V and 3.3 V, the memory chip can be operated. The circuits in the chip are always operated at the fixed voltage of 1 V so that the operation speed and power consumption can be held substantially constant. Such a memory chip is convenient to use for a user. Further, the ON/OFF control of the voltage limiter is not required so that the chip arrangement can be simplified. Incidentally, in this embodiment, 1.5 V corresponds to one battery and 3.3 V corresponds to two batteries so that the memory chip can be operated using one. battery or two batteries.

In accordance with this embodiment, the power consumption in DRAM can be greatly reduced. Particularly, the voltage amplitude of the data lines in operating the sense amplifiers can be greatly reduced as compared with the conventional case so that the charging/discharging current on the data line can be reduced. Further, the memory cell signal can be increased by rewriting it from a plate. Thus, the characteristics of data retention and a-ray soft error resistance of DRAM can be improved. Accordingly, reduced power supply voltage and reduced power consumption in DRAM can be realized so that DRAM can be operated using a battery(s).

Explanation will be given for several embodiments of improvements of the sense amplifier in their circuit configuration and operation which can assure the high speed operation of a memory at a relatively low power Supply voltage (2 V or less). In the embodiments explained hereinafter, the sense amplifier is improved on the basic premise of a precharging system of precharging the potential on a data line at an intermediate level between the high potential and low potential appearing on the data line (simply called “half precharge system”) in which with the high potential of a power supply voltage of V cc and the low potential of 0 V, the data line is precharged at {fraction (1/2+L )} V cc .

FIG. 71A shows the circuit arrangement in accordance with one embodiment of the present invention in which MOS-FETs (Q 1 ′, Q 2 ′, Q 3 ′ and Q 4 ′) each having a low threshold voltage Vth is used in a sense amplifier. The operation of the data line in the case where it is operated at a low voltage amplitude (1 V) will be explained with reference to the waveform chart of FIG. 71 C. When the voltage on a word line W 0 is boosted from VSS (0 V) to VDH (1.5 V), data stored in a storage capacitor Cs is read out on a data line D. Next, when P 1 P is varied from VDL (1.0 V) to VSS (0 V), and P 1 N is varied from VSS (0 V) to VDL (1.0 V), transistors QP and QN for driving sense amplifiers are turned ON and OFF so that a sense amplifier driving line varies from HVC (0.5 V) to VDL (1.0 V) and another sense amplifier driving line CSN varies from HVC (0.5 V) to VSS (0 V). Then, in the sense amplifier in this embodiment, the transistors (Q 1 ′, Q 2 ′, Q 3 ′ and Q 4 ′) each having a low threshold voltage are used so that the gate-source (drain) voltage sufficiently exceeds the threshold voltage. Thus, the transistors in the sense amplifier are sufficiently turned ON thereby to sufficiently amplify the signal voltage on the data line. On the other hand, in the sense amplifier constituted by transistors each having an ordinary (i.e. relatively high), the gate-source (drain) voltage becomes close to the threshold voltage. Thus, the transistors in the sense amplifier are not sufficiently turned ON so that the signal voltage on the data line can not be amplified. The subsequent operation of the data line is the same as the conventional DRAM. FIG. 71B shows the waveform chart in the case where the data line is operated at the voltage amplitude of 1.5 V. In this case, the charging/discharging speed of the data line is slightly increased because of the use of the sense amplifier in accordance with this embodiment.

FIG. 71D is a graph for explaining the advantages or merits of this embodiment. In the graph, VDLmin is the data line charging/discharging voltage when the sense amplifier reaches its operation limit. IDS is a sum of the currents flowing between the gates and sources (drains) in the all the sense amplifiers with the gate-source (drain) voltage of 0 V in 64 Mbit DRAM in which with respect to Q 1 , Q 2 , Q 3 and Q 4 ′) W/L=2 μpm/0.5 μm and 16000 sense amplifiers are operated. The current flowing between the drain and source when the gate-source (drain) voltage is set at 0 V is minutely disclosed in R. M. Swanson and J. D. Meindle “Ion-Implanted Complementary MOS Transistors in Low-Voltage Circuits”, Vol. SC7, No. 2, pp. 146-153. It is assumed that the relation between the gate-source voltage VGS of a MOS transistor and the square root ID the drain-source current can be expressed by ID=A VGS÷8. VTO in the graph of FIG. 71D represents the value of VGS when ID=0 in the equation.

FIGS. 71E and 71F are graphs showing the relation between VTO and the channel length Lg of the transistor. The sense amplifier (Q 1 ′, Q 2 ′, Q 3 ′ and Q 4 ′) in accordance with this embodiment uses low Vth MOS transistors, the other sense amplifier uses normal Vth MOS transistors, and the conventional sense amplifier uses high Vth MOS transistors. In this case, a comparatively long channel length Lg of 0.5 μm is adopted. This intends to prevent the threshold voltage of the transistors in the sense amplifier from being varied due to processing variations of Lg and so the sensibility of the sense amplifier from being reduced. In the transistors other than those in the sense amplifier, a comparatively short channel length Lg a e.g. 0.3 μm is adopted in order to provide a high driving capability.

The operation of this embodiment is different from the case of using the conventional sense amplifier when VDL is a low voltage of 1.0 V. or so. More specifically, in the case where the high Vth MOS transistors (VTO=0.5 V) as shown in FIGS. 71E and 71D are used in the sense amplifier, as seen from the graph of FIG. 71D , the sense amplifier will not be operated at VDL of 1.2 V (the worst value of VTO is 0.6 V). On the other hand, in the case the low Vth MOS transistors are used in the sense amplifier in accordance with this embodiment, the sense amplifier can still operate at VDL of 1.2 V. This is because VTL is a sufficiently small value of 0.4 V (worst or largest value) for the gate-source (drain) voltage of 0.6 V in the sense amplifier. In accordance with this embodiment, the operation range of the sense amplifier can be extended to VTL≧0.8 V. Then, the current IDS max flowing the drain and sources in the sense amplifiers is 100 μA (when 16000 sense amplifiers are operated), which is negligibly small as compared with the charging current on the data line.

The low Vth MOS transistors as shown in FIGS. 71E and 71F can be made by varying the amount of ion implanatation in masking the sense amplifier section. Further, the same effect as the low voltage operation of sense amplifiers can be realized by using low Vth MOS transistors in the parts where a low voltage is provided between the gate and source of each transistor (e.g. transistors for switching input/output lines in sharing a memory array). Moreover, the same effect can be also obtained by depiction type MOS transistors in place of the low Vth MOS transistors. In this case, during the precharging time when the sense amplifiers are not operated, the substrate potential of the N channel MOS transistors in the sense amplifiers is raised (that of the P channel MOS. transistors is lowered) so as not to conduct a current between the data lines.

Accordingly, in accordance with this embodiment, a memory circuit which can operate at a comparatively low power supply voltage without injuring the speed performance can be realized. The idea in this embodiment can also applied to the circuit components other than the sense amplifiers whereby an LSI memory with the performances of a high operation speed and reduced power consumption can be provided. Further, without being limited to the memory LSI, the other LSI such as a logic LSI (e.g. pass gate) which can operate at a comparatively low power supply voltage can also be provided.

FIGS. 72A and 72B show the circuit configuration in accordance with a further embodiment of the present invention in which the conventional sense amplifier driving transistors are connected in parallel in their two sets (QP 1 , QP 2 ; QN 1 , QN 2 ) and the sense amplifier driving lines CSP and CSN are provided with boosting capacitors CBP and CBN, respectively. The substrate potential of P channel MOS transistors constituting a sense amplifier is at the same level as that of the sense amplifier driving lines CSP and CSN.

The operation of the circuit of FIG. 72A will be explained with reference to the waveform chart of FIG. 72 B. When the voltage of a word line W 0 is varied from VSS (0 V) to VDH (1.5 V), the data stored in a storage capacitor CS is read out on a data line D. Next, when P 1 P is varied from VSS (0 V) to VDH (1.5 V), and P 1 N is varied from VDL (1.0 V) to VDB (−0.5 V), sense amplifier driving transistors QP 1 and QN 1 are turned on so that a sense amplifier driving line CSP varies from HVC (0.5 V) to VDL (1.0 V) and another sense amplifier driving line CSN varies from HVC (0.5 V) to VSS (0 V). When PBP is varied from VSS (0 V) to VDL (1.0 V) and PBN is varied from VDL (1.0 V) to VSS (0 V), the sense amplifier driving lines are boosted. Namely, CSP varies from VDL (1.0 V) to VDH (1.5 V) or so and CSN varies from VSS (0 V) to VDB (−0.5 V) or so. Then, by varying P 1 P from VDH (1.5 V) to VSS (0 V) and varying P 1 N from VDB (−0.5 V) to VDL (1.0 V), the electrons injected into the sense amplifier driving lines are not discharged from the sense amplifier driving transistors. Thus, the gate-source (drain) voltage of the transistors (Q 1 , Q 2 , Q 3 and Q 4 ) constituting a sense amplifier becomes VDL/2+0.5 V or so, so that the sense amplifier is sufficiently turned on thereby amplifying the voltages on data lines D and {overscore (D)} to VDL (1.0 V) and VSS (0 V), respectively. After the sense amplifier driving lines have been boosted, P 2 P is varied from VSS (0 V) to VDH (1.5 V) and P 2 N is varied from VDL (1.0 V) to VDB (−0.5 V). Thus, the sense amplifier driving transistors QP 2 and QN 2 are turned on so that the amplification by the sense amplifier can be sufficiently performed. The subsequent operation of the date lines is the same as the conventional system.

In order to provide the boosted voltages on the order shown in FIG. 72B , the capacitance of the boosting capacitors CBP and CBN may be 150 pF or so (assuming that 1000 sense amplifiers each having the data line capacitance of about 300 pF are connected with the sense amplifier driving lines). Any voltage values at the respective terminals other than the values shown in FIG. 72B may be used as long as the voltage amplitude between the sense amplifier driving lines CSP and CSN is larger than that between the data lines D and {overscore (D)}. The voltage of VDH may be generated by boosting VDL or reducing an external power supply voltage. Either CSP or CSN may be boosted. The VDL wiring may be provided with a boosting capacitor CBP for boosting VDL. In this case, the substrate potential of the sense amplifier driving transistors QP 1 and QP 2 is set at the same level as that of VDL. Further, the sense amplifier driving transistors QP 1 , QP 2 , QN 1 and QN 2 may be P channel MOS transistors, N channel MOS transistors or bipolar transistors as long as the potential of the sense amplifier driving line can be varied from HVC to VDL on the side of CSP and can be varied from HVC to VSS on the side of CSN. Further, by boosting the sense amplifier driving lines so that the substrate potential of each transistor is not forward-biased, the latch-up thereof, etc. can be prevented. By placing the substrate potential of Q 3 and Q 4 in the sense amplifier at the same potential level as the sense amplifier driving line CSP or placing that of Q 1 and Q 2 in the sense amplifier at the same potential level as the sense amplifier driving line CSN, the increase of the threshold voltage thereof due to the body effect can be prevented, thereby further improving the operation of the sense amplifiers. Placing the substrate potential in the sense amplifier at the same potential as the sense amplifier driving line can be realized by using the triple well structure of the substrate. Moreover, by using the low Vth MOS transistors in the embodiment of FIG. 71A in the sense amplifier (Q 1 , Q 2 , Q 3 and Q 4 ), the operation at further reduced voltage can be carried out.

Accordingly, in accordance with this embodiment, a memory circuit which can operate at a comparatively low power supply voltage without injuring the speed performance can be realized. The idea in this embodiment can also applied to the circuit components other than the sense amplifiers whereby an LSI memory with the performances of-a high operation speed and reduced power consumption can be provided. Further, without being limited to the memory LSI, the other LSI such as a logic LSI which can operate at a comparatively low power supply voltage can also be provided.

FIGS. 73A to 73 D show the concept of a further embodiment of the present invention.

In the circuit arrangement of FIG. 73B , constant voltage generating circuits LVDH, LVDL and LVDBL are provided in a memory chip in order to generate constant voltages VDH, VDL and VDBL. The constant voltages VDH, VDL, VDBL and VDBH (=VSS) are connected with sense amplifier driving lines CSP (VDH and VDL) and CSN (VDBL and VDBH) through switches SP 1 , SP 2 , SN 1 and SN 2 , respectively. Their voltage relation is VDH≧VDL>VDP (precharge voltage)>VDBL≧VDBH (=ground voltage VSS)≧VBB (substrate voltage).

The operation of this circuit of FIG. 73B will be explained with reference to FIG. 73 A. First, data line D, {overscore (D)} and sense amplifier driving lines CSP, CSN are precharged at a precharge voltage VDP. Next, the switches SP 1 and SN 1 are turned on to vary the voltage of CSP to VDH and that of CSN to VDBH (VSS). Thus, the gate-source (drain) voltage of the transistors in a sense amplifier can be made larger than VDP so that the sense amplifier is sufficiently turned on thereby to amplify the data lines D and {overscore (D)} to about VDL and VDBL, respectively. Next, the switches SP 1 and SN 1 are turned off and the switches SP 2 and SN 2 are turned on. Thus, CSP and CSN become VDL and VDBL, respectively, so that the data lines D and {overscore (D)} can be fixed at VDL and VDBL, respectively. The timing of turning SP 1 and SN 1 OFF and turning SP 2 and SN 2 ON set decided when D and {overscore (D)} become about VDL and VDEL, respectively. Thus, the data line D is prevented from becoming higher than VDL and the data line D is prevented from becoming lower than VDBL. The relation between the values of VDH, VDL and an external power supply voltage V cc may be optionally set (For example, VDH=VCC or VDL=VCC). The voltage of VDH may be also generated by boosting VDL. Further, the substrate voltage VBB is not necessarily required to be lower than VDBH (For example, it may be that VDBH (=VSS)=VBB). Also, the substrate voltage VBB may be applied to the memory array part and the sense amplifier part or either one of them while the ground voltage may be applied to the remaining parts. This can be realized by the triple structure of the substrate.

Accordingly, in accordance with this embodiment, a memory circuit which can operate at a comparatively low power supply voltage without injuring the speed performance can be realized. The idea in this embodiment can also be applied to the circuit components other than the sense amplifiers whereby an LSI memory with the performances of a high operation speed and reduced power consumption can be provided. Further, without being limited to the memory LSI, the other LSI such as a logic LSI which can operate at a comparatively low power supply voltage can also be provided.

In the circuit arrangement of FIG. 73D , constant voltage generating circuits LVDH, LVDL and LVDBL are provided in a memory chip in order to generate constant voltages VDH, VDL and VDBL. The constant voltages VDH, VDL, VDBH and VDBL (=VSS) are connected with sense amplifier driving lines CSP (VDH and VDL) and CSN (VDBH and VDBL) through switches SP 1 , SP 2 , SN 1 and SN 2 , respectively. Their voltage relation is VDH≧VDL>VDP (precharge voltage)>VDBL≧VDBH (=ground voltage VSS)≧VBB (substrate voltage).

The operation of this circuit of FIG. 73D will be explained with reference to FIG. 73 C. First, data lines D, {overscore (D)} and sense amplifier driving lines CSP, CSN are precharged at a precharge voltage VDP. Next, the switches SP 1 and SN 1 are turned on to vary the voltage of CSP to VDH and that of CSN to VDBH. Thus, the gate-source (drain) voltage of the transistors in a sense amplifier can be made larger than VDP so that the sense amplifier is sufficiently turned on thereby to amplify the data lines D and {overscore (D)} to about VDL and VDBL (VSS), respectively. Next, the switches SP 1 and SN 1 are turned off and the switches SP 2 and SN 1 are turned on. Thus, CSP and CSN become VDL and VDBL, respectively, so that the data lines D and {overscore (D)} can be fixed at VDL and VDBL (VSS), respectively. The timing of turning SP 1 and SN 1 off and turning SP 2 and SN 2 on set decided when D and {overscore (D)} become about VDL and VDBL, respectively. Thus, the data line D is prevented from becoming higher than VDL and the data line {overscore (D)} is prevented from becoming lower than VDBL. The relation between the values of VDH, VDL and an external power supply voltage V cc may be optionally set (For example, VDH=VCC or VDL=VCC). The voltage of VDH may be also generated by boosting VDL. Further, the substrate voltage VBB is not necessarily required to be lower than VDBH (For example, VDBH=VBB). Also, the substrate voltage VBB may be applied to the memory array part and the sense amplifier part or either one of them while the ground voltage may be applied to the remaining parts. This can be realized by the triple structure of the substrate.

Accordingly, in accordance with this embodiment, a memory circuit which can operate at a comparatively low power supply voltage without injuring the speed performance can be realized. The idea in this embodiment can also applied to the circuit components other than the sense amplifiers whereby an LSI memory with the performances of a high operation speed and reduced power consumption can be provided. Further, without being limited to the memory LSI, the other LSI such as a logic LSI which can operate at a comparatively low power supply voltage can also be provided.

FIG. 73E is a concrete circuit arrangement of the embodiments of FIGS. 73B and 73D . Only the side of the sense amplifier driving line CSP in FIG. 73C will be explained. In the circuit arrangement of FIG. 73E , the conventional sense amplifier driving transistors are connected in parallel in their two sets (QP 1 , QP 2 ; QN 1 , QN 2 ). And the drain of the P channel MOS transistor QP 1 is set at VDH (e.g. 1.5 V) whereas the drain of the P channel MOS transistor QP 2 is set at VDL (e.g. 1.0 V). Further, the substrate voltage of QP 1 and QP 2 is set at VDH.

The operation of the circuit of FIG. 73E will be explained with reference to the waveform chart of FIG. 73 F. When the voltage of a word line W 0 is varied from VSS (0 V) to VDH (1.5 V), the data stored in a storage capacitor CS is read out on a data line D. Next, when P 1 P is varied from VDH (1.5 V) to VSS (0 V), and P 1 N is varied from VSS (0 V) to VDL (1.0 V), sense amplifier driving transistors QP 1 and QN 1 are turned on so that a sense amplifier driving line CSP varies from HVC (0.5 V) to VDH (1.5 V) and another sense amplifier driving line CSN varies from HVC (0.5 V) to VSS (0 V). Thus, the gate-source (drain) voltage of the transistors Q 3 and Q 4 in a sense amplifier becomes VDL/2+0.5 V or so, so that the sense amplifier is sufficiently turned on thereby amplifying the voltages on a data line D to VDL (1.0 V). Also the gate-source (drain) voltage of the transistors Q 1 and Q 2 in the sense amplifier is increased thereby to amplify a data line to VSS (0 V). Around the time when the voltage of the data line-D exceeds VDL (1.0 V), if P 1 P is varied from VSS (0 V) to VDH (1.5 V) and P 2 P is varied from VDH (1.5 V) to VSS (0 V), QP 1 is turned OFF and QP 2 is turned ON so that CSP varies from VDH (1.5 V) to VDL (1.0 V). Thus, the voltage of the data line D is fixed at VDL (1.0 V). Then, if P 2 N is varied from VSS (0 V) to VDL (1.0 V), the sense amplifier driving transistor QN 2 is turned on so that the amplification by the sense amplifier can be sufficiently performed. The subsequent operation of the date lines is the same as the conventional system.

Any voltage values at the respective terminals other than the values shown in FIG. 73F may be used as long as the voltage of the sense amplifier driving lines CSP is larger than the charging voltage VDL of the data line. The voltage of VDH may be generated by boosting VDL or reducing an external power supply voltage. Further, the sense amplifier driving transistors QP 1 , QP 2 , QN 1 and QN 2 may be P channel MOS transistors, N channel MOS transistors or bipolar transistors as long as the potential of the sense amplifier driving line can be varied from HVC to VDL on the side of CSP and can be varied from HVC to VSS on the side of CSN. By placing the substrate potential of Q 3 and Q 4 in the sense amplifier at the same potential level as the sense amplifier driving line CSP or placing that of Q 1 and Q 2 in the sense amplifier at the same potential level as the sense amplifier driving line CSN, the increase of the threshold voltage thereof due to the body effect can be prevented, thereby further improving the operation of the sense amplifiers. Placing the substrate potential in the sense amplifier at the same potential as the sense amplifier driving line can be realized by using the triple well structure of the substrate. Moreover, by using the low Vth MOS transistors in the embodiment of FIG. 71A in the sense amplifier (Q 1 , Q 2 , Q 3 and Q 4 ), the operation at further reduced voltage can be carried out.

Accordingly, in accordance with this embodiment, a memory circuit which can operate at a comparatively low power supply voltage without injuring the speed performance can be realized. The idea in this embodiment can also be applied to the circuit components other than the sense amplifiers whereby an LSI memory with the performances of a high operation speed and reduced power consumption can be provided. Further, without being limited to the memory LSI, the other LSI such as a logic LSI which can operate at a comparatively low power supply voltage can also be provided.

Incidentally, the voltage relation should not be limited to those as shown in FIGS. 73A to 73 E since the same effect as mentioned above can be obtained by causing the gate-source voltage of the MOS transistors operating with a small amplitude to sufficiently exceed the threshold voltage thereof only during a certain period of the operation.

FIG. 74A shows the circuit arrangement of a further embodiment of the present invention in which plate terminals of the storage capacitors CSs connected with reference data lines DS are adapted to be driven at a time. As a precharge voltage to be applied to a precharge circuit (Q 5 ′, Q 6 ′, Q 7 ′, Q 5 , Q 6 and Q 7 ), a constant voltage VDP, which has the characteristic as shown in FIG. 74E or FIG. 74F , is adopted.

The operation of the circuit of FIG. 74A will be explained with reference to the waveform chart shown in FIG. 74 B. First, when the voltage of a word line W 0 is varied from VSS (0 V) to VDH (1.5 V), the data stored in the storage capacitor CS is read out on the data line {overscore (D)}. Specifically, in the case of reading “1”, CD/(CD+CS)×(VDL−VDP)=0.25 CD/(CD+CS) VOLT is read out whereas in the case of reading “0”, CD/(CD+CS)×(VDP−VSS)=0.75 CD/(CD+CS) volt (where CD is a data line capacitance) is read out. Then, the voltage of a dummy word line DW 0 is varied from VSS (0 V) to VDH (1.5 V) while the voltage of the reference data line D is held at the precharge voltage VDP (0.75 V). Next, the voltage of the plate terminal CSB of the storage capacitor CS′ connected with the data line D is varied from VDP (0.75 V) to HVC (0.5 V). Thus, the voltage of the reference data line {overscore (D)} is lowered by CD/(CD+CS)×(VDP−HVC)=0.25 CD/(CD+CS) volt so that the signal voltage difference between the data lines D and {overscore (D)} is VDL/2×CD/(CD+CS)=0.5 CD/(CD+CS) volt for both cases of reading “1” and “0”. Next, when P 1 P is varied from VDL (1.0 V) to VSS (0 V), and P 1 N is varied from VSS (0 V) to VDL (1.0 V), sense amplifier driving transistors QP 1 and QN 1 are turned on so that a sense amplifier driving line CSP varies from VDP (0.75 V) to VDL (1.0 V) and another sense amplifier driving line CSN varies from VDP (0.75 V) to VSS (0 V). Thus, the gate-source (drain) voltage of the transistors Q 1 and Q 2 in a sense amplifier becomes VDP, so that the sense amplifier is sufficiently turned on thereby amplifying the voltages on a data line {overscore (D)} to VSS (0 V). Also, the gate-source (drain) voltage of the transistors Q 3 and Q 4 in the sense amplifier is increased thereby to amplify a data line D to VDL (1.0 V). Then, if P 2 P is varied from VSS (0 V) to VDL (1.0 V), the sense amplifier driving transistor QN 2 is turned ON so that the amplification by the sense amplifier can be sufficiently performed. The subsequent operation of the data line is the same as the conventional system. The voltage of the plate CSB is varied from HVC (0.5 V) to VDP (0.75 V) before precharging the data lines. The dummy word line DW 0 is varied from VDH (1.5 V) to VSS (0 V) around the time when the data line voltage has been restored to VDP (0.75 V) after the precharging. Although the above explanation is directed to the case where VDP has the characteristic shown in FIG. 74E , the same effect can be obtained also in the case where VDP has the characteristic shown in FIG. 74 F. Further, any voltage values at the respective terminals other than the values shown in FIGS. 74B , 74 E, and 74 F as long as VDP>VDL/2=HVC (FIG. 74 F), or VDP<VDL/2=HVC (FIG. 74 F). As seen from FIGS. 74E and 74F , when VDL is comparatively high, more precisely 1.5 V or more, VDP equals HVC. The operation of this case is the same as the conventional system as shown in FIG. 74 C. Incidentally, the technique for driving the plate voltage has been explained in relation to the embodiments previously mentioned.

In order to drive the plate voltage for dummy word lines at a high speed, as shown in FIG. 74D , a driver consisting of MOS transistors Q 20 and Q 21 (Q 22 and Q 23 ) may be provided on the way of a plate driving line CSL to use signals from the dummy word lines DW 1 and DW 2 as switching signals through gates NAD 1 and NAD 2 . Q 20 , Q 21 , Q 22 , Q 23 , NAD 1 and NAD 2 are arranged cyclically in the memory. But they may be arranged collectively outside the memory array. Although each of NAD 1 and NAD 2 of FIG. 74D is constituted by an OR circuit, it may be constituted by a NOR circuit and an inverter. Further the dummy cell may be in any optional format. Specifically, with the plate voltage for the dummy word lines set at a fixed voltage (VP) as usual, the dummy word line DW 0 may be varied from VDH (1.5 V) to VSS (0 V) when the data line voltage immediately after the precharging becomes HVC (0.5 V). Otherwise, with a MOS transistor for writing provided between CS′ and QW 0 , HVC (1.5 V) may be written.

The voltage of VDP may be generated by boosting VDL or reducing an external power supply voltage. Further, the sense amplifier driving transistors QP 1 , QP 2 , QN 1 and QN 2 may be P channel MOS transistors, N channel MOS transistors or bipolar transistors as long as the potential of the sense amplifier driving line can be varied from HVC to VDL on the side of CSP and can be varied from HVC to VSS on the side of CSN. By placing the substrate potential of Q 3 and Q 4 in the sense amplifier at the same potential level as the sense amplifier driving line CSP or placing that of Q 1 and Q 2 in the sense amplifier at the same potential level as the sense amplifier driving line CSN, the increase of the threshold voltage thereof due to the body effect can be prevented, thereby further improving the operation of the sense amplifiers. Placing the substrate potential in the sense amplifier at the same potential as the sense amplifier driving line can be realized by using the triple well structure of the substrate. Further, by commonly using the sense amplifier driving line CSP or CSN and a wiring for precharging, the precharging speed can be enhanced without increasing the wiring area. Moreover, by using the low Vth MOS transistors in the embodiment of FIG. 71A in the sense amplifier (Q 1 , Q 2 , Q 3 and Q 4 ), the operation at further reduced voltage can be carried out.

Accordingly, in accordance with this embodiment, by varying the operation amplitude of the circuit in accordance with the power supply voltage, a memory circuit which can operate at a comparatively low power supply voltage without injuring the speed performance can be realized. The idea in this embodiment can also be applied to the circuit components other than the sense amplifiers whereby an LSI memory with the performances of a high operation speed and reduced power consumption can be provided. Further, without being limited to the memory LSI, the other LSI such as a logic LSI which can operate at a comparatively low power supply voltage can also be provided.

FIG. 75A shows the circuit arrangement of a further embodiment of the present invention in which a boosting capacitor CB is connected with each data line.

The operation of the circuit of FIG. 75A will be explained with reference to the waveform chart of FIG. 75 B. When the voltage of a word line W 0 is varied from VSS (0 V) to VDH (1.5 V), the data stored in a storage capacitor CS is read out on a data line D. Next, when the voltage of a boosting terminal PCB is varied from VSS (0 V) to VDL (1.0 V), both data lines D, {overscore (D)} are boosted by 0.2 V or so (assuming that CB is about 70 fF). Next, when P 1 P is varied from VDL (1.0 V) to VSS (0 V), and P 1 N is varied from VSS (0 V) to VDL (1.0 V), sense amplifier driving transistors QP and QN are turned on so that a sense amplifier driving line CSP varies from HVC (0.5 V) to VDL (1.0 V) and another sense amplifier driving line CSN varies from HVC (0.5 V) to VSS (0 V). Thus, the gate-source (drain) voltage of the transistors Q 1 and Q 2 a sense amplifier becomes VDL/2+0.5 V or so, so that the sense amplifier is sufficiently turned on thereby amplifying the voltages on the data line {overscore (D)} to VSS (0 V). Also, the gate-source (drain) voltage of the transistors Q 3 and Q 4 in the sense amplifier is increased thereby to amplify the data line D to VDL (1.0 V). The subsequent operation of the data lines is the same as the conventional system. In this case, the voltage at the boosting terminal PCB is varied from VDL (1.0 V) to VSS (0 V) before precharging the data lines.

Any voltage value at the respective terminals other than the values shown in FIG. 75B as long as in driving the sense amplifier, a voltage difference between the data line voltage and VSS is VDL/2 or more. Further, the boosting voltage may be applied with the phase reverse to the case mentioned above so that both voltages of the data lines D and {overscore (D)} are lowered. Also in this case, the above voltage difference in driving the sense amplifier has only to be required to be VDL/2 or more. The boosting line and the sense amplifier CSP (or CSN) may be commonly used. Further, the sense amplifier driving transistors QP and QN may be P channel MOS transistors, N channel MOS transistors or bipolar transistors as long as the potential of the sense amplifier driving line can be varied from HVC to VDL on the side of CSP and can be varied from HVC to VSS on the side of CSN. By placing the substrate potential of Q 3 and Q 4 in the sense amplifier at the same potential level as the sense amplifier driving line CSP or placing that of Q 1 and Q 2 in the sense amplifier at the same potential level as the sense amplifier driving line CSN, the increase of the threshold voltage thereof due to the body effect can be prevented, thereby further improving the operation of the sense amplifiers. Placing the substrate potential in the sense amplifier at the same potential as the sense amplifier driving line can be realized by using the triple well structure of the substrate. Moreover, by using the low Vth MOS transistors in the embodiment of FIG. 71A in the sense amplifier (Q 1 , Q 2 , Q 3 and Q 4 ), the operation at further reduced voltage can be carried out.

Accordingly, in accordance with this embodiment, a memory circuit which can operate at a comparatively low power supply voltage without injuring the speed performance can be realized. The idea in this embodiment can also be applied to the circuit components other than the sense amplifiers whereby an LSI memory with the performances of a high operation speed and reduced power consumption can be provided. Further, without being limited to the memory LSI, the other LSI such as a logic LSI which can operate at a comparatively low power supply voltage can also be provided.

FIG. 76A shows the circuit arrangement of a further embodiment of the present invention in which the data line boosting capacitors CBs in FIG. 75A are connected with the gates of MOS transistors Q 1 and Q 2 constituting a sense amplifier and these gates and CBs are adapted to be separatable from the data lines by MOS transistors.

The operation of the circuit of FIG. 76A will be explained with reference to the waveform chart of FIG. 76 B. As mentioned above, when the word line W 0 becomes a high potential, data is read out on the data line D from the storage capacitor CS. Then, the gate voltage of QA and QB is held at substantially the same potential VDH as the word line W 0 (The value of the voltage CGA may be a value which permits QA and QB to be sufficiently turned on in its precharging). Thus, the data on the data line D is sent to also the gate of Q 1 through QA. Also the reference voltage of D is sent to the gate of Q 2 . Next, sense amplifier driving transistors QP and QN are turned on thereby to vary a sense amplifier driving line CSP from HVC (0.5 V) to VDC (1.0 V) and to vary another sense amplifier driving line CSN from HVC to VSS (0 V). Then, the gate voltage CGA of QA and QB is lowered to the potential of VDL by a capacitor CPC inserted between it and CSN so that QA and QB become their high resistance state, thereby electrically separating the data lines D and {overscore (D)} from gates of Q 1 and Q 2 . Thus, the boosting capacitors CBs boost only the gates of Q 1 and Q 2 so that a sufficient voltage can be obtained with a small capacitance than in the previous embodiment. Thereafter, when the voltage of a boosting terminal PCB is varied from VSS to VDL, both gate voltages of Q 1 and Q 2 are boosted to VD½+0.2 or more. Thus, Q 1 and Q 2 are sufficiently turned ON thereby to amplify the data line {overscore (D)} to VSS at a high speed. Also, the gate-source voltage of Q 3 becomes large thereby to amplify the data line D to VDL at a high speed. The subsequent operation of the data lines and the boosting terminal PCB is the same as in the previous embodiment. Incidentally, precharging of CGA is carried out through QPC 2 during the period when the sense amplifier driving transistor QN is in the ON state. The precharging voltage is VDL (1.0 V). Thus, in precharging CSN, CGA is boosted to about VDH through its capacitive coupling with CPC.

Accordingly, in accordance with this embodiment, a memory circuit which can operate at a comparatively low power supply voltage without injuring the speed performance can be realized. The idea in this embodiment can also be applied to the circuit components other than the sense amplifiers whereby an LSI memory with the performances of a high operation speed and reduced power consumption can be provided. Further, without being limited to the memory LSI, the other LSI such as a logic LSI which can operate at a comparatively low power supply voltage can also be provided.

FIG. 77A shows the circuit arrangement of a further embodiment of the present invention. In this circuit arrangement, the sense amplifier is composed of two stages of a sense amplifier consisting of MOS transistors Q 12 to Q 15 coupled with each other through data lines and capacitors CC and the conventional sense amplifier consisting of MOS transistors Q 1 to Q 4 . The former sense amplifier operates at a higher voltage VDH (1.5 V) than VDL (1.0 V) in the conventional sense amplifier. CHP and CHN are common driving lines for these sense amplifiers.

The operation of the circuit of FIG. 77A will be explained with reference to the waveform chart of FIG. 77 B. As previously mentioned, when the word line W 0 becomes a high potential, data is read out from the storage capacitor CS. The data (change of the potential on the data line) is sent to the sense amplifier consisting of Q 12 to Q 15 through the coupling capacitor CC. Next, when CHP is varied from VPH (0.75 V) to VDH (1.5 V), and CHN is varied from VPH (0.75 V) to VSS, the sense amplifier consisting of Q 12 to Q 15 starts the amplification in accordance with the data on the data line. Then, the gate-source voltage of Q 12 to Q 15 is 0.75 V which is a precharging voltage. This voltage is sufficiently higher than the threshold voltage 0.6 V of the MOS transistors and the capacitance involved at the output of the sense amplifier is {fraction (1/10)} or so (only the capacitances of the gate and CC) of that on the data line so that the sense amplifier can carry out the amplification at a high speed. Thus, the output voltage of VSS (0 V) and VDH (1.5 V) are provided. Next, if CSP and CSN are varied to VDL and VSS as usual, the gate-source voltage in the transistors in the conventional sense amplifier is sufficiently higher than the threshold voltage thereof (1.5 V for NMOS Q 2 and −1.0 V for PMOS Q 3 ) since the input terminal of the conventional sense amplifier consisting of Q 1 to Q 4 is connected with the sense amplifier consisting of Q 12 to Q 15 . Therefore, charging/discharging can be performed at a high speed for the data lines. The minimum value of the data line voltage amplitude in this embodiment is theoretically 0.6 V where the maximum value of the gate-source voltage of PMOSs (Q 3 , Q 4 ) equals the threshold voltage thereof. Considering the operation speed, that voltage amplitude is actually about 0.8 V.

Further, in accordance with this embodiment, it is possible to set the low level of CHN at a negative value so that the gate-source voltage of PMOS can be further increased which permits the operation at a further reduced voltage. For example, if the low level of CHN is set at −0.5 V, with the gate-source voltage of 0.8 V which allows a normal operation, the data line voltage amplitude can be reduced to 0.3 V which is lower than the threshold voltage of the transistors in the sense amplifier.

Further, also in this embodiment, during the precharting time, the data lines are short-circuited and precharged by the precharging signal PC as in the embodiment of e.g. FIG. 71A , but further in this embodiment, the output terminal of the sense amplifier consisting of Q 12 to Q 15 is also short-circuited and precharged. To this end, transistors Q 16 , Q 17 and Q 18 are provided. The precharging voltage is 0.75 V which is ½ of VDH (1.5 V). Therefore, the amplitude of the precharging signal PC may be 1.35 V or more.

In this way, in accordance with this embodiment, even if the voltage amplitude of the data lines is smaller than the threshold voltage of the transistors in the sense amplifier for driving the data lines, the gate-source voltage thereof in driving can be made sufficiently higher than the threshold voltage, which makes it possible to realize the high speed operation and reduced power consumption. Thus, in accordance with this embodiment, a memory circuit which can operate at a substantially low power supply voltage without injuring the speed performance thereof can be provided. Further, the gist of the present invention is that by decreasing the voltage amplitude of signal lines (data lines in this embodiment) with large load capacitance, the circuit for driving the signal lines is driven with a voltage amplitude which is sufficiently larger than the operating threshold voltage of the elements constituting the sense amplifier. Therefore, the idea in this embodiment can also be applied to the circuit components other than the sense amplifiers whereby an LSI memory with the performances of a high operation speed and reduced power consumption can be provided. Further, without being limited to the memory LSI, the other LSI such as a logic LSI which can operate at a comparatively low power supply voltage can also be provided. Moreover, by optimizing the combination of a small or large voltage amplitude and a threshold voltage, an LSI with the performances of high speed operation and reduced power consumption can be provided. For example, by using depletion type MOS-FETs for a part of Q 1 to Q 4 , further high speed operation can be realized.

FIG. 78A is a schematic view of the circuit arrangement and section of a further embodiment of the present invention. This circuit serves to control the substrate voltage VBB of transistors in a sense amplifier thereby to optimize the threshold voltage VT thereof for operation. To this end, this circuit is composed of an MOS transistor for monitoring the threshold voltage, a reference voltage (VR) generating circuit, a comparator circuit COMP and a substrate voltage (VBB) generating circuit.

The operation of FIG. 78A will be explained with reference to FIG. 78B which represents a relation between VBB and VT. The threshold voltage VT of a MOS transistor is varied by varying the substrate voltage VBB thereof. For example, as seen from FIG. 78B , in the case of NMOS, if VBB is increased in its negative direction, the threshold voltage VT is enhanced whereas if VBB is decreased in the same direction, VT is lowered. In order to operate a sense amplifier at a low voltage (1.0 V or so) and also at a high speed, the threshold voltage may be lowered. To this end, in accordance with this embodiment, as seen from FIG. 78A , the threshold voltage of a MOS transistor in diode-connection is monitored through its constant current driving, the monitored threshold voltage is compared with the reference voltage VR by the comparator circuit COMP, and an output voltage from the VBB generating circuit is controlled by the output from the comparator circuit so that the threshold voltage of the monitoring MOS transistor equals the reference voltage VR. Thus, even if the threshold voltage of the MOS transistor is located at a point b higher than a point a indicative of an optimum value due to fabrication variation, by lowering VBB to VB 1 , the threshold voltage can be shifted so as to be equal to VR. Further, if the threshold voltage is located at a lower point (point c ), by enhancing VBB to VB 2 , the threshold voltage can be also shifted to a point e so as to be equal to VR. Therefore, in accordance with this embodiment, a sense amplifier stabilized against fabrication variation can be provided. Further, by setting VR at (a point f ) lower than (the standard point a ) during the operation time and setting it at (a higher point g ) during the stand-by time, the high speed operation during the operation time and the reduced power consumption can be simultaneously realized, Moreover, with the well provided with the same circuit, during the operation time, VR is set negative for NMOS and positive for PMOS in order to place their threshold voltage in a depletion type whereas during the stand-by time, it is set positive for NMOS and negative for PMOS to place their threshold voltage in an enhancement type which is normal. Thus, the high speed operation and low voltage amplitude can be further advanced. In the case where the substrate voltage is required to be varied at a high speed because the operation cycle is short, the triple well structure may be used to separate the substrate part corresponding to the sense amplifier section whereby reduced power consumption can be realized also for the VBB generating circuit.

FIG. 78C shows a concrete structure of FIG. 78 A. In FIG. 78C , QB 1 and QB 2 are MOS transistors for monitoring; QB 3 to QB 8 constitute a comparator; OSC is an oscillating circuit for the VBB generating circuit; and INV 1 , INV 2 , C 2 , C 3 and QB 9 to QB 12 constitute the VBB generating circuit. It should be noted that two stages of monitoring MOS transistors are connected for the purpose of an optimum bias for the comparator circuit. Correspondingly, VR is required to be twice as large as an objective threshold voltage. Incidentally, the number of the stages of the monitoring transistors is not limited but may be any number which permits an input voltage for the comparator circuit to be optimized. Further, the rectifying circuit (C 2 , C 3 and QB 9 to QB 12 ) in the VBB generating circuit is adapted to generate a double voltage in order to extend the control range of the threshold voltage, but this may be changed in accordance with the rate of change for the operation voltage of the sense amplifier or the substrate voltage. In this way, in accordance with this embodiment, the threshold voltage in the sense amplifier can be stabilized regardless of fabrication variation and also can be varied in the operation time and stand-by time so that DRAM with the characteristics of a high speed and reduced power consumption can be provided.

Accordingly, in accordance with this embodiment, a memory circuit which can operate at a comparatively low power supply voltage without injuring the speed performance can be realized. The idea in this embodiment can also be applied to the circuit components other than the sense amplifiers whereby an LSI memory with the performances of a high operation speed and reduced power consumption can be provided. Further, without being limited to the memory LSI, the other LSI such as a logic LSI which can operate at a comparatively low power supply voltage can also be provided. Incidentally, the gist of the present invention is that means of detecting the operation threshold voltage of the elements is provided and the threshold voltage is controlled by an output from the means so that it is an optimum value for circuit operation and so the circuit arrangement should not be limited to the arrangement mentioned above.

The present invention has been explained in relation to DRAM, but may be applied to an LSI in any form including a random access memory (RAM) (dynamic or static), a read only memory (ROM), a logic LSI such as a microcomputer, etc. Further, the elements or devices to be used may be bipolar transistors, MOS transistors, the combination thereof, or transistors made of the material e.g. GaAs other than Si.

Accordingly, in accordance with the present invention, a memory circuit which can operate at a comparatively low power supply voltage without injuring the speed performance can be realized. This memory circuit can be used as a memory for battery back-up or battery operation. The idea in this embodiment can also be applied to the circuit components other than the sense amplifiers whereby an LSI memory with the performances of a high operation speed and reduced power consumption can be provided. Further, without being limited to the memory LSI, the other LSI such as a logic LSI which can operate at a comparatively low power supply voltage can also be provided.

Further, in accordance with the present invention, one chip ULSI which can operate in accordance with a wide range of power supply voltage can be realized. Also, the ULSI with reduced power consumption can be accomplished. One chip ULSI which can correspond to a number of input/output levels can also be realized.

It is further understood by those skilled in the art that the foregoing description is preferred embodiments of the disclosed devices and that various changes and modifications may be made in the invention without departing from the spirit and scope thereof.

Claims

1. A semiconductor device comprising:a plurality of data line pairs, a plurality of word lines intersecting said plurality of data line pairs, memory cells located at the intersecting points, sense amplifiers each for amplifying a difference voltage of a data line pair of said plurality of data line pairs to a first voltage in a term of an amplifying operation, and a common driving line pair for driving said sense amplifiers; wherein the voltage amplitude between said common driving line pair is made larger than the maximum value of said first voltage between the data line pair in a part of the term of the amplifying operation.

2. A semiconductor device according to claim 1:wherein the common driving line pair is one of a plurality of common driving line pairs and, wherein the voltage of one of said common driving line pairs is boosted by boosting capacitors.

3. A semiconductor device according to claim 1 further comprising:first, second and third power supply lines, and three switches connecting said first, second and third power supply lines with said common driving line pair respectively; wherein the voltage between said first and second power supply lines is larger than the voltage between said second and third power supply lines which is substantially equal to the maximum value of said first voltage between the data line pair.

4. A semiconductor device according to claim 3,wherein one of the voltages of the power supply lines is generated on the chip.

5. A semiconductor device comprising:a plurality of data lines, a plurality of word lines intersecting the plurality of data lines, memory cells located at the intersecting points, sense amplifiers each for amplifying a memory cell signal read out on each of the data lines, common driving lines for driving said sense amplifiers, and an internal voltage generator to generate a first internal voltage; wherein said first internal voltage is substantially an intermediate value between a first external voltage and a second external voltage when the difference between the first and second external voltages is larger than a first reference voltage, whereas the difference between the first internal voltage and one of the external voltages is made constant when the difference between the first and the second external voltages is larger than a second reference voltage.

6. A semiconductor device comprising:a plurality of data lines, a plurality of word lines intersecting the plurality of data lines, memory cells located at the intersecting points, sense amplifiers each for amplifying a memory cell signal read out on each of the data lines, and common driving lines for driving said sense amplifiers; wherein when said sense amplifiers start to operate, voltage of the data lines is varied to effectively boost an absolute value of the gate-source voltage of transistors in each of the sense amplifiers.

7. A semiconductor device according to claim 6, wherein said voltage of the data lines is boosted by capacitors.

8. A semiconductor device comprising:a plurality of data lines, a plurality of word lines intersecting the plurality of data lines, memory cells located at the intersecting points, sense amplifiers each for amplifying a memory cell signal read out on each of the data lines, and common driving lines for driving said sense amplifiers; wherein said sense amplifiers operate with a voltage amplitude higher than that of the data lines and each of said sense amplifiers includes an inverter which operates with a voltage amplitude as that of the data lines.

9. A semiconductor device comprising:a plurality of data lines, a plurality of word lines intersecting the plurality of data lines, memory cells located at the intersecting points, sense amplifiers each for amplifying a memory cell signal read out on each of the data lines, and common driving lines for driving said sense amplifiers; wherein a threshold voltage of each of the transistors in each of the sense amplifiers is varied in accordance with the operating condition of the sense amplifiers.

10. A semiconductor device according to claim 9, wherein said threshold voltage is varied dynamically.

11. A semiconductor device according to claim 10, wherein said threshold voltage is varied in range including 0 V.

12. A semiconductor device according to claim 10, wherein said threshold voltage is varied by varying a substrate voltage.

13. A semiconductor device comprising:a first circuit block having a plurality of circuits and being operative by a first voltage which is defined by a first potential and a second potential; and a voltage generator producing a first bias potential which is determined with reference to the first potential and a second bias potential which is determined with reference to the second potential, wherein each of the plurality of circuits includes a first MISFET with a first conduction type, a second MISFET with the first conduction type, a third MISFET with a second conduction type, and a fourth MISFET with the second conduction type which are coupled in series between the first potential and the second potential, wherein the first bias potential is supplied to the gate of the second MISFET and the second bias potential is supplied to the gate of the third MISFET, and wherein the gate of the first MISFET is prepared to receive a first signal having an amplitude that is smaller than the first voltage and the gate of the fourth MISFET is prepared to receive a second signal having an amplitude smaller than the first voltage.

14. A semiconductor device according to claim 13,wherein each of the plurality of circuits further includes, a first coupling node between the first MISFET and the second MISFET, a second coupling node between the third MISFET and the fourth MISFET, and a third coupling node between the second MISFET and the third MISFET, wherein the first coupling node can output a first output signal having an amplitude that is smaller than a difference voltage between the first potential and the first bias potential, wherein the second coupling node can output a second output signal having an amplitude that is smaller than a difference voltage between the second potential and the second bias potential, and wherein the third coupling node can output a third output signal having an amplitude that is larger than that of the first output signal or the second output signal.

15. A semiconductor device according to claim 13,wherein the channel conductance of the second MISFET is larger than that of the first MISFET, and wherein the channel conductance of the third MISFET is larger than that of the fourth MISFET.

16. A semiconductor device according to claim 13,wherein one of the plurality of circuits is an inverter circuit including the first, second, third, and fourth MISFETs, wherein the inverter circuit further includes a first coupling node between the first MISFET and the second MISFET, a second coupling node between the third MISFET and the fourth MISFET, and a third coupling node between the second MISFET and the third MISFET, wherein the first coupling node can output a first output signal having an amplitude that is smaller than the first voltage, wherein the second coupling node can output a second output signal having an amplitude that is smaller than the first voltage, and wherein the second coupling node can output a third output signal having an amplitude that is larger than that of the first output signal or the second output signal.

17. A semiconductor device according to claim 13, further comprising a second circuit block being operative by a second voltage which is smaller than the first voltage,wherein one of the plurality of circuits is an output circuit which receives a third signal with a first amplitude outputted from the second circuit block and outputs a fourth signal with a second amplitude which is larger than the first amplitude, wherein the output circuit includes a level converter circuit which receives the third signal, a first inverter circuit which receives a set of signals outputted from the level converter circuit, and a second inverter circuit which receives a set of signals outputted from the first inverter circuit and outputs the fourth signal, and wherein each of the level converter circuit, the first inverter circuit, and the second inverter circuit includes the first, second, third, and fourth MISFETs.

18. A semiconductor device according to claim 17, wherein the first amplitude is substantially the same as the second voltage and the second amplitude is substantially the same as the first voltage.

19. A semiconductor device according to claim 13, wherein one of the plurality of circuits is a NAND circuit including the first, second, third, and fourth MISFETs,wherein the NAND circuit further includes a fifth MISFET with the first conduction type having a source-drain path that is coupled in parallel with the source-drain path of the first MISFET and a sixth MISFET with the second conduction type having a source-drain path that is coupled between one end of the source-drain path of the fourth MISFET and the second potential, wherein the NAND circuit further includes a set of first input nodes which are the gates of the first and fourth MISFETs, a set of second input nodes which are the gates of fifth and sixth MISFETs, a first coupling node between the first MISFET and the second MISFET, a second coupling node between third MISFET and the fourth the MISFET, and a third coupling node between the second MISFET and the third MISFET, wherein the set of first input nodes are prepared to receive the first signal and the second signal, respectively, wherein the set of second input nodes are prepared to receive a fifth signal and a sixth signal, respectively, each of the fifth and sixth signals having an amplitude that is smaller than the first voltage, wherein the first coupling node can output a first output signal having an amplitude that is smaller than the first voltage, wherein the second coupling node can output a second output signal having an amplitude that is smaller than the first voltage, and wherein the second coupling node can output a third output signal having an amplitude that is larger than that of the first output signal or the second output signal.

20. A semiconductor device according to claim 13,wherein one of the plurality of circuits is a tri-state output buffer circuit including a NAND circuit, a NOR circuit, and an output driver, and wherein each of the NAND circuit, the NOR circuit, and the output driver includes the first, second, third, and fourth MISFETs.

21. A semiconductor device according to claim 20,wherein the NAND circuit further includes a set of first input nodes which are the gates of the first and fourth MISFETs of the NAND circuit to which a set of first input signals are supplied, and a first output node from which a first output signal is outputted, wherein the NOR circuit further includes a set of second input nodes which are the gates of the first and fourth MISFETs of the NOR circuit to which a set of second input signals are supplied, and a second output node from which a second output signal is outputted, wherein the output driver further includes a set of third input nodes which are the gates of the first and fourth MISFETs of the output circuit, and a coupling node between the second and third MISFETs, wherein the first output node is coupled to one the set of third input nodes and the second output node is coupled to another one of the set of the third input nodes, and wherein the coupling node of the output driver can output a third output signal having an amplitude that is larger than that of the first output signal or the second output signal.

22. A semiconductor device according to claim 21,wherein the amplitude of the third output signal is substantially the same as the first voltage.

23. A semiconductor device according to claim 13,wherein said semiconductor device is formed on a chip, wherein one of the plurality of circuits is an input circuit which receives an input signal from an outside of the chip and includes the first, second, third, and fourth MISFETs, wherein the input circuit further includes a fifth MISFET with the first conduction type having one end of the source-drain path that is coupled to the gate of the first MISFET and having a gate that is coupled to the gate of the second MISFET, and a sixth MISFET with the second conduction type having one end of the source-drain path that is coupled to the gate of the fourth MISFET and having a gate that is coupled to the gate of the third MISFET, wherein the input circuit further includes a first coupling node between the first MISFET and the second MISFET, and a second coupling node between the third MISFET and the fourth MISFET, wherein another end of the source-drain path of the fifth MISFET and another end of the source-drain path of the sixth MISFET are coupled together and the input signal is supplied thereto, wherein the first coupling node can output a first output signal having an amplitude that is smaller than a difference voltage between the first potential and the first bias potential, and wherein the second coupling node can output a second output signal having an amplitude that is smaller than a difference voltage between the second potential and the second bias potential.

24. A semiconductor device according to claim 23, wherein the amplitude of the input signal is substantially the same as the first voltage.

25. A semiconductor device according to claim 13, wherein the first potential is higher than the second potential, the first bias potential is lower than the first potential, and the second bias potential is higher than the second potential.

26. A semiconductor device according to claim 25,wherein the first potential has a first changing rate according to the variation of the first voltage and the second potential has a second changing rate according to the variation of the first voltage, wherein when the first voltage is in a first predetermined voltage range, the first bias potential has a third changing rate according to the variation of the first voltage and the second bias potential has a fourth changing rate according to the variation of the first voltage, and wherein the third changing rate is larger than the fourth changing rate.

27. A semiconductor device according to claim 26,wherein the first changing rate is larger than the second changing rate, and wherein the third changing rate is proportional to the first changing rate, and the fourth changing rate is proportional to the second changing rate.

28. A semiconductor device according to claim 27,wherein the third changing rate is substantially equal to the first changing rate, and the fourth changing rate is substantially equal to the second changing rate.

29. A semiconductor device according to claim 28, further comprising a second circuit block being operative by a second voltage which is smaller than the first voltage,wherein a thickness of a gate insulator layer of said MISFETs in said first circuit block is substantially the same as that of MISFETs included in said second circuit block.

30. A semiconductor device according to claim 29,wherein the first conduction type is a P-channel and the second conduction type is an N-channel, and wherein said semiconductor device is a microprocessor LSI in a chip.

31. A semiconductor device according to claim 26,wherein when the first voltage is in a second predetermined voltage range which is larger than the first predetermined voltage range, the first bias potential has a fifth changing rate according to the variation of the first voltage and the second bias potential has a sixth changing rate according to the variation of the first voltage, and wherein the fifth changing rate is smaller than the third changing rate and sixth changing rate is larger than the fourth changing rate.

32. A semiconductor device according to claim 31, wherein both the fifth and sixth changing rates are half of the first changing rate.

33. A semiconductor device according to claim 31, wherein the second predetermined voltage range is an aging operation voltage range for said semiconductor device.

34. A semiconductor device according to claim 33, wherein the first conduction type is a P-channel and the second conduction type is an N-channel.

35. A semiconductor device according to claim 34, further comprising a second circuit block being operative by a second voltage which is smaller than the first voltage,wherein a thickness of a gate insulator layer of said MISFETs in said first circuit block is substantially the same as that of MISFETs included in said second circuit block.

36. A semiconductor device according to claim 35, wherein said semiconductor device is a microprocessor LSI in a chip.

37. A semiconductor device according to claim 14, wherein the first conduction type is a P-channel and the second conduction type is an N-channel.

38. A semiconductor device according to claim 14, further comprising a second circuit block being operative by a second voltage which is smaller than the first voltage,wherein a thickness of a gate insulator layer of said MISFETs in said first circuit block is substantially the same as that of MISFETs included in said second circuit block.

39. A semiconductor device according to claim 14, further comprising a second circuit block being operative by a second voltage which is smaller than the first voltage,wherein said semiconductor device is a microprocessor LSI chip, and wherein the second circuit block is an internal circuit block and the first circuit block is an interface circuit block between the internal circuit and an outside of the microprocessor LSI chip.

40. A semiconductor device according to claim 14, wherein said semiconductor device is a dynamic random access memory chip.

41. A semiconductor device according to claim 14, further comprising a second circuit block being operative by a second voltage which is smaller than the first voltage,wherein said semiconductor device is a microprocessor LSI chip, wherein a thickness of a gate insulator layer of said MISFETs in said first circuit block is substantially the same as that of MISFETs included in said second circuit block, and wherein the first voltage is an external voltage supplied from an outside of the microprocessor LSI chip.

42. A semiconductor device comprising:a first circuit block being operative by a first voltage; and a second circuit block being operative by a second voltage which is larger than the first voltage and is defined by a first potential and a second potential, wherein said second circuit block includes an output circuit which receives a first signal outputted from the first circuit block and outputs a second signal having an amplitude that is larger than that of the first signal, wherein the output circuit further includes a level converter circuit which receives the first signal, a first inverter circuit, and a second inverter circuit, wherein the level converter circuit includes a 1st MISFET, a 2nd MISFET, a 3rd MISFET, and a 4th MISFET which are coupled in series between the first potential and the second potential, wherein the level converter circuit includes a 5th MISFET, a 6th MISFET, a 7th MISFET, and an 8th MISFET which are coupled in series between the first potential and the second potential, wherein the level converter circuit includes a first coupling node between the 5th MISFET and the 6th MISFET and a second coupling node between the 7th MISFET and the 8th MISFET, wherein the gates and drains of the 1st and the 5th MISFETs are cross-coupled together, wherein the first signal is supplied to the gate of the 4th MISFET and inverted the first signal is supplied to the gate of the 8th MISFET, wherein the first inverter circuit includes a 9th MISFET, a 10th MISFET, an 11th MISFET, and a 12th MISFET which are coupled in series between the first potential and the second potential, wherein the first inverter circuit further includes a third coupling node between the 9th MISFET and the 10th MISFET and a fourth coupling node between the 11th MISFET and the 12th MISFET, wherein the gate of the 9th MISFET is coupled to the first coupling node and the gate of the 12th MISFET is coupled to the second coupling node, wherein the second inverter circuit includes a 13th MISFET, a 14th MISFET, a 15th MISFET, and a 16th MISFET which are coupled in series between the first potential and the second potential, wherein the second inverter circuit further includes a fifth coupling node between the 14th MISFET and the 15th MISFET, wherein the gate of the 13th MISFET is coupled to a third coupling node and the gate of the 16th MISFET is coupled to the fourth coupling node, and wherein the fifth coupling node can output the second signal.

43. A semiconductor device according to claim 42, further comprising a voltage generator producing a first bias potential which is determined with reference to the first potential and a second bias potential which is determined with reference to the second potential,wherein the first bias potential is supplied to the gates of the 2nd, 6th, 10th, and 14th MISFETs and the second bias potential is supplied to the gates of the 3rd, 7th, 11th, and 15th MISFETs.

44. A semiconductor device according to claim 43,wherein the channel conductance of the 2nd, 6th, 10th, and 14th MISFETs is larger than that of the 1st, 5th, 9th, and 13th MISFETs, and wherein the channel conductance of the 3rd, 7th, 11th, and 15th MISFETs is larger than that of the 4th, 8th, 12th and 16th MISFETs.

45. A semiconductor device according to claim 43, wherein the amplitude of the first signal is substantially equal to the first voltage and an amplitude of the second signal is substantially equal to the second voltage.

46. A semiconductor device according to claim 43,wherein the first potential is higher than the second potential, the first bias potential is lower than the first potential, and the second bias potential is higher than the second potential, wherein the first potential has a first changing rate according to the variation of the second voltage and the second potential has a second changing rate according to the variation of the second voltage, wherein when the second voltage is in a first predetermined voltage range, the first bias potential has a third changing rate according to the variation of the second voltage and the second bias potential has a fourth changing rate according to the variation of the second voltage, and wherein the third changing rate is larger than the fourth changing rate.

47. A semiconductor device according to claim 46,wherein when the second voltage is in a second predetermined voltage range which is larger than the first predetermined voltage range, the first bias potential has a fifth changing rate according to the variation of the second voltage and the second bias potential has a sixth changing rate according to the variation of the second voltage, and wherein the fifth changing rate is smaller than the third changing rate and sixth changing rate is larger than the fourth changing rate.

48. A semiconductor device according to claim 47, wherein both the fifth and sixth changing rates are half of the first changing rate.

49. A semiconductor device according to claim 47, wherein the second operating voltage range is an aging operating voltage range for said semiconductor device.

50. A semiconductor device according to claim 43, wherein the 1st, 2nd, 5th, 6th, 9th, 10th, 13th, and 14th MISFETs are P-channel MISFETs and the 3rd, 4th, 7th, 8th, 11th, 12th, 15th, and 16th MISFETs are N-channel MISFETs.

51. A semiconductor device according to claim 50, wherein a thickness of a gate insulator layer of MISFETs in said first circuit block is substantially the same as those of said MISFETs included in said second circuit block.

52. A semiconductor device according to claim 51,wherein said semiconductor device is a microprocessor LSI chip, and wherein the first circuit block is an internal circuit block and the second circuit block is an interface circuit block between the internal circuit and an outside of the microprocessor LSI chip.

53. A semiconductor device comprising:a first node and a second node for receiving a first voltage defined by a first potential and a second potential; a first circuit block including a first gate circuit having a first MISFET with a first conduction type, a second MISFET with the first conduction type, a third MISFET with a second conduction type, and a fourth MISFET with the second conduction type which are coupled in series between the first node and the second node; a bias voltage supplying circuit having a third node coupled to the gate of the second MISFET and a fourth node coupled to the gate of the third MISFET, wherein the bias voltage supplying circuit supplies a first bias potential to the third node and a second bias potential to the fourth node, and wherein the gate of the first MISFET is prepared to receive a first signal having an amplitude that is smaller than the first voltage and the gate of the fourth MISFET is prepared to receive a second signal having an amplitude that is smaller than the first voltage.

54. A semiconductor device according to claim 53,wherein the first potential is higher than the second potential, the first bias potential is lower than the first potential, and the second bias potential is higher than the second potential, and wherein when the first voltage is varied in a predetermined voltage range, the changing rate of the second bias potential is smaller than that of the first potential.

55. A semiconductor device according to claim 54, further comprising:a fifth node and a sixth node for receiving a second voltage defined by a voltage between the second potential and a fifth potential which is higher than the second potential; and a second circuit block, including a second gate circuit having a fifth MISFET with the first conduction type and a sixth MISFET with the second conduction type which are coupled in series between the fifth node and the sixth node and having a logical amplitude of the second voltage, wherein the second voltage is smaller than the first voltage, and wherein a thickness of a gate insulator layer of each of the first to sixth MISFETs is substantially the same.

56. A semiconductor device according to claim 55, wherein the first conduction type is a P-type and the second conduction type is an N-type.

57. A semiconductor device according to claim 53,wherein said semiconductor device is formed on a chip, and wherein the first gate circuit is a tri-state output buffer circuit and outputs one of the first potential, the second potential, and a floating state to an outside of the chip from a coupling node between the second MISFET and the third MISFET.

58. A semiconductor device according to claim 57, wherein the first conduction type is a P-type and the second conduction type is an N-type.

59. A semiconductor device according to claim 53, wherein the first conduction type is a P-type and the second conduction type is an N-type.

60. A semiconductor device comprising:a plurality of memory cells located at the intersection points of a plurality of data line pairs and a plurality of word lines; a plurality of sense amplifiers each for amplifying a difference voltage of a corresponding data line pair of said plurality of data line pairs to a first voltage; a first driving line coupled to first power receiving nodes of said plurality of sense amplifiers; a second driving line coupled to second power receiving nodes of said plurality of sense amplifiers; a precharge circuit for precharging said plurality of data line pairs, said first driving line, and said second driving line to a precharge voltage; a first voltage supplying circuit for supplying the first voltage; a second voltage supplying circuit for supplying a second voltage which is larger than the first voltage; and a switching circuit inserted between said first and second driving lines and said first and second voltage supplying circuits; wherein when said plurality of sense amplifiers begin an amplifying operation, said switching circuit has: a first period for making the voltage between said first and second driving lines larger than the first voltage by making a current path between said second voltage supplying circuit and said first and second driving lines which have been at the precharge voltage; and a second period for making the voltage between said first and second driving lines the first voltage by making a current path between said first voltage supplying circuit and said first and second driving lines after the first period.

61. A semiconductor device according to claim 60,wherein said switching circuit includes a first MISFET having a source-drain path coupled between a first node and said first driving line, a second MISFET having a source-drain path coupled between a second node and said first driving line, and a third MISFET having a source-drain path coupled between a third node and said second driving line, and wherein the first voltage is supplied between the second node and the third node and the second voltage is supplied between the first node and third node.

62. A semiconductor device according to claim 61,wherein each of said plurality of memory cells has a MISFET and a capacitor, wherein each of said plurality of sense amplifiers includes a p-channel MISFET pair cross-coupled with each other and an n-channel MISFET pair cross-coupled with each other, and wherein the first node is coupled with a first potential, the second node is coupled with a second potential lower than the first potential, and the third node is coupled with a ground potential lower than the second potential.

63. A semiconductor device according to claim 62, wherein the precharge voltage is half of the first voltage.

64. A semiconductor device according to claim 60,wherein said semiconductor device is formed on a semiconductor chip, wherein each of said plurality of memory cells has a MISFET and a capacitor, wherein each of said plurality of sense amplifiers includes a p-channel MISFET pair cross-coupled with each other and an n-channel MISFET pair cross-coupled with each other, wherein the precharge voltage is half of the first voltage, and wherein said first voltage supplying circuit includes a voltage generating circuit which receives an operating voltage larger than the first voltage from the outside of the semiconductor chip and generates the first voltage.

65. A semiconductor device according to claim 60,wherein said semiconductor device is formed on a semiconductor chip, wherein each of said plurality of memory cells has a MISFET and a capacitor, wherein each of said plurality of sense amplifiers includes a p-channel MISFET pair cross-coupled with each other and an n-channel MISFET pair cross-coupled with each other, and wherein said second voltage supplying circuit includes a voltage generating circuit which receives an operating voltage smaller than the second voltage from the outside of the semiconductor chip and generates the second voltage.

66. A semiconductor device according to claim 60,wherein said switching circuit includes a first switch coupled between a first node and said first driving line, a second switch coupled between a second node and said first driving line, a third switch coupled between a third node and said second driving line, and a fourth switch coupled between a fourth node and said second driving line, and wherein the first voltage is supplied between the second node and third node and the second voltage is supplied between the first node and the fourth node.

67. A semiconductor device according to claim 66,wherein each of said plurality of memory cells includes a MISFET and a capacitor, wherein each of said plurality of sense amplifiers includes a p-channel MISFET pair cross-coupled with each other and an n-channel MISFET pair cross-coupled with each other, and wherein the first node is coupled with a first potential, the second node is coupled with a second potential lower than the first potential, the third node is coupled with a third potential lower than the second potential, and the fourth node is coupled with a ground potential lower than the third potential.

68. A semiconductor device according to claim 66,wherein each of said plurality of memory cells includes a MISFET and a capacitor, wherein each of said plurality of sense amplifiers includes a p-channel MISFET pair cross-coupled with each other and an n-channel MISFET pair cross-coupled with each other, and wherein the first node is coupled with a first potential, the second node is coupled with a second potential lower than the first potential, the third node is coupled with a ground potential lower than the second potential, and the fourth node is coupled with a negative potential lower than the ground potential.

69. A semiconductor device comprising:a plurality of memory cells located at the intersecting points of a plurality of data lines and a plurality of word lines; an X-decoder for selecting one of the plurality of word lines, driving the selected word line to a first potential, and driving non-selected word lines of the plurality of word lines to a second potential, a plurality of sense amplifiers each coupled to a corresponding data line of said plurality of data lines and for amplifying the corresponding data line to one of a third potential and a fourth potential; a first driving line coupled to first power receiving nodes of said plurality of sense amplifiers; a second driving line coupled to second power receiving nodes of said plurality of sense amplifiers; a sense amplifier driving circuit for driving said first driving line to the third potential and driving said second driving line to the fourth potential, wherein the first potential is higher than the third potential, the third potential is higher than the fourth potential and the fourth potential is higher than the second potential.

70. A semiconductor device according to claim 69,wherein each of said plurality of memory cells includes a switching MISFET and a capacitor having a first electrode coupled to a source-drain path of the switching MISFET and a second electrode, and wherein the second potential is a ground potential.

71. A semiconductor device according to claim 70, further comprising:a plate wiring coupled to the second electrodes of said plurality of memory cells; and a plate driving circuit for driving the plate wiring to the third potential when the plurality of word lines are not selected and driving said plate wiring to a fifth potential lower than the fourth potential when one of the plurality of word lines is selected; a precharge circuit for precharging said plurality of data lines to a precharge voltage having a potential half way between the third and fourth potentials; a voltage generating circuit for generating the fourth and fifth potentials from an operating voltage higher than the fourth and fifth potentials.

72. A semiconductor device comprising:a voltage converter circuit having a first power receiving node coupled with an operating voltage and an output node for outputting an internal voltage; and a circuit block having a second power receiving node coupled to the output node, wherein said semiconductor device has a first operation mode and a second operation mode, wherein when the operating voltage is in a first voltage range, said voltage converter circuit supplied the internal voltage at a first voltage changing rate opposing the change of the operating voltage and at an amplitude smaller than the operating voltage in both the first and second operation modes, and wherein when the operating voltage is in a second voltage range larger than the first operating voltage range, said voltage converter circuit supplies the internal voltage at the first voltage changing rate and at an amplitude smaller than the operating voltage at the first operation mode, and the internal voltage at a second changing rate, which is positive and larger than the first voltage changing rate, opposing the change of the operating voltage in the second operation mode.

73. A semiconductor device according to claim 72,wherein said semiconductor device is formed on a semiconductor chip, wherein said voltage converter circuit has a node for receiving a control signal which indicate the first and second operation modes, and wherein the control signal is generated by information supplied from outside of the semiconductor chip.

74. A semiconductor device according to claim 73, wherein said voltage converter circuit includes:a first reference voltage circuit supplying a first reference voltage to be a standard of the first voltage changing rate, a second reference voltage circuit supplying a second reference voltage to be a standard of the second voltage changing rate, and a switching circuit for selecting one of the first reference voltage and the second reference voltage according to the control signal.

75. A semiconductor device according to claim 72, wherein the first voltage changing rate is smaller than that of the operating voltage.

76. A semiconductor device according to claim 75, wherein the first voltage changing rate is substantially zero.

77. A semiconductor device according to claim 72,wherein the first voltage changing rate is substantially zero, wherein the second operation mode is an aging operation mode of said semiconductor, and wherein said circuit block includes a memory circuit having a plurality of memory cells each having a MISFET and a capacitor.

78. A semiconductor device comprising:a plurality of dynamic memory cells each having a first MISFET with N-type and a capacitor; and a peripheral circuit for selecting one of the plurality of memory cell and read a data stored therein or write a date thereto and including a plurality of second MISFETs with N-type, a plurality of third MISFETs with N-type, a plurality of fourth MISFETs with P-type, wherein said semiconductor device is formed in a semiconductor substrate with P-type, wherein the first MISFETs of the plurality of memory cells are formed in a first semiconductor region with P-type isolated from said semiconductor substrate with P-type by a second semiconductor region with N-type, wherein the plurality of second MISFETs are formed in a third semiconductor region with P-type isolated from said semiconductor substrate with P-type by a fourth semiconductor region with N-type, wherein the plurality of third MISFETs are formed in said semiconductor substrate with P-type, wherein plurality of fourth MISFETs are formed in a fifth semiconductor region with N-type, and wherein said semiconductor substrate is coupled with a ground potential and the first semiconductor region and the third semiconductor region are coupled with a negative potential lower than the ground potential.

79. A semiconductor device according to claim 78, wherein the fourth semiconductor region is electrically connected to the fifth semiconductor region.

80. A semiconductor device according to claim 79, wherein the second, fourth, and fifth semiconductor regions are coupled with a positive bias potential.

81. A semiconductor device according to claim 79,wherein the first semiconductor region is a first P-well, wherein the second semiconductor region is a second N-well formed in the semiconductor substrate and the first P-well is formed in the second N-well, wherein the third semiconductor region is a third P-well, wherein the fourth semiconductor region is a fourth N-well formed in the semiconductor substrate and the third P-well is formed in the fourth N-well, and wherein the fifth semiconductor region is a fifth N-well formed in the semiconductor substrate.

82. A semiconductor device comprising:a plurality of data lines, a plurality of word lines intersecting the plurality of data lines, memory cells located at the intersecting points, CMOS sense amplifiers each for amplifying a memory cell signal read out on each of the data lines to a first potential or a second potential, a precharge circuit for precharging the plurality of data lines to a third potential which is a half of the first and second potentials, and common driving lines for driving said CMOS sense amplifiers; wherein when said CMOS sense amplifiers start to operate, voltage of the data lines is varied to effectively boost an absolute value of the gate-source voltage of transistors in each of the CMOS sense amplifiers.

83. A semiconductor device according to claim 82, wherein said voltage of the data lines is boosted by capacitors and wherein each of the capacitors is provided for a corresponding one of the plurality of data lines and has a first electrode and a second electrode, each of the first electrodes being connected to the corresponding one of the plurality of data lines, and the second electrodes being commonly connected to a capacitor driving line.