Patent Application
20230068911
The present disclosure generally relates to separation of a sapphire or other substrate from a semiconductor LED attached to CMOS substrate.
Various emerging display applications, including wearable devices, head-mounted, and large-area displays require miniaturized chips composed of arrays of microLEDs (μLEDs or uLEDs) with a high density having a lateral dimension down to less than 100 μm×100 μm. MicroLEDs (uLEDs) typically have dimensions of about 50 μm in diameter or width and smaller that are used to in the manufacture of color displays by aligning in close proximity microLEDs comprising red, blue and green wavelengths. Generally, two approaches have been utilized to assemble displays constructed from individual microLED dies. The first is a pick-and-place approach, which comprises picking up and then aligning and attaching each individual blue, green and red wavelength microLED onto a backplane, followed by electrically connecting the backplane to a driver integrated circuit. Due to the small size of each microLED, this assembly sequence is slow and subject to manufacturing errors. Furthermore, as the die size decreases to satisfy increasing resolution requirements of displays, larger and larger numbers of die must be transferred at each pick and place operation to populate a display of required dimensions.
An alternative to pick-and-place manufacture of semiconductor light-emitting devices (LEDs) or microLEDs is provided by wafer scale manufacture. Control electronics on a CMOS die can be directly attached by solder, conductive pillars, or other suitable interconnects to an LED wafer. Unfortunately, processing LED and CMOS connected dies and wafers can be difficult as compared to processing LED die or wafers alone. Complex process steps such as sapphire substrate removal, gallium cleaning, and phosphor attachment must be able to be performed with damaging CMOS die integrity and functionality.
Laser lift-off processes, which involve projecting a laser light source through a transparent material to be absorbed in an adjacent material on the backside, are a particular concern. Confined plasma at the interface between a transparent substrate (e.g. sapphire) and an absorbing material (e.g. GaN) results in lift-off or separation of the materials. Unfortunately, coatings and processing steps associated with CMOS die attachment can interfere with lift-off. For example, underfill coating between a CMOS die or wafer and an LED die or wafer can include unwanted coating of the transparent substrate, which prevents lift-off unless the underfill is first partially removed.
In one embodiment, a method of manufacturing a light emitting diode (LED) device includes forming an LED structure by depositing a plurality of semiconductor layers on a transparent substrate. Trenched metal is placed in the plurality of semiconductor layers, with the trenched metal contacting the transparent substrate. The LED structure is attached to a CMOS structure with electrical interconnects that define a cavity therebetween. Laser light is used to provide laser lift-off of the transparent substrate from the plurality of semiconductor layers.
In some embodiments, an underfill material can be deposited in the cavity.
In some embodiments, the trenched metal is arranged to define a trenched grid.
In some embodiments, the transparent substrate is sapphire.
In some embodiments, the electrical interconnects are electrically conductive pillars.
In some embodiments, the plurality of semiconductor layers are GaN.
In some embodiments, the method of manufacturing a light emitting diode (LED) device includes attaching an LED structure including trenched metal within a plurality of semiconductor layers to a CMOS structure with electrical interconnects that define a cavity therebetween. Laser light is directed to provide laser lift-off of the transparent substrate from the plurality of semiconductor layers.
Non-limiting and non-exhaustive embodiments of the present disclosure are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various figures unless otherwise specified.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. The figures are not drawn to scale. For example, the heights and widths of the CMOS die or wafer are not drawn to scale.
Before describing several exemplary embodiments of the disclosure, it is to be understood that the disclosure is not limited to the details of construction or process steps set forth in the following description. The disclosure is capable of other embodiments and of being practiced or being carried out in various ways.
The term “substrate” as used herein according to one or more embodiments refers to a structure, intermediate or final, having a surface, or portion of a surface, upon which a process acts. In addition, reference to a substrate in some embodiments also refers to only a portion of the substrate, unless the context clearly indicates otherwise. Further, reference to depositing on a substrate according to some embodiments includes depositing on a bare substrate, or on a substrate with one or more films or features or materials deposited or formed thereon.
In one or more embodiments, the “substrate” means any substrate or material surface formed on a substrate upon which film processing is performed during a fabrication process. In exemplary embodiments, a substrate surface on which processing is performed includes materials such as silicon, silicon oxide, silicon on insulator (SOI), strained silicon, amorphous silicon, doped silicon, carbon doped silicon oxides, germanium, gallium arsenide, glass, sapphire, and any other suitable materials such as metals, metal nitrides, III-nitrides (e.g., GaN, AlN, InN and alloys), metal alloys, and other conductive materials, depending on the application. Substrates include, without limitation, light emitting diode (LED) devices. Substrates in some embodiments are exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, e-beam cure and/or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in some embodiments, any of the film processing steps disclosed are also performed on an underlayer formed on the substrate, and the term “substrate surface” is intended to include such underlayer as the context indicates. Thus for example, where a film/layer or partial film/layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film/layer becomes the substrate surface.
The term “wafer” and “substrate” will be used interchangeably in the instant disclosure. Thus, as used herein, a wafer serves as the substrate for the formation of the LED devices described herein.
In one or more embodiments, the transparent substrate comprises one or more of sapphire, silicon carbide, silicon (Si), quartz, magnesium oxide (MgO), zinc oxide (ZnO), spinel, and the like. In one or more embodiments, the substrate is not patterned prior to the growth of the Epi-layer. Thus, in some embodiments, the substrate is not patterned and can be considered to be flat or substantially flat. In other embodiments, the substrate is patterned, e.g. patterned sapphire substrate (PSS).
In some embodiments the transparent substrate can support an epitaxially grown or deposited semiconductor N-layer. A semiconductor p-layer can then be sequentially grown or deposited on the N-layer, forming an active region at the junction between layers. Semiconductor materials capable of forming high-brightness light emitting devices can include, but are not limited to, Group III-V semiconductors, particularly binary, ternary, and quaternary alloys of gallium, aluminum, indium, and nitrogen, also referred to as III-nitride materials. In some embodiments, the III-nitride material comprises one or more of gallium (Ga), aluminum (Al), and indium (In). Thus, in some embodiments, the semiconductor layer comprises one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), and the like. In one or more specific embodiments, the semiconductor layer 104 comprises gallium nitride and is an n-type layer.
Electrical and mechanical connection between the CMOS chip or wafer 210 can be provided by electrically conductive pillars 222. The pillars define a cavity or gap 220 that can be filled with an underfill material to improve mechanical stability and attachment, and also improve electrical isolation.
With reference to
In this embodiment the semiconductor layers 430 include trenched metal 460 that together forms a trenched metal grid 462. In effect, trenches can help define a plurality of spaced mesas that in turn define pixels, with each of the plurality of spaced mesas comprising the semiconductor layers and each of the spaced mesas having a height less than or equal to their width. The trenched metal 460 is deposited in a space between each of the plurality of spaced mesas, the metal both providing optical isolation between each of the spaced mesas and allowing electrical contact with sidewalls of the GaN LED. In one embodiment, electrical contact can include electrically contacting the N-type layer of each of the spaced mesas along sidewalls of the N-type layers. The space between each of the plurality of spaced mesas can result in a pixel pitch in a range of from 1 μm to 100 μm and space between adjacent edges of the p-contact layer of less than 10% of the pixel pitch when the pixel pitch is in a range of from 10 um to 100 um and when the pixel pitch is in a range of 1 um to 10 um, the space gap is less than or equal to 5 μm and greater than 0.5 μm.
In some embodiments, the trenched metal 460 comprises a reflective metal. In some embodiments, the trench metal width is less than or equal to 4 μm and greater than 0.5 μm or less than or equal to 3 μm and greater than 0.5 μm. In some embodiments, the plurality of spaced mesas between trenched metal grid 462 is arranged into pixels, and the pixel pitch ranges from 5 μm to 100 μm or from 30 μm to 50 μm. In some embodiments, the semiconductor layers 430 have a thickness in a range of from 2 μm to 10 μm.
Since the trenched metal 460 is attached between the sapphire 440 and the semiconductor layers 430 of the LED die, sapphire lift-off requires breaking connection with the metal 460. In this embodiment, laser light 402 decomposes the GaN (or other semiconductor material 430) to create separation from the sapphire 440. While the laser energy is not high enough to cause decomposition and direct release of the metal 460, in regions where the area of GaN is sufficiently greater than the area of the metal 460 the force of nitrogen gas expansion from decomposition of GaN causes separation of metal from sapphire.
Having described the invention in detail, those skilled in the art will appreciate that, given the present disclosure, modifications may be made to the invention without departing from the spirit of the inventive concept described herein. Therefore, it is not intended that the scope of the invention be limited to the specific embodiments illustrated and described.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/US2021/020187 | 3/1/2021 | WO |
| Number | Date | Country | |
|---|---|---|---|
| 62987915 | Mar 2020 | US |
