Layer-stacked wiring and method for manufacturing same and semiconductor device using same and method for manufacturing semiconductor device

Abstract

A layer-stacked wiring made up of a microcrystalline silicon thin film and a metal thin film is provided which is capable of suppressing an excessive silicide formation reaction between the microcrystalline silicon thin film and metal thin film, thereby preventing peeling of the thin film. In a polycrystalline silicon TFT (Thin Film Transistor) using the layer-stacked wiring, the microcrystalline silicon thin film is so configured that its crystal grains each having a length of the microcrystalline silicon thin film in a direction of a film thickness being 60% or more of a film thickness of the microcrystalline silicon thin film amount to 15% or less of total number of crystal grains or that its crystal grains each having a length of the microcrystalline silicon thin film in a direction of a film thickness being 50% or less of a film thickness of the microcrystalline silicon thin film amount to 85% or more of the total number of crystal grains making up the microcrystalline silicon thin film.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, advantages, and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a cross-sectional view of a semiconductor device using a layer-stacked wiring according to a first embodiment of the present invention;

FIGS. 2A, 2B and 2C are process diagrams illustrating, in order of processes, a manufacturing method of a semiconductor device according to a second embodiment of the present invention;

FIGS. 3D, 3E and 3F are also process diagrams illustrating, in order of processes, a manufacturing method of a semiconductor device according to the second embodiment of the present invention;

FIGS. 4G and 4H are also process diagrams illustrating, in order of processes, a manufacturing method of a semiconductor device according to the second embodiment of the present invention;

FIG. 5 is a diagram explaining principles of the present invention and is a photo of a cross section of a crystal structure of a microcrystalline silicon thin film in which no peeling of the thin film occurred even after heat treatment process;

FIG. 6 is also a diagram explaining principles of the present invention and is another photo of a cross section of a crystal structure of a microcrystalline silicon thin film in which peeling of the thin film occurred after heat treatment process;

FIG. 7 is a diagram explaining a definition of a length of a crystal grain making up a crystal structure of the microcrystalline silicon thin film;

FIG. 8 is a diagram explaining principles of the present invention and is a cumulative frequency distribution table showing a relation between cumulative frequency distribution (ordinate) and length of a crystal grain of a microcrystalline silicon thin film/thickness of the microcrystalline silicon thin film (abscissa);

FIG. 9 is also a diagram explaining principles of the present invention and is a cumulative frequency distribution table showing a relation between cumulative frequency distribution (ordinate) and length of a crystal grain of a microcrystalline silicon thin film/thickness of the microcrystalline silicon thin film (abscissa);

FIG. 10 is also a diagram explaining principles of the present invention and shows a relation of correspondence between a deposition condition for a microcrystalline silicon thin film and peeling of the thin film; and

FIG. 11 is a cross-sectional view showing a semiconductor device using the conventional layer-stacked wiring.

Claims

1. A layer-stacked wiring comprising: a microcrystalline silicon thin film; anda metal thin film formed on said microcrystalline silicon thin film,wherein crystal grains making up a crystal structure of said microcrystalline silicon thin film, each having a length of said microcrystalline silicon thin film in a direction of a film thickness being 60% or more of a film thickness of said microcrystalline silicon thin film amount to 15% or less of total number of said crystal grains.

2. A layer-stacked wiring comprising: a microcrystalline silicon thin film; anda metal thin film formed on said microcrystalline silicon thin film,wherein crystal grains making up a crystal structure of said microcrystalline silicon thin film, each having a length of said microcrystalline silicon thin film in a direction of a film thickness being 50% or less of a film thickness of said microcrystalline silicon thin film amount to 85% or more of the total number of crystal grains.

3. A method for manufacturing a layer-stacked wiring comprising a microcrystalline silicon thin film and a metal thin film formed on said microcrystalline silicon thin film, said method comprising: a microcrystalline silicon thin film forming process to form a portion corresponding to a desired film thickness of said microcrystalline silicon thin film on an insulating substrate at a deposition rate that does not degrade, at least, quality of a thin film of said microcrystalline silicon thin film;a metal thin film forming process to form said metal thin film on said microcrystalline silicon thin film; anda heat treatment process to perform heat treatment on said insulating substrate formed on said microcrystalline silicon thin film and said metal thin film.

4. The method for manufacturing the layer-stacked wiring according to claim 3, wherein, in said microcrystalline silicon thin film forming process, a portion corresponding to a desired film thickness of said microcrystalline silicon thin film at a deposition rate combined with a deposition rate that degrades quality of a thin film of said microcrystalline silicon thin film.

5. The method for manufacturing the layer-stacked wiring according to claim 4, wherein, in said microcrystalline silicon thin film forming process, a portion corresponding to at least 20% of a film thickness of said microcrystalline silicon thin film is formed at a deposition rate that does not degrade quality of said thin film.

6. The method for manufacturing the layer-stacked wiring according to claim 3, wherein said deposition rate that does not degrade quality of said thin film is 13 nm/min.

7. The method for manufacturing the layer-stacked wiring according to claim 3, wherein said heat treatment process comprises an activating process to perform heat treatment on an impurity implanted in advance and a hydrogenating process to perform heat treatment in an atmosphere of nitrogen.

8. The method for manufacturing the layer-stacked wiring according to claim 7, wherein said activating process is performed at 400° C. or more and for four hours or less.

9. The method for manufacturing a layer-stacked wiring according to claim 8, wherein said hydrogenating process is performed at 350° C. or more and for 30 minutes or less.

10. A semiconductor device comprising: a polycrystalline silicon thin film having a source region and a drain region at its both ends, which is formed on an insulating substrate with a front-end insulating film interposed between said polycrystalline silicon thin film and said insulating substrate; anda gate electrode formed on said polycrystalline silicon thin film with a gate insulating film interposed between said gate electrode and said polycrystalline silicon thin film, wherein said gate electrode comprises a layer-stacked wiring comprising: a microcrystalline silicon thin film; anda metal thin film formed on said microcrystalline silicon thin film,wherein crystal grains making up a crystal structure of said microcrystalline silicon thin film, each having a length of said microcrystalline silicon thin film in a direction of a film thickness being 60% or more of a film thickness of said microcrystalline silicon thin film amount to 15% or less of total number of said crystal grains.

11. A semiconductor device comprising: a polycrystalline silicon thin film having a source region and a drain region at its both ends, which is formed on an insulating substrate with a front-end insulating film interposed between said polycrystalline silicon thin film and said insulating substrate; anda gate electrode formed on said polycrystalline silicon thin film with a gate insulating film interposed between said gate electrode and said polycrystalline silicon thin film, wherein said gate electrode comprises a layer-stacked wiring comprising: a microcrystalline silicon thin film; anda metal thin film formed on said microcrystalline silicon thin film,wherein crystal grains making up a crystal structure of said microcrystalline silicon thin film, each having a length of said microcrystalline silicon thin film in a direction of a film thickness being 50% or less of a film thickness of said microcrystalline silicon thin film amount to 85% or more of the total number of crystal grains.

12. A method for manufacturing a semiconductor device comprising: a process of forming an amorphous silicon thin film on an insulating substrate with a front-end insulating film interposed between said amorphous silicon thin film and said insulating substrate;a process of crystallizing said amorphous silicon thin film to form a polycrystalline silicon thin film by performing a laser annealing process on said amorphous silicon thin film;a process of forming, after making said polycrystalline silicon thin film have an island structure, a layer-stacked film comprising a microcrystalline silicon thin film and a metal thin film which are stacked sequentially on a gate insulating film; anda process of performing patterning on said layer-stacked film to form a gate electrode having a desired shape;wherein, as said microcrystalline silicon thin film, a thin film is used whose crystal grains, each having a length of said microcrystalline silicon thin film in a direction of a film thickness being 60% or more of a film thickness of said thin film amount to 15% or less of total number of crystal grains making up said thin film or whose crystal grains, each having a length of said thin film in a direction of a film thickness being 50% or less of a film thickness of said thin film amount to 85% or more of the total number of crystal grains making up said thin film.