Patent Application
20110016445
This application is based upon and claims the benefit of priority from Japanese patent application No. 2009-167808, filed on Jul. 16, 2009, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a layout design system, in particular, a layout design system related to arrangement of dummy metal in design for manufacturability (DFM) of a semiconductor integrated circuit.
2. Description of Related Art
Since multi wiring layers are realized due to the advancement of microfabrication technique, a planarization is carried out in semiconductor manufacturing by using a polishing technique (CMP: Chemical Mechanical Polishing). When there is unevenness in distribution of metal wirings, mottles are generated in CMP and planarization cannot be achieved. Therefore, in a layout design method to satisfy a design for manufacturability of a semiconductor integrated circuit, dummy metals are required to be filled such that distribution density of metal wirings is a predetermined value or more in any position.
In recent years, in the design of semiconductor integrated circuit, since a circuit scale increases with the advancement of microfabrication, amount of dummy metal to be provided increases. For example, in a layout design in which a layout tool is used, the layout tool inputs layout data such as net list of circuits and coordinates at which the circuits are arranged (arrangement coordinates), processes the layout data, and outputs the processed layout data. Since arrangement coordinates of dummy metals are described in the layout data, as the number of dummy metals increases, the size of the layout data increases.
In
A wiring layout design method according to the general technique will be described below referring to
In the arrangement of dummy metal at Step S15, distribution density of metal wiring is checked, dummy metal is arranged in an area in which the distribution density of metal wiring is less than a prescribed value such that the pitch between the arranging dummy metal and an existing wiring coincides with a predetermined minimum wiring pitch, and thereby the prescribed value is satisfied. As shown in
Referring to
As related art, Japanese patent publication (JP-A-Heisei 5-258017) discloses a semiconductor integrated circuit device and a wiring layout method for the semiconductor integrated circuit device. According to the related art, actual wiring is formed to connect between elements formed in the semiconductor integrated circuit, and a grid-like dummy wiring with a minimum wiring pitch is formed in the same wiring layer of the actual wiring in the whole region of the semiconductor integrated circuit device such that the grid-like dummy wiring is separated from the actual wiring by the minimum wiring pitch and is not connected to any of actual wiring, element and terminal.
The present inventor has recognized as follows.
As described above, in recent LSI (Large Scale Integration) manufacturing, with the advancement of miniaturization of LSI, an integration density has increased and a gate scale has increased. This causes increase in data size required to fill dummy metal. The increase in the data size leads to a problem that an expensive computer having high throughputs and a large amount of memory needs to be used as a processing machine for wiring correction and the like.
The reason is considered as follows. According to the general technique, in order to fill dummy metal, in the arrangement of the dummy metal, the actual wiring layout data is generated based on circuit data of a semiconductor integrated circuit device and the grid-like dummy wiring layout data 7a with the minimum wiring pitch is generated over the whole region of the semiconductor integrated circuit device which is determined by the actual wiring layout data.
Consequently, it is impossible to specify a common location (coordinate) at which the dummy metal is arranged based on the different actual wiring layout data for each layout process and generate a new layout cell in which the dummy metal is arranged in advance at the specified arrangement location. Further, the layout data of the dummy metal is arranged by describing arrangement information for each dummy wiring layout data 7a. Furthermore, the amount of description of the layout data increases with an increase in the data size of the filled dummy metal. In addition, high throughputs and a large amount of memory are required to process the layout data.
In one embodiment, a layout design system includes: a first unit which selects a layout cell based on layout design and usage rate in a semiconductor integrated circuit, specifies a common coordinate at which dummy metal is arranged for the selected layout cell, and generates a new layout cell in which dummy metal is arranged in advance at the specified coordinate; and a second unit which uses the new layout cell in place of the selected layout cell.
In another embodiment, a layout design method of a semiconductor integrated circuit comprising: generating a new layout cell in which dummy metal is arranged in advance at a specified coordinate; and using the new layout cell in place of a selected layout cell. The generating the new layout cell includes: selecting a layout cell as the selected layout cell based on layout design and usage rate; and specifies a common coordinate as the specified coordinate at which dummy metal is arranged for the selected layout cell.
According to the layout design system and the layout design method, design can be carried out by using an inexpensive computer having low throughputs and a small amount of memory. Process such as wiring correction in which the amount of data depends on processing speed can be carried out by use of the inexpensive computer having low throughputs and the small amount of memory.
The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which:
The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes.
A first embodiment of the present invention will be described below referring to the attached drawings.
A layout design method according to the present embodiment can be carried out by a layout design system using a computer.
As shown in
The design tool 11 includes a design program. The input data 12 is inputted to the design tool 11. The output data 13 is outputted from the design tool. The cell library 14 is referred to by the design tool 11. The correspondence list 15 is referred to by the design tool 11. Here, the design tool 11 refers to the cell library 14 and the correspondence list 15 and generates the output data 13 from the input data 12.
An example of the computer that can serve as the layout design system 10 includes a PC (personal computer), thin client terminal/server, a work station, a mainframe computer and a supercomputer. The layout design system 10 is not limited to the computer itself but may be relay equipment, peripheral equipment, an expansion board mounted to a computer, virtual machine (VM) environment built on a computer or the like. However, in fact, the layout design system 10 is not limited to these examples.
An example of hardware that implements the design tool 11 includes: a processor such as a CPU (Central Processing Units), and a microprocessor; or a semiconductor integrated circuit (IC) having the same function as that of the processor. That is, the design tool 11 is implemented by hardware such as CPU which is driven based on a program and software based on which the hardware is driven to perform desired processes. However, in fact, the design tool is not limited to these examples.
An example of hardware for inputting the input data 12 includes: an interface (I/F) for acquiring information from an external input device or storage device; a driving device for reading and writing data from and to storage media; a network adaptor such as NIC (Network Interface Cards); an antenna; and a communication port. An example of the input device includes a keyboard, a keypad, a keypad on screen, a touch panel and a tablet. However, in fact, the hardware for inputting the input data 12 is not limited to these examples.
An example of hardware for outputting the output data 13 includes: an interface for outputting information to an external display device or storage device; a driving device for reading and writing data from and to the storage media; a network adaptor such as NIC; an antenna; and a communication port. An example of the display device includes an LCD (Liquid Crystal Display), a PDP (Plasma Display Panel), an organic EL display (organic electroluminescence display) and a printer for printing outputted contents on paper or the like. However, in fact, the hardware for outputting the output data 13 is not limited to these examples.
An example of storage means for folding the software for the design tool 11, the input data 12, the output data 13, the cell library 14 and the correspondence list 15 includes: a semiconductor storage device such as an EEPROM (Electrically Erasable and Programmable Read Only Memory) and a flash memory; an auxiliary storage device such as a hard disk and an SSD (Solid State Drive); and storage media such as a DVD (Digital Versatile Disk) and a memory card. The storage means is not limited to a storage device installed in a main unit of a computer but may be a peripheral device (external HDD or the like), a storage device installed in an external server (storage server or the like) or NAS (Network Attached Storage). However, in fact, the storage means is not limited to these examples.
An operation according to the first embodiment of the present invention will be described, for example, in the case that a logical circuit shown in
Instances a1 to a15 in the logical circuit in
The instances a1 to a12 includes CELL1s which are buffers performing the same logical operation (function) and cells of cell type having large driving ability, and have individual names a1 to a12.
The instances a13 and a14 includes CELL2s which are buffers performing the same logical operation (function) as that of the CELL1 and cells of cell type having driving ability smaller than that of the CELL1.
The instance a15 includes CELL3 which is a buffer performing a logical operation (function) of AND different from those of CELL1 and CELL2 and a cell of cell type having the same driving ability as that of the CELL1. Inputs of the instances a1 to a3 and a5 to a15 are connected to an output of the instance a4.
An outline of the first embodiment of the present invention will be described referring to a flowchart in
First, the design tool 11 performs floor plan arrangement of 10 terminals (input/output terminals) and macros.
Next, the design tool 11 performs a power source wiring.
Next, the design tool 11 arranges respective layout cells.
Next, the design tool 11 performs a signal wiring.
Next, the design tool 11 specifies locations at which dummy metals are arranged, newly generates a layout cell in which dummy metals are arranged in advance at the specified locations, and adds the layout cell to the cell library. Details of a method of generating the new layout cell will be described later.
Next, the design tool 11 replaces the layout cell of the instance having the locations at which dummy metals are arranged by the generated new layout cell having dummy metals.
Next, the design tool 11 judges whether or not metal usage rate after the replacement using the new layout cell satisfies a metal standard of the whole of one chip. When the metal usage rate after the replacement does not satisfy the metal standard of the whole of one chip, the design tool 11 is shifted to the new layout cell generation process (Step S105) again. When being shifted to the new layout cell generation process (Step S105) again, the design tool 11 first eliminates the instance in which the dummy metals are arranged at execution of the process at Step S106 from data of Step S106 and then, executes the processes of Step S105 and the following steps. When the metal usage rate after the replacement satisfies the metal standard of the whole of one chip, the design tool 11 terminates the flow.
Although not shown, the design tool 11 includes function units for executing the processes of Steps S101 to S107. Here, the design tool 11 includes a floor plan process unit (Step S101), a power source wiring process unit (Step S102), an arrangement process unit (Step S103), a wiring process unit (Step S104), a dummy metal-arranged layout cell generation process unit (Step S105), a dummy metal-arranged layout cell replacement process unit (Step S106) and a metal usage rate judgment process unit (Step S107). It should be noted that although these units are conceptually separated from each other, these units may be integrated physically in arbitrary combination.
Next, a procedure for generating the new layout cell at Step S105 will be described referring to
In the method of generating the new layout cell, in order to commonly and efficiently arrange dummy metals in cells of the same cell type in the target layout, wiring data on the instances are summarized, common locations (coordinates) are specified at which dummy metals are arranged, and a common pattern is obtained. By again summarizing the wiring data for the layout data from which instances recognized as the common pattern are eliminated, a common pattern is repeatedly obtained to generate a layout cell in which one or more dummy metals are arranged.
With respect to the instances a1 to a12 in the logical circuit shown in
With respect to the instances a13 and a14 in the logical circuit shown in
With respect to the instance a15 in the logical circuit shown in
In
The design tool 11 classifies all instances in the layout data according to cell types, and for each cell type, calculates the number of cells and layout area of a cell to obtain the layout total area as the product of the number of cells and the layout area of the cell. At this time, the design tool 11 obtains the number of cells, the area, and the total area for each cell type used in the circuit diagram shown in
The design tool 11 selects CELL1 as the cell type having the largest total area of layout cell, which is obtained at Step S201.
The design tool 11 generates a wiring database for the instances using CELL1 selected at Step S202.
The design tool 11 summarizes values in the wiring database that are generated at Step S203. In
For each of the coordinate names 1A to 2R of the wiring tracks, a sum total of numbers of wirings of the instances a1 to a12 for a coordinate name of the wiring tracks is calculated as a coordinate total. Namely, for each of the coordinate names 1A to 2R, a sum total in a column is calculated as the coordinate total.
In the present embodiment, the first layer total of the instance a1 is “6” as the total of “1A=1, 1B=1, 1C=1, 1D=1, 1E=1, 1F=0, 1G=0, 1H=0, 1I=0, 1J=0, 1K=0, 1L=0, 1M=0, 1N=0, 1O=0, 1P=0, 1Q=0, and 1R=1”.
In the present embodiment, the coordinate total of the coordinate name 1A is “4” as the total of “instance a1=1, instance a2=0, instance a3=0, instance a4=1, instance a5=1, instance a6=0, instance a7=0, instance a8=0, instance a9=0, instance a10=0, instance a11=1, and instance a12=0”.
According to the above-mentioned totals, numbers of wirings which exist at the coordinates on the plurality of instances are obtained. Furthermore, when a dummy metal is arranged on a coordinate, the dummy metal can be arranged in an instance in which there is no wiring at the coordinate since a wiring and the dummy metal do not overlap each other. When the value of the coordinate total is small, many dummy metals can be arranged on the coordinates in the whole layout.
The total number of coordinates at which dummy metals are arranged are calculated as a number of intersections (coordinates) of the wiring tracks, and a specific calculation method will be described in the description of Step S207.
The design tool 11 selects an instance having a minimum number of the coordinate totals obtained at Step S204. When there are a plurality of coordinates having the minimum number, an instance having a maximum number of the wiring layer total is selected among the selected plurality of instances. In other words, an instance that uses the corresponding wiring layer most in the layout cell having the maximum number of coordinates without wiring is selected.
For example, in the case of
The design tool 11 regenerates the wiring database in which the instance a7 selected at Step S205 is eliminated. In the regenerated wiring database, the coordinate totals for the coordinates 1H and 1I which are used by the selected instance a7 for wiring are “0”.
The design tool 11 calculates a number of intersections (coordinates) of the wiring tracks in the wiring database generated at Step S206. The number of intersections (coordinates) of the wiring tracks is a value obtained by calculating a number of coordinates having the coordinate total of “0” and multiplying the number of coordinates by a number of remaining instances other than the instance eliminated at Step S206. For example, in
The design tool 11 repeats the processes of Steps S205 to S207 for n times (n is two or more integer) by using the wiring database generated again at Step S206 to obtain an optimum common pattern.
The processes of Steps S205 to S207 are repeated for n of more than two.
In
When the metal number obtained at the n-th Step S207 is equal to or smaller than that obtained at the n−1-th Step S207, the wiring database of n−1-th time is judged to be the optimum common pattern and retrieval of the common pattern is finished.
In the present embodiment, as shown in
As shown in
The metal number is eighty four in the case of n=8 and ninety in the case of n=7. Thus, since the metal number in the case of n=7 is larger than that in the case of n=8, the wiring database at n=7 is judged as the optimum common pattern. Since the metal number in the database of n-th time is the total number of the cell coordinates at which dummy metals can be arranged in layout, the wiring pattern having the maximum metal number when the metal number increases from n−1-th time to n-th time and decreases from n-th time to n+1-th time is obtained as the optimum common pattern.
The design tool 11 generates a cell in which dummy metals are arranged based on the optimum common pattern obtained at Step S208.
Although not shown, the design tool 11 includes function units for executing the processes of Steps S201 to S209. Here, the design tool 11 includes, as components of the dummy metal-arranged layout cell generation process unit (Step S105), a cell information summarization process unit (Step S201), a layout cell selection process unit (Step S202), a wiring data conversion process unit (Step S203), a wiring data summarization process unit (Step S204), a non-common pattern retrieval process unit (Step S205), a non-common pattern elimination process unit (Step S206), an arranged dummy metal number calculation process unit (Step S207), an arranged dummy metal number judgment process unit (Step S208) and a new layout cell generation process unit (Step S209). It should be noted that although these units are conceptually separated from each other, these units may be integrated physically in arbitrary combination.
For example,
Dummy metals are arranged at locations in
Similarly,
According to the above-mentioned procedure, locations at which dummy metals of the respective layer are arranged are specified, a cell is newly generated in which dummy metals are arranged in advance at the locations, and the cell is added to the cell library. The newly generated cell is referred to as “new layout cell”.
The design tool 11 executes the new layout cell replacement process at Step S106 by replacing a cell name in a layout cell arrangement coordinate description H603 in
Cell replacement in layout will be described referring to
As shown in
Replacement between the original layout cell and the new layout cell is achieved by executing the replacement of cell name in the layout cell arrangement coordinate description H603, namely by replacing CELL1 in the layout cell arrangement coordinate description H903 by CELL1_METAL1 in the layout cell arrangement coordinate description H603.
A dummy metal description H602 describes arrangement coordinates of dummy metals and indicates an end of description of an arrangement coordinate of one layout cell by a semicolon.
The layout cell arrangement coordinate description H603 describes the arrangement coordinates of the layout cells and indicates an end of description of an arrangement coordinate of one layout cell by a semicolon.
The definition of new layout cell is described as CELL1_METAL1 in the layout cell definition H601. When all dummy metals are arranged by using the new layout cells in the process according to the present embodiment, the dummy metal description H602 does not describe any dummy metal.
According to the present embodiment, a common location (coordinate) at which dummy metal is arranged is specified from the frequently-used layout cell, the new layout cell in which the dummy metal is arranged in advance at the specified arrangement location is generated, and the dummy metal is arranged by replacing the frequently-used layout cell from which the new layout cell is generated by the new layout cell having dummy metal.
According to the present embodiment, since the description of the arrangement coordinates of the dummy metals in the layout data can be described as the arrangement coordinates of cells by defining the new layout cells, data size required to describe the arrangement coordinates of the dummy metals in the layout data can be reduced.
As described above, an advantage is provided that an expensive computer having high throughputs and a large amount of memory does not required to be used for a process such as wiring correction in which data size depends on processing speed.
A mechanism for solving the above-mentioned problem will be described. According to the conventional art, in order to fill dummy metal, in the dummy metal arrangement at Step S104, the dummy wiring layout data 7a is arranged by describing arrangement coordinate in a layer for each dummy wiring layout data 7a. Therefore, description amount of the layout data increases depending on the data size of the filled dummy metal.
However, according to the present embodiment, in Steps S105 to 107, the description of the arrangement coordinates of the dummy metals in the layout data can be described as the arrangement coordinates of cells by defining the new layout cells. Therefore, data size required to describe the arrangement coordinates of the dummy metals in the layout data can be reduced.
A specific data size will be described referring to
The layout cell definition H601 defines the layout cells. The new layout cell generated according to the present embodiment is added to the layout cell definition H601.
In the first embodiment of the present invention, CELL1_METAL1 as a cell of the cell type is defined and rectangular information of the dummy metal is described in the definition.
The dummy metal description H602 describes the arrangement coordinates of the dummy metals. When all dummy metals are arranged by using the new layout cells in the process according to the present embodiment, the dummy metal description H602 does not describe any dummy metal.
The layout cell arrangement coordinate description H603 describes the arrangement coordinates of the layout cells and describes the cell names and coordinates of the arranged layout cells.
According to the present embodiment, CELL1_METAL1 is generated and used as the new layout cell having two dummy metals.
The definition of the new layout cell having description of rectangles of two dummy metals is added to the layout cell definition H601. In the layout cell arrangement coordinate description H603, the dummy metals are arranged by replacing the layout cell from which the new layout cell is generated by the added new layout cell and by using the new layout cell.
As described above, since the dummy metals can be arranged by generating the new layout cell which describes rectangular information of the dummy metals and by replacing the layout cell name as in the case of the layout cell arrangement coordinate description H603, all of the six dummy metals are arranged. Therefore, the dummy metal description H602 includes no arranged data.
On the contrary, in the layout carried out according to the conventional procedure, the dummy metals are arranged by describing arrangement information for every dummy wiring layout data. Therefore, for example, rectangles of all of the six dummy metals are required to be described to express the dummy metals in the layout in
As described above, by describing and using the dummy metals in the layout cell, the description of the arrangement coordinates of the dummy metals can be described as the arrangement coordinates of cells by defining the new layout cells. Therefore, data size required to describe the arrangement coordinates of the dummy metals in the layout data can be reduced.
Also when the above-mentioned layout data is used in the tool, the rectangular data can be expanded by describing the description of the arrangement coordinates of the dummy metals as the arrangement coordinates of cells by defining the new layout cells. Therefore, the rectangular data can be shared also in the tool. Consequently, data size required to describe the arrangement coordinates of the dummy metals can be reduced.
A second embodiment of the present invention will be described below.
Differences between the flow of
In the flow of generating the new layout cell, the area of the layout as a target of process can be the whole chip as illustrated in the flow of
An outline of the second embodiment of the present invention will be described using the flow of
First, the design tool 11 performs floor plan arrangement of IO terminals and macros.
Next, the design tool 11 performs a power source wiring.
Next, the design tool 11 arranges respective layout cells.
Next, the design tool 11 performs a signal wiring.
Steps S301 to S304 in the second embodiment of the present invention are the same as Steps S101 to S104 in the first embodiment.
Next, the design tool 11 divides the layout as target into areas and processes each divided area.
Step S305 is an area division process. In the process, an arbitrary area such as an area in which metal usage rate is low is cut off from the layout data to be delivered to Step S306. By performing the area division process, the number of instances in the circuit, from which a common pattern is sought, is reduced. Therefore, a common pattern specific to the area can be obtained.
Next, the design tool 11 specifies locations at which dummy metals are arranged, newly generates a layout cell in which dummy metals are arranged in advance at the specified locations, and adds the layout cell to the cell library.
Next, the design tool 11 replaces the layout cell of the instance having the locations at which the dummy metals are arranged by the generated new layout cell having dummy metals.
Next, the design tool 11 judges whether or not metal usage rate after replacement using the new layout cell satisfies a metal standard of the whole of one chip. When the metal usage rate after replacement does not satisfy the metal standard of the whole of one chip, the design tool 11 is shifted to the new layout cell generation process (Step S306) again. When the metal usage rate after replacement satisfies the metal standard of the whole of one chip, the design tool 11 is shifted to an area judgment process (Step S309).
Steps S306 to S308 in the second embodiment of the present invention are the same as Steps S105 to S107 in the first embodiment.
Next, the design tool 11 checks whether all pieces of the layout data divided in Step S305 are processed. When there is unprocessed piece of the layout data, the design tool 11 is shifted to the new layout cell generation process (Step S306) again. When the all pieces of the layout data are processed, the design tool 11 terminates the flow.
Although not shown, the design tool 11 includes function units for executing the processes of Steps S301 to S309. Here, the design tool 11 includes a floor plan process unit (Step S301), a power source wiring process unit (Step S302), an arrangement process unit (Step S303), a wiring process unit (Step S304), an area division process unit (Step S305), a dummy metal-arranged layout cell generation process unit (Step S306), a dummy metal-arranged layout cell replacement process unit (Step S307), a metal usage rate judgment process unit (Step S308) and an area judgment process unit (Step S309). It should be noted that although these units are conceptually separated from each other, these units may be integrated physically in arbitrary combination.
In the second embodiment of the present invention, the number of instances as targets is reduced by dividing the layout into areas. Therefore, a common pattern specific to the area can be obtained and the new layout cell in which a larger number of dummy metals are arranged can be generated. As described above, the metal usage rate can be increased.
A third embodiment of the present invention will be described.
With respect to differences between the flow of
The arrangement of dummy metal is executed for all the wiring layers at the same time in the flow of
With respect to differences between the flow of
Therefore, in specifying common locations (coordinates) at which dummy metals are arranged, for example, even when there exist an instance in which dummy metals can be arranged in the first layer but cannot be arranged in the second layer, or even when there exist an instance in which dummy metals cannot be arranged in the first layer but can be arranged in the second layer, dummy metals can be arranged in each wiring layer.
An outline of the third embodiment of the present invention will be described referring to the flow of
First, the design tool 11 performs floor plan arrangement of IO terminals and macros.
Next, the design tool 11 performs a power source wiring.
Next, the design tool 11 arranges respective layout cells.
Next, the design tool 11 performs a signal wiring.
Steps S401 to S404 in the third embodiment are the same as Steps S101 to S104 in first embodiment.
Next, the design tool 11 specifies, with respect to an m-th layer (m is an integer of one to a integer corresponding to a topmost wiring layer), locations at which dummy metals are arranged, newly generates a layout cell in which dummy metals are arranged in advance at the specified locations, and adds the layout cell to the cell library.
Next, the design tool 11 replaces the layout cell of the instance having the locations at which dummy metals are arranged with the generated new layout cell having dummy metals.
The design tool 11 checks the metal usage rate. When the metal usage rate does not reach a target, the design tool 11 is shifted to a new layout cell generation process (Step S405) again with respect to only the area in which dummy metal is not arranged. When the metal usage rate reaches the target, the design tool 11 is shifted to a wiring layer check process (Step S408).
The design tool 11 executes the wiring layer check process. When the m-th layer is not the topmost wiring layer, the design tool 11 increments m by one and is shifted to the new layout cell generation process (Step S405) again. When the m-th layer is the topmost wiring layer, the design tool 11 terminates this flow.
Although not shown, the design tool 11 includes function units for executing the processes of Steps S401 to S408. Here, the design tool 11 includes a floor plan process unit (Step S401), a power source wiring process unit (Step S402), an arrangement process unit (Step S403), a wiring process unit (Step S404), a dummy metal-arranged layout cell generation process unit (Step S405), a dummy metal-arranged layout cell replacement process unit (Step S406), a metal usage rate judgment process unit (Step S407) and a wiring layer check process unit (Step S408). It should be noted that although these units are conceptually separated from each other, these units may be integrated physically in arbitrary combination.
The design tool 11 classifies all instances in the layout data according to cell type, and for each cell type, calculates the number of cells and layout area of a cell to obtain the layout total area as the product of the number of cells and the layout area of the cell. In this manner, at Step S501, like Step S201 in the first embodiment, the cell information summarization process is executed.
The design tool 11 selects CELL1 as the cell type having the largest total area of layout cell, which is obtained at Step s501. In this manner, at Step S502, like Step S202 in the first embodiment, the layout cell selection process is executed.
The design tool 11 generates a wiring database for the instances using CELL1 selected at Step S502. At Step S503, the generation of wiring database for all the wiring layers as described as Step S203 in the first embodiment is not executed, and the generation of wiring database for only m-th layer (m is an integer of one to the integer corresponding the topmost wiring layer) is executed.
The design tool 11 summarizes values in the wiring database that are generated at Step S503. In this manner, at Step 504, like Step S204 in the first embodiment, the wiring data conversion process is executed.
The design tool 11 selects an instance having a minimum number of the coordinate totals obtained at Step S504. When there are a plurality of coordinates having the minimum number, an instance having a maximum number of the wiring layer total is selected among the selected plurality of instances. In other words, an instance that uses the corresponding wiring layer most in the layout cell having the maximum number of coordinates without wiring is selected.
Like Step S206 in the first embodiment, the design tool 11 regenerates the wiring database in which the instance a7 selected at Step S505 is eliminated.
Like Step S207 in the first embodiment, the design tool 11 calculates a number of intersections (coordinates) of the wiring tracks in the wiring database generated at Step S506. The number of intersections (coordinates) of the wiring tracks is a value obtained by calculating a number of coordinates having the coordinate total of “0” and multiplying the number of coordinates by the number of remaining instances other than the instance eliminated at Step S506.
The design tool 11 repeats the processes of Steps S505 to S507 for n times (n is two or more integer) using the wiring database generated again at Step S506 to judge an optimum common pattern, as described in the first embodiment.
The design tool 11 generates a cell in which dummy metals are arranged based on the optimum common pattern obtained at Step S508. Although the dummy metals are arranged in the selected layout cell in the first embodiment, in the new layout cell generation process of Step S509, the new layout cell generated in the third embodiment is METAL1 as a cell of cell type having only information of dummy metals in the m-th wiring layer.
Although not shown, the design tool 11 includes function units for executing the processes of Steps S501 to S509. Here, the design tool 11 includes, as components of the dummy metal-arranged layout cell generation process unit (Step S405), a cell information summarization process unit (Step S501), a layout cell selection process unit (Step S502), a wiring data conversion process unit (Step S503), a wiring data summarization process unit (Step S504), a non-common pattern retrieval process unit (Step S505), a non-common pattern elimination process unit (Step S506), an arranged dummy metal number calculation process unit (Step S507), an arranged dummy metal number judgment process unit (Step S508) and a new layout cell generation process unit (Step S509). It should be noted that although these units are conceptually separated from each other, these units may be integrated physically in arbitrary combination.
In the third embodiment of the present invention, in the new layout cell replacement process at Step S406, the design tool 11 arranges dummy metals by arranging METAL1 as the cell of the cell type so as to overlap the coordinate of the layout cell of the instance selected at Step S505, from which METAL1 is generated.
A layout cell definition H701 defines layout cells and indicates an end of definition of one layout cell by a semicolon,
A dummy metal description H702 describes arrangement coordinates of dummy metals and indicates an end of description of an arrangement coordinate of one layout cell by a semicolon.
A layout cell arrangement coordinate description H703 describes the arrangement coordinates of the layout cells and indicates an end of description of an arrangement coordinate of one layout cell by a semicolon.
In the layout cell arrangement coordinate description H703, METAL1 having only the dummy metal information is arranged along with the description of the coordinate of the layout cell of the instance selected at Step S205, from which METAL1 is generated. In the present embodiment, by describing METAL1 as the new layout cell having only dummy metals and CELL 1 side by side in the layout cell arrangement coordinate description H703 in
In the third embodiment, by executing the dummy metal arrangement for each wiring layer, even when the common locations (coordinates) at which dummy metals are arranged are specified, the new layout cell in which many dummy metals are arranged can be generated.
For example, even when there exist an instance in which dummy metals can be arranged in the first layer but cannot be arranged in the second layer, or even when there exist an instance in which dummy metals cannot be arranged in the first layer but can be arranged in the second layer, the dummy metal arrangement can be executed for each wiring layer. Therefore, the new layout cell in which many dummy metals are arranged can be generated. Furthermore, as described above, the metal usage rate can be increased.
According to the embodiment, as a first procedure, a common location (coordinate) at which dummy metal is arranged is specified from a frequently-used layout cell, a new layout cell in which dummy metal is arranged is generated, and dummy metal is arranged by replacing the layout cell from which the new layout cell is generated by the new layout cell having dummy metal.
According to the procedure, the description of the arrangement coordinates of the dummy metals in the layout data can be described as the arrangement coordinates of cells by defining the new layout cells and data size required to describe the arrangement coordinates of the dummy metals in the layout data can be reduced. Therefore, a process such as wiring correction in which data size depends on processing speed can be carried out by using an inexpensive computer having low throughputs and the small amount of memory.
Furthermore, by using a machine having throughputs and amount of memory required for the conventional method, the process can be carried out in a shorter process time.
According to the embodiment, as a second procedure, the layout area is divided to arrange dummy metals.
According to the procedure, since the number of instances as targets is reduced, the new layout cell in which a larger number of dummy metals are arranged can be generated. As described above, the metal usage rate can be increased.
According to the embodiment, as a third procedure, the dummy metal arrangement is executed for each wiring layer.
According to the procedure, since the optimum common pattern is retrieved for each wiring layer, the new layout cell in which a larger number of dummy metals are arranged can be generated. Thus, the metal usage rate can be increased.
According to a layout design method according to the embodiment as a layout design method of semiconductor integrated circuit includes: a step of generating a new layout cell; and a step of arranging dummy metal. In the step of generating the new layout cell, a common location (coordinate) at which dummy metal is arranged is specified by selecting a frequently-used layout cell, and the new layout cell in which the dummy metal is arranged in advance at the specified arrangement location is generated. In the step of arranging the dummy metal, the dummy metal is arranged by replacing the frequently-used layout cell from which the new layout cell is generated by the new layout cell having dummy metal or by overlapping them.
The step of generating the new layout cell includes a layout cell information summarization process, a layout cell selection process, a wiring data conversion process, a wiring data summarization process, a non-common pattern retrieval process, a non-common pattern elimination process, an arranged dummy metal number calculation process, an arranged dummy metal number judgment process, and a new layout cell generation process.
The layout cell information summarization process includes a step of multiplying the use number of layout cell in a target circuit by the area of the layout cell.
The layout cell selection process includes a step of selecting layout cell having the largest value among values obtained in the layout cell information summarization process.
The wiring data conversion process includes a step of digitizing coordinates-on-tracks of an instance having the selected layout cell to 0 or 1, and a step of generating wiring database of the instance.
The wiring data summarization process includes a step of calculating a coordinate total for each coordinate on each track, a step of calculating a layer total of the instance for each wiring layer, and a step of calculating total number of metals.
The non-common pattern retrieval process includes a step of retrieving an instance to be eliminated based on the coordinate total and the layer total.
The non-common pattern elimination process includes a step of updating the generated database by eliminating the retrieved instance from the generated database.
The arranged dummy metal number calculation process includes a step of calculating the total number of dummy metals in the updated database.
The arranged dummy metal judgment process includes a step of judging whether or not the calculated total number of dummy metals is a maximum value to determine an optimum common pattern.
The new layout cell generation process includes a step of generating the new layout cell having dummy metal based on the determined optimum common pattern.
The step of generating new layout cell includes a step of dividing layout data into arbitrary areas, and a step of judging whether or not the new layout cell generation process and a new layout cell replacement process are executed for the divided areas.
The step of generating new layout cell includes a step of executing the new layout cell generation process for each wiring layer, and a step of judging whether or not the new layout cell generation process is executed for all wiring layers.
The above-mentioned embodiments can be implemented in combination.
The embodiments of the present invention have been specifically described. However, the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2009-167808 | Jul 2009 | JP | national |
