Patent Application
20240296271
This application claims the benefit of Taiwan application Serial No. 112107302, filed Mar. 1, 2023, the disclosure of which is incorporated by reference herein in its entirety.
The disclosure relates in general to a layout method, a non-transitory computer-readable medium, and an associated integrated circuit, and more particularly to a layout method, a non-transitory computer-readable medium, and an associated integrated circuit used for power gating.
Power saving is an important issue for mobile electronic products. Therefore, it is required that integrated circuits have dynamic power-saving functions. Integrated circuits usually include circuit blocks receiving different supply voltages or operating at different periods. One type of known power-saving operation of the integrated circuits is setting idle circuit blocks in a disabled mode MDoff with no power input to save power.
The switch sets sw_1˜sw_Q are selectively switched on or switched off in response to the corresponding block-enabling signals EN_1˜EN_Q sent by the voltage-switching circuit 11. For example, when the switch set sw_q is switched on in response to the block-enabling signal EN_q, the block voltage terminal bVdd_q of the circuit block BLK_q receives the supply voltage Vdd_q through the switch set sw_q. Similarly, the circuit blocks BLK_1˜BLK_Q receive the supply voltages Vdd_1˜Vdd_Q through the switch sets sw_1˜sw_Q, respectively. The voltage-switching circuit 11 uses the block-enabling signals EN_1˜EN_Q to selectively and dynamically activate the circuit blocks BLK_1˜BLK_Q or set the idle circuit blocks BLK_1˜BLK_Q in the disabled mode MDoff to save power.
For illustration purposes, it is assumed that the circuit block BLK_q is in the disabled mode MDoff and all other (Q−1) circuit blocks BLK_1˜BLK_(q−1), BLK_(q+1)˜BLK_Q are in the enabled mode MDon. Immediately after the circuit block BLK_q is switched from the disabled mode MDoff to the enabled mode MDon, the circuit block BLK_q receives a high inrush current from the supply voltage terminal Vdd_q. The other (Q−1) circuit blocks BLK_1˜BLK_(q−1), BLK_(q+1)˜BLK_Q in the enabled mode MDon may be disturbed by the inrush current flowing through the circuit block BLK_q so that IR drop occurs. Therefore, the switching operation of the supply voltage Vdd_q in the prior arts needed to be improved.
The disclosure is directed to a layout method, a non-transitory computer-readable medium, and an associated integrated circuit.
According to one embodiment, a layout method is provided. The integrated circuit includes Q circuit blocks. The layout method includes the following steps. Firstly, K gate-controlled elements and (K−1) buffers are placed on the edge of a qth circuit block among the Q circuit blocks. Each of the K gate-controlled elements includes a first terminal, a second terminal, and a control terminal, and each of the (K−1) buffers includes an input terminal and an output terminal. Then, the first terminals of the K gate-controlled elements are connected to a supply voltage terminal, and the second terminals of the K gate-controlled elements are connected to the qth circuit block. Among the K gate-controlled elements, (K−1) gate-controlled elements, including an SEL[1]-th gate-controlled element, are selected as (K−1) source nodes, wherein the control terminal of the SEL[1]-th gate-controlled element receives a qth enabling signal corresponding to the qth circuit block. Among the K gate-controlled elements, another (K−1) gate-controlled elements other than the SEL[1]-th gate-controlled element are selected as (K−1) destination nodes. The (K−1) buffers are respectively routed as the (K−1) delayed gating lines connected between the (K−1) source nodes and the (K−1) destination nodes. The variables Q, q, K, and SEL[1] are positive integers, SEL[1] is smaller than K, and q is smaller than or equivalent to Q.
According to another embodiment, a non-transitory computer-readable medium is provided. The non-transitory computer-readable medium records a software program for performing the above-described layout method on an integrated circuit.
According to a further embodiment, an integrated circuit is provided. The integrated circuit includes Q layout blocks corresponding to Q supply voltages respectively. A qth layout block among the Q layout blocks includes a qth circuit block, K gate-controlled elements, and (K−1) buffers. The qth circuit block operates with a qth supply voltage among the Q supply voltages. The K gate-controlled elements are placed on the edge of the qth circuit block. Each of the K gate-controlled elements includes a first terminal connected to a supply voltage terminal, a second terminal connected to the qth circuit block, and a control terminal. The control terminal of a SEL[1]-th gate-controlled element among the K gate-controlled elements receives a qth enabling signal corresponding to the qth circuit block. The (K−1) buffers are placed on the edge of the qth circuit block. Each of the (K−1) buffers includes an input terminal and an output terminal. Among the K gate-controlled elements, (K−1) gate-controlled elements, including the SEL[1]-th gate-controlled element, are selected as (K−1) source nodes, and another (K−1) gate-controlled elements other than the SEL[1]-th gate-controlled element are selected as (K−1) destination nodes. The (K−1) buffers are selected as (K−1) delayed gating lines between the (K−1) source nodes and the (K−1) destination nodes, respectively. The variables Q, q, K, and SEL[1] are positive integers, SEL[1] is smaller than K, and q is smaller than or equivalent to Q.
The advantages of the present disclosure will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings.
In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing.
As described above, when the integrated circuit in the prior arts switches the mode of the circuit block BLK_q, the high inrush current affects the voltages of other circuit blocks BLK_1˜BLK_(q−1) and BLK_(q+1)˜BLK_Q. Therefore, the disclosure proposes a specific layout of the gate-controlled elements of the circuit block BLK_q to eliminate the influence of the high inrush current on the peripheral-enabled circuit blocks BLK_1˜BLK_(q−1) and BLK_(q+1)˜BLK_Q.
The gate-controlled element in the disclosure generally refers to any element which is switched on or off by gate control. In the subsequent embodiments, the gate-controlled elements are implemented by NMOS transistors, which are switched on when the block-enabling signal EN_q is at the high logic level. However, the circuit behaviors of the gate-controlled elements p_1˜p_K in response to the logic level of the block-enabling signal EN_q are not limited to the embodiments in practical applications. In the disclosure, the drain terminal, the source terminal, and the gate terminal of the NMOS transistor are defined as the first terminal, the second terminal, and the control terminal of the gate-controlled element, respectively. The first terminals of the gate-controlled elements p_1˜p_K are all connected to the supply voltage Vdd_q, and the second terminals of the gate-controlled elements p_1˜p_K are all connected to the block voltage terminal bVdd_q of the circuit block BLK_q.
According to the layout method of the disclosure, (K−1) buffers are selected as (K−1) delayed gating lines between the K gate-controlled elements p_1˜p_K. In the disclosure, the variable “i” represents the numerical order (sequence number) of the delayed gating line, and the symbol buf[i] represents the buffer number, wherein i is a positive integer and i≤(K−1). The length of the ith delayed gating line (i=1˜(K−1)) may vary with the sequence number i. In a concise manner, the buffers in the delayed gating lines are not shown in the subsequent figures, and the delayed gating lines are presented with simple lines.
In the embodiments of the disclosure, a layout loop includes sequentially viewing the 1st˜Kth gate-controlled elements p_1˜p_K on the edge of the circuit block BLK_q and selecting some of the gate-controlled elements p_1˜p_K as source nodes src[i]/destination nodes dst[i] to route the delayed gating lines. Each layout loop usually routes Y delayed gating lines (Y<K). Therefore, the layout method of the disclosure needs several times of layout loops to route the (K−1)=91 delayed gating lines. According to the concepts of the disclosure, only one gate-controlled element is selected as the enablement input node p_enIN and directly receives the block-enabling signal EN_q with its control terminal, and other (K−1) gate-controlled elements do not directly receive the block-enabling signal EN_q with their control terminals, but indirectly and gradually receive the block-enabling signal EN_q through corresponding one or ones of the 1˜(K−1) delayed gating lines. A combination of a circuit block BLK_q and its corresponding gate-controlled elements, buffers, delayed gating lines, and so forth adopted during the layout process is defined as a layout block in the specification.
The layout method of the disclosure provides two types of delayed gating lines to connect the gate-controlled elements, depending on the distance between two connected gate-controlled elements. The delayed gating line routed according to Type A means that the buffer buf connects the control terminal of the gate-controlled element selected as the source node src to the control terminal of the gate-controlled element selected as the destination node dst, wherein the two gate-controlled elements are neighboring gate-controlled elements (as shown in
When the gate-controlled element selected as the source node src of one delayed gating line is switched on, the gate-controlled element selected as the destination node dst of the same delayed gating line is also switched on. As the delayed gating line routed according to Type A has a shorter distance between the gate-controlled element selected as the source node src[i] and the gate-controlled element selected as the destination node dst[i], the switch-on time difference between the two gate-controlled elements is shorter. The delayed gating line routed according to Type B has a longer distance between the gate-controlled element selected as the source node src[i] and the gate-controlled element selected as the destination node dst[i] so that the switch-on time difference between the two gate-controlled elements is longer. Although the switch-on time difference in one delayed gating line, regardless of Type A or Type B, is quite short, the gate-controlled element selected as the source node src[i] and the gate-controlled element selected as the destination node dst[i] are not switched on simultaneously. Actually, the gate-controlled elements are switched on sequentially.
The gate-controlled elements selected as the source node src[i] and the destination node dst[i] of the ith delayed gating line are arranged clockwise in the drawings. The two gate-controlled elements selected as the source node src[i] and the destination node dst[i] in one clockwise layout loop have the relationship that the gate-controlled element selected as the source node src[i] has a smaller sequence number than the gate-controlled element selected as the destination node dst[i]. The exception is that the gate-controlled element selected as the source node src[i] is located at the fourth side, and the gate-controlled element selected as the destination node dst[i] is located at the first side. At this time, the gate-controlled element selected as the source node src[i] has a larger sequence number than the gate-controlled element selected as the destination node dst[i].
In the disclosure, the gate-controlled element for the enablement input node p_enIN is routed as the source node only, and the gate-controlled element for the destination node dst[K−1] of the (K−1)th delayed gating line is routed as the destination node only. Except for these two gate-controlled elements, other gate-controlled elements are routed as both the destination node dst[i] of one delayed gating line (for example, the ith delayed gating line) and the source node src[i+1] of the next delayed gating line (for example, the (i+1)th delayed gating line). In other words, after the gate-controlled element being selected as the destination node dst[i] is switched on, it is further selected as the source node src[i+1] to make the gate-controlled element being selected as the destination node dst[i+1] switched on.
The layout method of the disclosure routes the delayed gating line according to Type A as follows. The input terminal of a buffer buf is connected to the control terminal of the gate-controlled element p_(k−3) as the source node src, and the output terminal of another buffer buf is connected to the control terminal of the gate-controlled element p_(k−2) as the destination node dst. The control terminal of the gate-controlled element p_(k−1) as the destination node dst is connected to the control terminal of the gate-controlled element p_(k−2) as the source node src through a further buffer buf. The control terminal of the gate-controlled element p_k as the destination node dst is connected to the control terminal of the gate-controlled element p_(k−1) as the source node src through a further buffer buf. The control terminal of the gate-controlled element p_(k+1) as the destination node dst is connected to the control terminal of the gate-controlled element p_k as the source node src through a further buffer buf. The control terminal of the gate-controlled element p_(k+2) as the destination node dst is connected to the control terminal of the gate-controlled element p_(k+1) as the source node src through a further buffer buf. The control terminal of the gate-controlled element p_(k+2) as the source node src is connected to the control terminal of the gate-controlled element p_(k+3) as the destination node dst through a further buffer. Through the connection lines between the gate-controlled elements in
In
In
In
Comparing
Therefore, the control terminal of the gate-controlled element selected as the source node src actually receives the block-enabling signal EN_q slightly earlier than the control terminal of the gate-controlled element selected as the destination node dst. Also, the gate-controlled element selected as the source node src is switched on to conduct an associated branch current slightly earlier than the gate-controlled element selected as the destination node dst. Hence, the overall current flows from the supply voltage Vdd_q to the circuit block BLK_q are gradually increased when more and more branch currents are generated.
For illustration purposes, the embodiments give that there are K=92 gate-controlled elements arranged on the edge of the circuit block BLK_q, wherein L=30 gate-controlled elements (p_1˜p_30, p_47˜p_76) are arranged at the longer sides of the circuit block BLK_q, and W=16 gate-controlled elements (p_31˜p_46, p_77˜p_92) are arranged at the shorter sides of the circuit block BLK_q. In practical applications, the numbers K, L, and M are positive integers, L and M are much smaller than K, and K=2*(L+M). The values of K, L, and M are not limited to the embodiments of the disclosure. In fact, the number K may have a value up to thousands.
For illustration purposes, the gate-controlled elements p_1˜p_K are numbered along the clockwise direction, and the source nodes src[1]˜src[K−1] and the destination nodes dst[1]˜dst[K−1] of the ith delayed gating lines (i=1˜(K−1)) are determined based on the clockwise arrangement. Further, the gate-controlled element, as the source node src[1] of the first delayed gating line (i=1), is defined as the enablement input node p_enIN; and the gate-controlled element, as the destination node dst[K−1] of the (K−1)th delayed gating line (i=(K−1)), is defined as the layout loop-end position p_END. In practical applications, the layout method of the disclosure does not limit the numbering rule of the gate-controlled elements p_1˜p_K, the relative position between the source nodes src[1]˜src[K−1] and the destination nodes dst[1]˜dst[K−1] of the ith delayed gating lines (i=1˜(K−1)), and the position of the first numbered gate-controlled element at any side of the circuit block BLK_q.
As described above, two neighboring gate-controlled elements, used as the source node src[i] and the destination node dst[i] of the ith delayed gating line, are connected to each other through the buffer buf in
Please refer to both
The K gate-controlled elements p_1˜p_K in
The layout method of the disclosure routs the delayed gating line according to either Type A or Type B. There are three types of connection configurations for connecting the K gate-controlled elements p_1˜p_K on the edge of the circuit block BLK_q. The first type of connection configuration routes all the (K−1) delayed gating lines according to Type A; the second type of connection configuration routes all the (K−1) delayed gating lines according to Type B; and the third type of connection configuration routes some delayed gating lines according to Type A and other delayed gating lines according to Type B.
The second type of connection configuration is only applicable to the condition that the number K is a multiple of the number X (for example, K=92 and X=4), and the gate-controlled element p_1 is selected as the layout loop-initialization position p_INIT (that is, INIT=1). The second type of connection configuration for the layout needs Z=X layout loops to finish routing the delayed gating lines.
In the third type of connection configuration, it is not necessary that the first gate-controlled element of the routing section sec_1 is the gate-controlled element p_1. For illustration purposes, the first gate-controlled element of the routing section sec_1 is defined as the layout loop-initialization position p_INIT, wherein 1≤INIT≤L. Thus, Y is expressed as Y=floor((K−INIT+1)/X). When the layout loop-initialization position p_INIT is not the gate-controlled element p_1 (that is, INIT>1), it means that (INIT−1) gate-controlled elements located at the first side, where the layout loop-initialization position p_INIT is located, are selected to route the delayed gating lines according to Type A. Further, when K>((INIT−1)+Y*X), it means that R=(K−((INIT−1)+Y*X)) gate-controlled elements located at the fourth side are selected to route the delayed gating lines according to Type A.
According to the description above, to route the ith delayed gating line according to Type A, the source node src[i] and the destination node dst[i] of the ith delayed gating line are two neighboring gate-controlled elements. On the other hand, to route the ith delayed gating line according to Type B, the source node src[i] and the destination node dst[i] of the ith delayed gating line are two non-neighboring gate-controlled elements.
No matter whether the ith delayed gating line is routed according to Type A or Type B, the procedure of selecting the gate-controlled elements as the source node src[i] and the destination node dst[i] determines the sequence of switching on the gate-controlled elements. Especially, after the gate-controlled element selected as the source node src[i] is switched on, the buffer buf connected to the two gate-controlled elements delays the block-enabling signal EN_q and conducts the delayed signal to the control terminal of the gate-controlled element selected as the destination node dst[i]. Therefore, the switch-on time point of the gate-controlled element selected as the destination node dst[i] is slighter later than the switch-on time point of the gate-controlled element selected as the source node src[i]. Hence, the gate-controlled element selected as the source node src[i] and the gate-controlled element selected as the destination node dst[i] are sequentially switched on. Therefore, in the disclosure, the two ends of the ith delayed gating lines (i=1˜(K−1)) determine not only how the buffers buf are routed between the gate-controlled elements, but also the switch-on order of the gate-controlled elements p_1˜p_92 which conduct the supply voltage Vdd_q to the circuit block BLK_q.
It could be seen from
It can be seen from
Table 2 shows how the gate-controlled elements p_1˜p_92 are selected to route the delayed gating lines according to Type A through the layout methods of
The simplest case to route the ith delayed gating line is that the gate-controlled element p_1 is selected as the enablement input node p_enIN (that is, p_enIN=p_1). In this case, the gate-controlled element p_i is selected as the source node src[i] of the ith delayed gating line, and the gate-controlled element p_(i+1) is selected as the destination node dst[i] of the ith delayed gating line.
On the other hand, if the gate-controlled element p_1 is not selected as the enablement input node p_enIN (p_enIN≠p_1), there are three conditions to route the ith delayed gating lines based on the relation between the values of i, enIN, K. In the first condition of 1≤i≤(K−enIN), the gate-controlled element p_(i+enIN−1) is selected as the source node src[i] of the ith delayed gating line, and the gate-controlled element p_(i+enIN) is selected as the destination node dst[i] of the ith delayed gating line. In the second condition of i=(K−enIN+1), the gate-controlled element p_K is selected as the source node src[i] of the ith delayed gating line, and the gate-controlled element p_1 is selected as the destination node dst[i] of the ith delayed gating line. In the third condition of (K−enIN+2)≤i≤(K−1), the gate-controlled element p_(enIN+i−K−1) is selected as the source node src[i] of the ith delayed gating line, and the gate-controlled element p_(enIN+i−K) is selected as the destination node dst[i] of the ith delayed gating line.
In the embodiments with reference to
Based on the composition of the routing sections sec_1˜sec_15 in
To route the delayed gating lines according to Type B, a few layout loops, which start from the enablement input node p_enIN and circulate the edge of the circuit block BLK_q along a clockwise direction, for repetitively selecting the source nodes src[i] and the destination nodes dst[i] as the ith delayed gating lines (i=1˜(K−1)), are required. Herein, the variable Z represents the number of the layout loops around the circuit block BLK_q to route the delayed gating lines, each of which has a distance of X gate-controlled elements, wherein Z is a positive integer and Z≤X. Several layout loops circulating the circuit block BLK_q are required to route the (K−1) delayed gating lines (i=1˜(K−1)), and each of the layout loops z=1˜Z, in which the ith delayed gating lines (i=1˜(K−1)) are routed, are illustrated in the embodiments with respective figures.
To make the drawings easy to read, the gate-controlled elements p_1˜p_92 are shown with the corresponding screentone according to its role during the layout loop. The lattice screentone represents that the gate-controlled elements are selected as the delayed gating lines during the current layout loop, the dotted screentone represents that the gate-controlled elements have been selected as the delayed gating lines during the previous layout loop, and the white cell represents the delay gate-controlled elements which have not been selected for routing the delayed gating lines yet.
The first group of rows of Table 6 lists the gate-controlled elements selected for routing the ith delayed gating lines (i=1˜15). The gate-controlled elements p_1, p_7, p_13, p_19, p_25, p_31, p_37, p_43, p_49, p_55, p_61, p_67, p_73, p_79, p_85 are selected as the source nodes src[1]˜src[15] of the ith delayed gating lines (i=1˜15); and the gate-controlled elements p_7, p_13, p_19, p_25, p_31, p_37, p_43, p_49, p_55, p_61, p_67, p_73, p_79, p_85, p_2 are selected as the destination nodes dst[1]˜dst[15] of the ith delayed gating lines (i=1˜15).
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In
According to the descriptions of
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In
For example, in
Please refer to
It is to be noted that the source node src[15] of the ith delayed gating line (i=15) is located at the fourth side of the circuit block BLK_q, but the destination node dst[15] is located at the first side of the circuit block BLK_q. Therefore, one circulation along the edge of the circuit block BLK_q is complete after the ith delayed gating line (i=15) is connected. At this time, the zth layout loop (z=1) in which the delayed gating lines are routed according to Type B is complete, as shown in
It can be seen from
In
Please refer to both
Please refer to
In practical applications, the layout method could route the delayed gating lines according to Type B during several layout loops and then route the delayed gating lines within the same routing sections according to Type A. In addition, the delayed gating lines crossing different routing sections are routed according to Type B, if any. The embodiments with reference to
In a concise manner, the disclosure only describes how to select the gate-controlled elements to route the first delayed gating lines (that is, i=(z−1)*Y+1) and the last delayed gating lines (that is, i=z*Y) according to Type B during the zth layout loops (z=1˜6), and these delayed gating lines are indicated by thicker dotted arrows in
After the ith delayed gating line (i=90) is connected, the remaining unselected gate-controlled elements cannot form the delayed gating lines having a length of X=5 gate-controlled elements. At this time, according to the positions of the gate-controlled elements and the order of routing the delayed gating lines, the gate-controlled elements p_85, p_87 immediately adjacent to the gate-controlled element p_86 have been selected as the delayed gating lines. Therefore, after the gate-controlled element p_86 is selected as the destination node dst[89], the delayed gating line cannot be routed according to Type A by selecting the gate-controlled element p_86 as the source node src[89]. As shown in
In
From the comparison between
During the zth layout loops (z=1˜6) when the delayed gating lines are routed according to Type B, the layout of the delayed gating lines between the gate-controlled elements p_1˜p_90 could be different due to different selections of the loop starting positions p_SEL[z]. For example, the ith delayed gating line (i=90) is connected between the gate-controlled elements p_90 and p_91 in
The destination node dst[90] of the ith delayed gating line (i=90) is the gate-controlled element p_91 in both
In the embodiments with reference to
In the above embodiments, the case of the layout loop-initialization position p_INIT=p_1=p_SEL[1] is given. In practical applications, the layout loop-initialization position p_INIT may be any one of the gate-controlled elements p_1˜p_30 at the first side. According to the embodiments in
Please refer to both Table 10 and
The layout in
Please refer to
In other words, when the gate-controlled element p_87 is selected as the destination node dst[83], the distance between the gate-controlled element p_87 and the gate-controlled element p_81 selected as the source node src[83] is X=6 gate-controlled elements. On the other hand, when the gate-controlled element p_87 is selected as the source node src[84], the gate-controlled element p_87 is immediately adjacent to the gate-controlled element p_88, as the destination node dst[84]. Therefore, the gate-controlled element p_87 is viewed as a boundary position p_BDRY connected to two delayed gating lines of inequivalent length.
Please refer to both
Table 12 compares the embodiments with reference to
As described above, according to the concepts of the disclosure, the gate-controlled elements p_1˜p_K do not synchronously conduct the supply voltage Vdd_q to the circuit block BLK_q immediately after the circuit block BLK_q starts to receive the supply voltage Vdd_q. The disclosure provides a method for sequentially switching on the gate-controlled elements p_1˜p_K in a specific order so as to gradually increase the currents received by the circuit block BLK_q. When the circuit block BLK_q is switched from the disabled mode MDoff to the enabled mode MDon to receive the supply voltage Vdd_q, this method can significantly reduce the fluctuation of the voltage interfering in the other circuit blocks BLK_1˜BLK_(q−1) and BLK_(q+1)˜BLK_Q in the enabled mode MDon.
The embodiments of the disclosure set X=6 to simplify the description. In practical applications, X is a positive integer, and 0≤X≤L. A larger value of X will result in a longer length of the delayed gating lines connected between the gate-controlled elements, and thus the overall current received by the circuit block BLK_q through the gate-controlled elements increases slower. Also, when the circuit block BLK_q switched from the disabled mode MDoff to the enabled mode MDon, the voltage change affects the other circuit blocks BLK_1˜BLK_(q−1) and BLK_(q+1)˜BLK_Q in a relatively smooth manner during the transition process. After certain simulations, it is observed that the propagation delay during the switching operations is transient and the normal operation of the circuit block BLK_q is not affected.
Although the above description takes the circuit block BLK_q as an example, the layout method can be modified to be applied to other circuit blocks BLK_1˜BLK_(q−1) and BLK_(q+1)˜BLK_Q. In practical applications, the Q circuit blocks BLK_1˜BLK_Q of the integrated circuit may receive the supply voltage Vdd_1˜Vdd_Q of equivalent or inequivalent values, and the values of the variables K, X, Y associated with the circuit blocks BLK_1˜BLK_Q may be adjusted for different cases. The integrated circuit could further include a power control circuit (not shown) electrically connected to the circuit blocks BLK_1˜BLK_Q. The power control circuit controls the voltage-switching circuit to generate and conduct the block-enabling signals EN_1˜EN_Q to gate-controlled elements on corresponding circuit blocks BLK_1˜BLK_Q in response to the enabled mode MDon/disabled mode MDoff of the circuit blocks BLK_1˜BLK_Q. Such modification or variation for the applications can be derived from the description and need not be described in detail herein.
In the above embodiments, the gate-controlled elements p_1˜p_K are placed between the supply voltage Vdd_q and the circuit block BLK_q. To activate the circuit block BLK_q, the supply voltage is provided to the circuit block BLK_q through the gate-controlled elements in a specific sequence according to the connection configuration applied to the gate-controlled elements p_1˜p_K in the layout. In practical applications, the gate-controlled elements could be placed between the ground voltage Gnd and the circuit block BLK_q. The layout method determines how delayed gating lines are routed between the gate-controlled elements. To disable the circuit block BLK_q, the ground voltage is conducted to the circuit block BLK_q through the gate-controlled elements p_1˜p_K in a specific sequence according to the connection configuration applied to the gate-controlled elements p_1˜p_K in the layout. Such applications can be derived from the description and will not be described in detail herein.
In practical applications, the concepts of the disclosure can be modified to divide the K gate-controlled elements into layout configuration-sections and determine the layout of each layout configuration-section. For example, there are two layout configuration-sections LOsec_A and LOsec_B arranged on the edge of the circuit block BLK_q. The layout configuration-section LOsec_A includes routing sections sec_A1˜sec_AY collectively including K1 gate-controlled elements, and each of the routing sections sec_A1˜sec_AY includes X1 gate-controlled elements; and the layout configuration-section LOsec_B includes routing sections sec_B1˜sec_BY collectively including K2 gate-controlled elements, and each of the routing sections sec_B1˜sec_BY includes X2 gate-controlled elements, wherein (K1+K2)=K, and X1, X2 may have equivalent or inequivalent values. The associated layout processes requiring variable substitution to arrange the delayed gating lines are still included in the scope of the present application.
The concepts of disclosure do not limit the implementation of the layout method. For example, the layout method can be executed by a software program recorded in a non-transitory computer-readable medium or a computer-readable medium to perform the layout associated with an integrated circuit. In practical applications, the layout method of the disclosure can be selected with electronic design automation (EDA) software for the circuit layout environment. The combination of the layout method of the disclosure and various computer-aided design software is applicable to the person skilled in the arts and is not described in detail herein.
It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 112107302 | Mar 2023 | TW | national |
