LC Oscillator Powering Arrangement and Method of Powering an LC Oscillator

Abstract

An LC oscillator powering arrangement comprises an LC oscillator configured to provide an oscillating signal output; a current source configured to supply the LC oscillator with a supply current, the current source during operation being controlled by a control voltage and supplied with a supply voltage subject to supply voltage ripple; and a replication block configured to generate an amplified replica of the supply voltage ripple directly from the supply voltage and to overlay the replica on the control voltage.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a non-provisional patent application claiming priority to European Patent Application No. EP 18175371.6, filed May 31, 2018, the contents of which are hereby incorporated by reference.

FIELD OF THE DISCLOSURE

The present disclosure relates to an LC oscillator powering arrangement and a method of powering an LC oscillator.

BACKGROUND

Portable devices, such as Internet-of-Things (IOT) devices, often include LC oscillators for radio communication purposes and may be powered by batteries or energy harvesters.

The devices may include DC-DC converters to transform output levels from power sources to a nominal supply voltage of circuitry of the IOT devices. However, switching operation of the DC-DC converters may cause output ripples in supply voltage. Such ripples may degrade the performance of circuitry that is sensitive to the supply voltage. For instance, ripples in supply voltage to an LC oscillator may cause periodic amplitude variations and may cause the LC oscillator to output a varying oscillating frequency leading to large spurs in the LC oscillator output spectrum

SUMMARY

The present disclosure relates to an LC oscillator powering arrangement which may ensure that an oscillation frequency output by the LC oscillator is accurately controlled.

According to an aspect of the present disclosure there is provided an LC oscillator powering arrangement, comprising an LC oscillator configured to provide an oscillating signal output; a current source configured to supply the LC oscillator with a supply current, where during operation the current source is controlled by a control voltage and supplied with a supply voltage subject to supply voltage ripple; and a replication block configured to generate a replica of the supply voltage ripple directly from the supply voltage and to overlay the replica on the control voltage.

Ripple present on the supply voltage will affect the current supplied by the current source to the LC oscillator, resulting in a time-varying oscillation amplitude. By overlaying a replica of the supply voltage ripple on the control voltage controlling the current source, this effect may be compensated for.

The replication block may be configured to generate a replica of the supply voltage ripple or an amplified replica of the supply voltage ripple. Thus, the generated replica may have the same amplitude as the ripple, be amplified with a pre-determined gain, or be amplified with a variable gain settable in a calibration procedure.

The LC oscillator powering arrangement according to the first aspect is configured to generate a replica of a ripple directly from the supply voltage. Generating the replica directly from the supply voltage should be understood as the replica being generated, over the cycle of periodic variations (ripple) of the supple voltage, from that supply voltage and not, for example, based in whole or part on the output of the LC oscillator. Using such a replica generated directly from the supply voltage, instead of, for example, from detection of the time-varying amplitude of the LC oscillator output, may avoid delay effects in the LC oscillator and detection circuitry, leading to compensation for the supply voltage ripple.

Because the LC oscillator power arrangement may be able to provide a stable supply current, despite supply voltage ripple, the use of power-consuming linear regulators, such as low-dropout linear regulators (LDOs), may be avoided. This may allow the LC oscillator to be run directly on the output of a DC-DC converter, such as a switched-mode power supply. As such, power may be saved.

According to one embodiment, the LC oscillator powering arrangement further comprises a calibration block, where the replication block is configured to amplify the replica with a tunable fractional gain settable by the calibration block, the calibration block being connected to the oscillating signal output of the LC oscillator and configured to minimize the amplitude variation of the oscillating signal output of the LC oscillator by determining an optimum value of the tunable fractional gain of the replication block.

This calibration may be performed on a time scale longer, and typically much longer, than the cycle of periodic variations (ripple) of the supple voltage.

The current source may be controlled to output a stable supply current despite supply voltage ripple by providing a replica of the supply voltage ripple to the control voltage. However, a replica on the control voltage based on a fixed pre-determined gain may not compensate for the supply voltage ripple. In particular, the arrangement may be affected by process, voltage and temperature (PVT) variations. Thus, the replica of the ripple may be amplified with an adjustable gain in order to ensure that a compensation for supply voltage ripple is provided, which is insensitive to PVT variations.

Using the calibration block, the oscillating signal may be analyzed in order to set a gain that include compensation for PVT variations or any other factors causing variation in the optimal gain between the supply voltage ripple and the replica.

The replication block may be configured to amplify the replica with a gain that is a combination of a fixed gain and a tunable fractional gain, which is set by the calibration block.

The fixed gain may be set to 1, whereas an tunable fractional gain may be determined by the calibration block in order to determine a suitable compensation for supply voltage ripple.

This allows the gain of the replica to be fine-tuned for attenuation of the amplitude variation of the LC oscillator output.

According to one embodiment, the calibration block comprises a detector configured to detect an amplitude variation of the oscillating signal output of the LC oscillator; a comparator comparing the amplitude variation with a reference voltage; and a controller connected to the comparator and configured to set the tunable fractional gain of the replication block during calibration.

Using the detector and the comparator, the calibration block may be configured to determine how the amplitude variation is affected by tuning the fractional gain. This may be used in order to determine an optimum value of the tunable fractional gain, which may then be set by the controller.

According to one embodiment, the LC powering arrangement is configured so that, during the minimizing of the amplitude variation, the reference voltage is set to a value larger than a minimum of the amplitude variation, the controller being configured to determine the optimum value of the tunable fractional gain as an average of a lower gain corresponding to a first output transition of the comparator and a higher gain corresponding to a second output transition of the comparator.

This allows the optimal gain of the replica to be accurately determined in a circuit, reducing complexity, power consumption, and cost.

According to one embodiment, the current source is a MOS transistor.

Thus, the current source may be implemented as a circuit component, which implies that the LC oscillator powering arrangement may be compact.

According to one embodiment, the current source is a PMOS transistor, the supply voltage is applied at a source terminal of the PMOS transistor, the control voltage is applied at a gate terminal of the PMOS transistor, and the supply current is drawn from a drain terminal of the PMOS transistor.

The supply current of the PMOS transistor may be controlled by a gate-to-source voltage. By providing a replica of the supply voltage ripple at the gate terminal, the supply voltage ripple provided at the source terminal may be compensated for.

However, for nanoscale PMOS transistors, the supply current may also depend on a drain-to-source voltage. This implies that an amplified replica of the supply ripple may be used.

The use of a calibration block for providing a tunable fractional gain may ensure that an amplification of the supply ripple is used, which may compensate for PVT variations.

According to one embodiment, the tunable fractional gain is settable by a n-bit digital code, where n is a predetermined integer.

This implies that a predetermined resolution of setting the tunable fractional gain may be used and that a trade-off between the time for determining the optimum value of the tunable fractional gain by the calibration block and the achievable resolution may be made, given a chosen dynamic range for the gain, by setting the predetermined integer.

According to one embodiment, the replication block comprises a replicating part, providing unitary gain, and a fractional part providing the tunable fractional gain, the fractional part comprising n injection blocks each individually switchable by an individual bit in the n-bit digital code.

This implies that the digital code may be used in order to quickly control the gain of the replication block, since an injection block may easily be controlled to contribute to the gain in dependence on a bit of the digital code.

According to one embodiment, the replicating part comprises a diode-connected PMOS transistor in series with two NMOS transistors forming a cascode, and each of the injection blocks comprises a current-source PMOS transistor in series with a switching PMOS transistor, a gate terminal of the switching PMOS transistor being connected to a corresponding the individual bit of the digital code and a drain terminal of the switching PMOS transistor being connected to a node of the cascode.

The replicating part may provide a unitary gain. By connecting a drain of the switching PMOS transistor to a node of the cascode of the replicating part, a fractional gain may be added to the unitary gain based on a signal, corresponding to the individual bit of the digital code, provided on the gate terminal of the switching PMOS transistor.

According to one embodiment, the detector comprises a peak detector, an amplifier, and a low-pass filter.

The peak detector may detect an amplitude variation of the oscillating signal output of the LC oscillator. This amplitude variation may further be amplified in order to facilitate detection of the amplitude variation. Further, the low-pass filter may ensure that the amplitude variation may be separated from an oscillation frequency of the LC oscillator and harmonics thereof.

According to one embodiment, the LC oscillator powering arrangement is provided on a single chip.

This implies that the LC oscillator powering arrangement may be compact and small size, ensuring that the LC oscillator powering arrangement is suitable for use e.g. in IOT devices.

According to another aspect of the present disclosure, there is provided a method of powering an LC oscillator, the method desensitizing the LC oscillator from supply voltage ripple and comprising: applying a supply voltage driving a current source, the supply voltage being subject to supply voltage ripple; generating a replica of the supply voltage ripple directly from the supply voltage; and applying a control voltage at the current source, the control voltage being overlaid with the replica, supplying the LC oscillator with a supply current from the current source.

Effects and features of this second aspect are largely analogous to those described above in connection with the first aspect. Embodiments mentioned in relation to the first aspect are largely compatible with the second aspect.

By applying a control voltage at a current source, wherein the control voltage is overlaid with a replica of supply voltage ripple generated directly from the supply voltage, a compensation of the supply voltage ripple on the supply current generated may be provided.

The above, as well as additional aspects, features and advantages of the present disclosure, will be understood through the following illustrative and non-limiting detailed description, with reference to the appended drawings. In the drawings like reference numerals will be used for like elements unless stated otherwise.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1a is a conceptual block diagram of an LC oscillator powering arrangement with the equivalent model, according to an example embodiment.

FIG. 1b is a conceptual block diagram of the proposed supply pushing reduction technique using a calibration loop, according to an example embodiment.

FIG. 2 shows simulation results of an LC oscillator with the proposed technique, according to an example embodiment.

FIG. 3 shows the operating principle of the calibration loop based on oscillation amplitude variation (ΔV_osc), according to an example embodiment.

FIG. 4 is a block diagram of a calibration loop, according to an example embodiment.

FIG. 5a shows the operating principle of the calibration loop using a proposed algorithm, according to an example embodiment.

FIG. 5b is a flow chart of the calibration loop with the proposed algorithm, according to an example embodiment.

FIG. 6a shows a simulated transfer function from peak detector output to comparator input in the calibration loop, according to an example embodiment.

FIG. 6b shows a simulated power spectrum density of noise at comparator input with contributions from different noise sources, according to an example embodiment.

FIG. 7 is a schematic of an implemented LC oscillator with a ripple replication block, according to an example embodiment.

FIG. 8a shows the output noise of the ripple replication block, according to an example embodiment.

FIG. 8b shows a schematic of a symmetrical transformer of the LC oscillator, according to an example embodiment.

FIG. 8c shows the phase degradation of the LC oscillator with and without the common mode resonance, according to an example embodiment.

FIG. 9 shows a chip micrograph of the LC oscillator with reduced supply pushing, according to an example embodiment.

FIG. 10a shows measured phase noise of the oscillator across a gain tuning range of the calibration loop, according to an example embodiment.

FIG. 10b shows measured spur level over a control code S_t provided by the calibration loop, according to an example embodiment.

FIG. 11a shows measured spur levels over sinusoidal ripple frequency, according to an example embodiment.

FIG. 11b shows the corresponding supply pushing for both manual and automatic calibrations, according to an example embodiment.

FIG. 11c shows measured spur levels over the oscillation frequency under the sinusoidal ripple, according to an example embodiment.

FIG. 11d shows the corresponding supply pushing for both manual and automatic calibrations, according to an example embodiment.

FIG. 11e shows measured spur levels over the frequency of sawtooth ripple, according to an example embodiment.

FIG. 11f shows measured spur levels over the oscillation frequency under the sawtooth ripple, according to an example embodiment.

FIG. 12a shows measured oscillator spectra before and after calibration under 50 mV peak-to-peak 5 MHz sinusoidal ripple, according to an example embodiment.

FIG. 12b shows measured oscillator spectra before and after calibration under 50 mV peak-to-peak 5 MHz saw-tooth ripple, according to an example embodiment.

FIG. 12c shows measured oscillator spectra under 50 mV peak-to-peak 2.5 MHz sinusoidal ripple, according to an example embodiment.

FIG. 12d shows measured oscillator spectra under 20 mV peak-to-peak 2.5 MHz sinusoidal ripple, according to an example embodiment.

FIG. 13 shows measured spur levels over 0-80° C., according to an example embodiment.

DETAILED DESCRIPTION

An LC oscillator powering arrangement is provided which is insensitive to supply voltage ripple so that an LC oscillator may provide an oscillation output frequency.

In the following, the operating principle of a technique for avoiding that a variation in supply voltage pushes or affects an oscillation output frequency, wherein the technique is based on replication of supply voltage ripple and in order to cancel an effect of the supply voltage ripple, will be elaborated. Particular reference will be made to a detailed circuit realization of a 5 GHz LC oscillator with the proposed feed-forward supply pushing reduction technique and an on-chip calibration loop.

FIG. 1a illustrates the operating principle of providing supply pushing reduction. In an LC oscillator powering arrangement 100, an LC oscillator 110 comprising a resonant tank 120, comprising an inductor and a capacitor, and cross-coupled transistors M₁, M₂, M₃ and M₄ is supplied with current I₀ from a current source.

In this embodiment, the current source is illustrated as being implemented by way of a MOS transistor, in this example a PMOS transistor M₀, supplying the LC oscillator 110 with a supply current I₀. The transistor M₀ is supplied with voltage V_DD, which is applied at its source terminal, and controlled by a control voltage V_b0, which is applied at its gate terminal. To stabilize I₀, and thus the oscillating signal output V_osc being output by the LC oscillator 110, in face of V_DD variations, a replica G A_ripple of the supply ripple A_ripple is generated at a ripple replication block 130, directly from the supply voltage V_DD, and overlaid on the gate of PMOS current source transistor M₀. In one case, if the replica is an exact copy of the supply voltage, i.e., G=1, the gate-to-source voltage V_gs of the PMOS current source transistor M₀ will be stabilized. As a result, the variation of I₀, and thereby of V_osc, may be suppressed.

The variation of oscillating frequency f_osc of the LC oscillator 110 with the supply voltage, V_DD, may be caused by the variation of parasitic capacitances seen by the resonant tank 120. The cross-coupled transistors M₁-M₄ provide a negative transconductance to sustain the oscillation and will experience cut-off, saturation and triode operating regions during each oscillation cycle. When V_DD varies, the supply current, I₀, and the corresponding oscillation amplitude, V_osc, will also vary. Thus it will change the time interval during which the transistors stay in each operating region. Since the gate capacitance of MOS transistors shows nonlinear dependence on the voltages at their terminals (i.e. gate-to-source voltage V_gs and drain-to-source voltage V_ds), the change in the operating states of MOS transistors would vary the equivalent parasitic capacitance, C_par,equ. Thus, the oscillating frequency will be pushed. If a periodical ripple is on V_DD, I₀ and V_osc will also show periodical variations. Therefore, the change of C_par,equ will also be periodical and could manifest itself as large spurs in the output spectrum of the LC oscillator 110. Stabilizing I₀ and V_osc under V_DD variations allows a clean output spectrum to be obtained when V_DD contains ripples.

If M₀ is a device, whose drain current is controlled by its V_gs according to the square law, then an exact copy of the supply ripple waveform is may be used at its gate terminal V_b0 to keep I₀ and V_osc constant. However, for nanoscale CMOS technologies, a channel-length modulation effect is not negligible. This means that the drain current of M₀ may depend on its Vs. Thus in order to compensate for residue current variation due to the variation of V_ds of M₀, some embodiments may use an amplified replica of the supply ripple in the waveform at V_b0.

FIG. 1a also shows the equivalent model to estimate the optimum gain (G_opt). Based on this model, the supply voltage variation, ΔV_DD, induced supply current variation, ΔI_0,VDD, could be calculated as

$\begin{array}{cc}\Delta I_{0,V_{\mathrm{DD}}}=\frac{1+g_{m0}·r_{o0}}{r_{o0}+Z_{\mathrm{eq}}}\Delta V_{\mathrm{DD}},& \left(1\right)\end{array}$

while the supply current variation induced by control voltage variation ΔV_b0=G·ΔV_DD is

$\begin{array}{cc}\Delta I_{0,V_{b0}}=-\frac{g_{m0}·r_{o0}}{r_{o0}+Z_{\mathrm{eq}}}\Delta V_{b0},& \left(2\right)\end{array}$

where Z_eq is the large-signal equivalent impedance of the cross-coupled transistors M₁-4 and the resonant tank 120 that is seen by M₀, while g_m0 and r_o0 are the effective transconductance and output resistance of M₀, respectively. To compensate for the supply current variation due to V_ds, the magnitudes of (1) and (2) should be equal. Hence, G_opt may be calculated as

$\begin{array}{cc}{G}_{\mathrm{opt}}\approx 1+\frac{1}{g_{m0}·r_{o0}}.& \left(3\right)\end{array}$

Since g_m0·r_o0 is relatively large (e.g. >10), G_opt is slightly larger than 1.

As shown in simulation results in FIG. 2, the variations of I₀ and V_osc may be largely suppressed when the waveform applied at V_b0 is the same as that of the supply ripple (gain, G=1). Hence, the frequency variations due to the supply voltage are largely reduced, resulting in a much lower supply pushing of the oscillator. FIG. 2 also shows that I₀ and V_osc are further stabilized (i.e. ˜10 times smaller variations compared to the G=1 case) under supply variations when G≈G_opt, thus the supply pushing of the oscillator becomes much lower.

Portable devices such as Internet-of-Things (IOT) devices powered by batteries or energy harvesters may include buck and/or switching DC-DC converters to transform the output levels of energy sources to the nominal supply voltage of IOT electronic circuitry. Due to the switching operation of DC-DC converters, the resulting output ripples can degrade performance of the supply-sensitive circuitry, such as LC-tank oscillators, when connected directly. This supply pushing of LC-tank oscillators may be reduced to allow them to operate from DC-DC converters, which naturally contain high level of ripples. To avoid this, a low dropout (LDO) linear regulator is usually inserted after the switching converter to stabilize the supply voltage. However, the extra voltage overhead (˜200 mV) may worsen the system's power efficiency (˜80% under 1V supply). This will make it even more critical with the supply scaling down with technology.

In the present disclosure, there is proposed a feed-forward supply ripple replication and cancellation technique which may be wholly contained within an LC oscillator in order to make it practically insensitive to supply ripples of switching DC-DC converters. Since, in the present disclosure, the LC oscillator may be driven directly from the output of the DC-DC converter, no extra voltage headroom may be used. Therefore, power can be saved.

Optionally, a calibration block, here in the form of a calibration loop 140, may also be implemented, optionally integrated on-die, as shown in FIG. 1b. The replication block 130 is configured to amplify the replica with a tunable fractional gain settable by the calibration block 140, with the calibration block 140 being connected to the oscillating signal output V_osc of the LC oscillator.

As can be gathered from equation 3, the optimum gain is prone to PVT variations. The calibration loop 140 may compensate for such variations, improving performance as compared to using a pre-determined gain.

The calibration scheme is based on measuring the variation of the oscillation amplitude, ΔV_amp, in response to the V_DD perturbations. FIG. 3 shows the operating principle of the calibration loop 140. When G<G_opt (case A), ΔI_0,Vb0 is smaller than ΔI_0,VDD, so ΔV_amp is in phase with ΔV_DD and decreases in magnitude as G gets closer to G_opt. However, when G>G_opt (case B), ΔI_0,Vb0 becomes larger than ΔI_0,VDD. Then, ΔV_amp is out of phase with ΔV_DD, and its magnitude increases again with the increase of G. At the optimum point, G=G_opt, and a constant oscillation, amplitude is maintained under supply variations.

Thus, the calibration loop 140 may be configured to measure ΔV_amp under different gain settings to calculate the optimum operating point for the oscillator circuit. Thus, the calibration block 140 is configured to minimize the amplitude variation ΔV_amp of the oscillating signal output V_osc of the LC oscillator 110 by determining an optimum value of a tunable fractional gain G of the replication block 130. The calibration loop 140 may be configured to only be active during calibration.

FIG. 4 shows an example block diagram of an integrated calibration loop 140. As discussed above, the perturbation of the oscillation amplitude, ΔV_amp, is used in the loop 140 as a stimulus to calibrate G_opt. The outputs of the oscillator may be first connected to a peak detector 410. The output V_pd of the peak detector 410, contains two frequency components: the one at f_ripple, and the additional one at the second harmonic of the oscillation frequency, f_osc. V_pd may then be amplified through self-biased inverters.

Two inverter stages 422, 424 with bandwidth of ˜20 MHz may be implemented. The inverter stages 422, 424 amplify the small input level at V_pd (e.g. 1 mV) to a larger amplitude (e.g., 250 mV) at the output V_inv, with a relatively large gain (e.g. 48 dB).

The output of the inverter chain, V_inv, may be filtered by an RC low-pass filter (LPF) 430. The cut-off frequency of the LPF 430 may be set to pass through the frequency component at f_ripple, while the second harmonic at 2×f_osc is filtered out. If there is any mismatch in the input differential pair of the peak detector, V_pd would contain a third frequency component at f_osc. Since f_osc (several GHz) is much higher than f_ripple (tens of MHz), this component is filtered out by the inverter chain and the LPF. Hence, the mismatch in the peak detector will not affect the calibration results.

The resulting transfer function from amplifier 420 input V_pd to LPF 430 output V_lpf is shown as a function of frequency in FIG. 6a.

Thus, the calibration block 140 comprises a detector—comprising the peak detector 410, the amplifier 420, and the LFP 430—configured to detect the amplitude variation ΔV_amp of the oscillating signal output V_osc of the LC oscillator 110.

The output of the LPF 430, V_lpf, may then be compared with a reference value, V_ref, through a comparator 440. V_ref is roughly set to a voltage higher than the product of the ΔV_amp and the DC gain of the peak detector 410 cascade with the inverter stages 422, 424.

The output V_out of the comparator 440 may be connected to the clock terminal of a D flip-flop (DFF) 450. When V_ref is crossed, the comparator's 440 output becomes high, triggering the output of the DFF to flip to 1. A digital algorithm in the loop monitors the latch output, Latch_out, and may calculate the optimum control code S_t (see below) for the ripple replication block 130. Other ways of controlling the replication block 130 are equally possible.

The digital block 460 attempts to find the minimum point of ΔV_amp vs. the control code (ΔV_amp,min in FIG. 5a). FIG. 5a shows the operating principle of the proposed technique. The reference voltage, V_ref, at the comparator input is roughly set to a value corresponding to an oscillation amplitude variation of ΔV_amp,th, which is higher than ΔV_amp,min. The calibration process starts from a small value of S_t, where G<G_opt and ΔV_amp>ΔV_amp,th. Thus, the initial value of Latch_out is 1. The algorithm keeps increasing S_t, which decreases ΔV_amp as G approaches G_opt. When ΔV_amp becomes lower than ΔV_amp,th, Latch_out changes from 1 to 0. The algorithm records this code as S_t,min, and then increases S_t again. When S_t is large enough, ΔV_amp would be higher than ΔV_amp,th again, and Latch_out switches back to 1. The algorithm records this code as S_t,max, and the optimum code, S_t,avg, is calculated as the average of these two recorded codes. FIG. 5b reveals the operational flow chart of this calibration process. The high-pass response of the loop due to AC-coupling limits the settling time when S_t changes. In this example, the corner frequency is designed to be ˜2.5 MHz, resulting in a settling time of 0.4 is per step. Lower corner frequency could be used to detect lower ripple frequency at the expense of longer settling time.

Thus, the LC powering arrangement 100 is configured so that, during the minimizing of the amplitude variation ΔV_amp, the reference voltage V_ref is set to a value larger than a minimum ΔV_amp,min of the amplitude variation, a controller, here in the form of digital block 460, being configured to determine the optimum value G_opt of the tunable fractional gain G as an average of a lower gain corresponding to a first output transition of the comparator 440 and a higher gain corresponding to a second output transition of the comparator 440.

Thus, in the present disclosure, a calibration algorithm is proposed whereby one comparator 440 without any offset calibration can be used in the loop. Otherwise, to precisely detect ΔV_amp,min, a set of comparators and DFFs may be used. The simulated amplitude variation at the output of the LPF is ˜300 mV. Thus, 20 comparators, followed by a DFF each, are able to achieve a voltage resolution of 15 mV Some offset calibration techniques could be used to reduce the input referred offset of comparators to a level much lower than the voltage resolution. The digital algorithm would then count the number of is in the output of the DFFs to determine ΔV_amp. Such a method would increase the design complexity greatly. Thus, the method of the present disclosure achieves an accurate determination of ΔV_amp,min while retaining low design complexity.

FIG. 6b shows the simulated power spectrum density (PSD) of noise at the comparator's input. A major part of the noise is contributed by the oscillator itself. The differential output of the oscillator is less affected by the variation of the common mode voltage, but the output level of the peak detector would be modulated. Thus, the calibration loop 140 is more sensitive to the common mode noise from the LC oscillator 110, e.g. noise of the supply current source. After being shaped by the transfer function of the inverter chain 420 and LPF 430, the common-mode noise is finally passed to the comparator's 440 input. From FIG. 6b, the integrated noise is around 14 mV, corresponding to ˜0.095 mV equivalent input noise at the input of the peak detector at 5 MHz f_ripple. To achieve less than −50 dBc spur level, ΔV_amp is simulated to be ˜1.8 mV (0.64 mV_rms), leading to a SNR of 16.5 dB, which is sufficient for an effective calibration.

FIG. 7 shows a schematic of an example ripple replication block 130 together with an example LC oscillator 110. The ripple replication block 130 is proposed to bias the gate terminal of current source M₀ of the LC oscillator 110. To generate the replica with the gain G larger than 1, the ripple replication block 130 is logically divided into two parts. The first part 132 (left dashed box in FIG. 7) contains a diode-connected PMOS transistor, M_b0, in series with two cascode NMOS transistors, Mb_1,2. Due to the high output impedance of the cascode, M_b0 can replicate the supply ripple to V_b0 with a fixed and unitary gain of 1. Thus, the first term on the right hand side of equation 3 is covered by this part.

To boost the gain above 1, the fractional part 134 (right dashed box in FIG. 7) is introduced to inject some extra current proportional to V_DD into the cascode node, V_inj. To digitally control the fractional gain, current source PMOS transistors M_pk(k=0, 1, . . . n) are individually turned on/off by switch PMOS transistors M_sk (k=−0, 1, . . . n) according to the digital code S_t generated by the calibration loop 140. Switching PMOS transistor M_pk drain terminal is connected to the node V_inj of the cascode.

Thus, the tunable fractional gain is settable by a n-bit digital code, where n is a predetermined integer and the fractional part of the replication block comprises n injection blocks each individually switchable by an individual bit in the n-bit digital code.

The fractional part thus provides an adjustable transconductance between V_DD and V_inj. The final gain G provided by the ripple replication block 130 can be approximated as

$\begin{array}{cc}G\approx 1+\frac{g_{m,f}}{g_{m,b0}}& \left(4\right)\end{array}$

where g_m,f and g_m,b0 are the total equivalent transconductance of the fractional part 134 and the transconductance of M_b0, respectively. Since G_opt is only slightly larger than 1, the g_m,f should be much smaller than g_m,b0. Therefore, the total current injected into V_inj may be smaller than the current consumed by M_b0, and would not lead to a large variation of the operating point of the LC oscillator. Moreover, the cascode transistor M_b1 could be removed for designs with lower V_DD. The slightly reduced gain provided by the first part could be compensated by slightly increasing g_m,f.

In this design, a channel length of 120 nm is used for M₀ leading to a load of ˜800 fF. When g_m/I_ds≈12, the total current consumption (including the fractional part) is ˜200 μA with a maximum G of ˜1.1. A 5-bit thermometer code is implemented to cover the aforementioned maximum G. The PMOS transistors in the fractional part are sized to achieve tuning resolution of ˜0.003 as a trade-off between the resolution and calibration time. The unit-gain bandwidth, co, of the ripple replication block is established by both the frequency of the supply ripple, f_ripple, and the tolerable phase shift between the ripple and the replica. To guarantee <−50 dBc spur level at f_ripple=20 MHz, a ω_u of 450 MHz may be used based on simulations. Together with the capacitive load at the output of the ripple replication block, this bandwidth determines the current consumption of this block. A smaller capacitance could be achieved when M₀ is designed with a minimum channel length. However, the G_opt would increase, which could adversely affect the tuning resolution and/or calibration time. The present design provides a compromise.

For the LC oscillator 110, as in this example, a complementary cross-coupled oscillator structure may be chosen. This leads to lower power consumption compared to its NMOS- and PMOS-only counterparts at same V_DD and equivalent parallel resistance of the tank. The designed oscillator uses a transformer-based resonant tank. Since the ripple replication block is connected to the gate of supply current source M₀, the replicator's output noise (see FIG. 8a), especially flicker noise of transistors M_b0,2, will modulate the oscillator's current, thus up-converting into output phase noise (PN) through a mechanism such as Groszkowski's effect. An implicit common-mode resonance technique is applied, which limits PN degradation. Single-ended capacitor banks are connected to a symmetrical transformer, as shown in FIG. 8b, are used to tune the common-mode resonance frequency to around 2×f_osc. Simulation results in FIG. 8c show that the PN degradation can be reduced to <IdB when the implicit common-mode technique is used. Both the NMOS and PMOS cross-coupled transistors M_1-4 provide the negative transconductance in the complementary structure. The body terminals of the PMOS cross-coupled pair, M_1,2, are deliberately connected to their source terminals to avoid the body effect. Otherwise, their threshold voltage, V_th, would be modulated under supply variations thus varying the oscillation amplitude V_osc, consequently pushing f_osc. Simulation results show that the supply pushing due to this body effect could be as high as 9.5 MHz/V Note that the above mentioned NMOS alternative to the supply current transistor M₀ would not be effective unless a costly triple-well technology is used.

The example LC oscillator 110 with the proposed powering arrangement 100 with feed-forward ripple replication and cancellation was implemented in TSMC 40-nm 1P8M CMOS process without ultra-thick metal layers. The proposed calibration loop 140 was also integrated on-die. FIG. 9 shows the chip micrograph. The total active area is 0.23 mm², in which the oscillator core occupies about 0.215 mm². The additional area occupied by the ripple replication block with its biasing circuit and the calibration loop 140 is just 0.012 mm². The symmetrical transformer was designed by stacking the top two metal layers with the aluminum capping layer, which enhances the tank's Q-factor. The spacing between each turn of the transformer was optimized for a magnetic coupling factor of 0.31. The simulated differential inductance of the transformer is 1.7 nH. The Q-factor of the whole tank is estimated to be ˜7. The capacitor banks are split into a 5-bit differential bank and a 5-bit common-mode bank to tune the common-mode resonance frequency.

The measured tuning range (TR) is 4.9-5.7 GHz (15%). FIG. 10a shows the measured PN performance across the TR. PN varies from −108 to 111 dBc/Hz @1 MHz offset, with a flicker noise corner of around 100 kHz. To verify the concept of the proposed technique, the control code S_t of the ripple replication block is manually swept while a 50 m V_pp (peak-to-peak) 5 MHz sinusoidal ripple is applied on the oscillator supply. As shown in FIG. 10b, there exists an optimum code at which the spur level is lower than −60 dBc, corresponding to a >27 dB improvement over the S_f=0 case. Note that G≈1 when S_t=0, and the oscillator already benefits from the significantly reduced supply pushing.

The effectiveness of the automatic calibration loop 140 is verified in FIG. 12a, which compares the spectra before and after the calibration. With the supply contamination by a 50 m V_pp 5 MHz sinusoidal ripple, the spur level is reduced by 30 dBc and reaches −68.7 dBc after the calibration. FIG. 11a shows the measured spur level over the frequency of the supply ripple. The proposed technique achieves ≤−49 dBc optimum spur levels under ≤50 m V_pp, 0.5-20 MHz sinusoidal ripples, while the calibrated spur levels closely follow the optimum ones in most cases. The increase of the spur level at high ripple frequencies is due to the bandwidth limitation of the ripple replication block, and could be extended by expending more power. In FIG. 1 lc, the spur level is measured across the tuning range of the oscillator. The worst-case spur under a 50 m V_pp 5 MHz sinusoidal ripple is ≤59 dBc. FIG. 11b and FIG. 11d show the oscillator's supply pushing based on the measured spur levels. When the ripple frequency is lower than 12 MHz, the calculated supply pushing is lower than 1 MHz/V for both the optimum and calibrated cases.

Similar measurements were also performed for saw-tooth ripples. FIG. 12b compares the spectra before and after the calibration. Under a 50 m V_pp 5 MHz saw-tooth ripple, the spur at the fundamental offset is reduced by 22.9 dB and reaches −61.7 dBc after the calibration. For spurs at higher harmonics, the suppression is also observed, but with lower magnitudes (5.8 dBc suppression for the second harmonic reaching −59.1 dBc after the calibration). FIG. 11e shows the spur levels over the ripple frequency. The worst-case spur of −47 dBc is found under ≤50 m V_pp, 0.5-20 MHz saw-tooth ripples, while the calibration results follow the optima. In FIG. 11f, the spurs are lower than −58 dBc within the entire tuning range under a 50 m V_pp 5 MHz saw-tooth ripple.

FIG. 12c shows the measured oscillator spectrum under a 50 m V_pp 2.5 MHz supply ripple. A spur can also be observed at an offset frequency of 5 MHz (i.e. 2×2.5 MHz). This second ripple harmonic spur mainly comes from the nonlinearity of the fractional part of the ripple replication block. To achieve fine tuning resolution, the transistors in this part are biased with small overdrive voltage, resulting in V_IP2≈140 mV and g_m/I_ds≈19. To improve the performance at the second ripple these transistors can be re-sized and biased with a different linearity and smaller g_m/I_ds. The resulting increase in current consumption would be quite small (i.e. ˜12 μA) since the current consumed by the fractional part is much smaller than that consumed by the integer part. Also, the spur at the second ripple harmonic reduces faster with the ripple amplitude. As shown in FIG. 12c, the measured spur level at the second harmonic is reduced to −65.9 dBc under a 20 m V_pp ripple, which should bear little practical consequences.

The IC chip was also measured over the temperature range of 0-80 C, and the results are shown in FIG. 13. The spur levels are lower than −60 dBc, except for the calibrated one at 80 C.

Table I summarizes the features and performance of the proposed technique.

TABLE 1
Description	Feed-forward compensation
Osc. Type	LC
Tech. (nm)	40 (w/o UTM)
Vpp (V)	1.0
Frequency Range (GHz)	4.9-5.7 (15%)
PN (dBc/Hz) @1 MHz	−107.9 to −110.9
Ripple amplitude	50 mVpp
Sinewave	Spur (dBc)	@1 MHz	<−54
		@5 MHz	<−58
	Ksup (MHz/V)	@1 MHz	<0.16*
		@5 MHz	<0.5*
	Improv. (dBc)	@1 MHz	18-24**
		@5 MHz	24-30**
Saw-tooth	Spur (dBc)	@1 MHz	<−50
		@5 MHz	<−58
	Improv. (dBc)	@1 MHz	11.3**
		@5 MHz	22-27**
Osc. Power Cons. (mW)	0.8-1.3
Power Cons. Ksup Reduction Tech. (mW)	0.2
Area of Ksup Reduction Tech (mm2)	0.012
Total area (mm2)	0.23
*Calculated value from the spur level.
**Compared with the case St = 0 (G = 1) where the supply pushing of the oscillator is already suppressed.

With the present disclosure, it is possible to significantly reduce supply pushing in current-mode LC oscillators while consuming no extra voltage headroom. The proposed ripple replication block 130 generates an amplified supply ripple replica GA_ripple at the gate terminal of the oscillator's 110 supply current source, in order to stabilize the supply current and oscillation amplitude under supply variations. The oscillation frequency is stabilized in turn, leading to <1 MHz/V supply pushing for supply ripples up to 12 MHz. To suppress the phase noise degradation due to the extra circuitry, implicit common mode resonance is used in the resonant tank. A calibration loop 140 with an algorithm is also integrated on-chip, which finds the optimum gain G for the ripple replication block 130.

The above disclosure has mainly been described with reference to a limited number of examples. However, other examples than the ones disclosed above are equally possible within the scope of the disclosure, as defined by the appended claims.

Claims

1. An LC oscillator powering arrangement, comprising: an LC oscillator configured to provide an oscillating signal output;a current source configured to supply the LC oscillator with a supply current, wherein during operation, the current source is controlled by a control voltage and supplied with a supply voltage subject to supply voltage ripple; anda replication block configured to generate a replica of the supply voltage ripple directly from the supply voltage and to overlay the replica on the control voltage.

2. The arrangement of claim 1, further comprising a calibration block, wherein the replication block is configured to amplify the replica with a tunable fractional gain settable by the calibration block, and wherein the calibration block is connected to the oscillating signal output of the LC oscillator and is configured to minimize an amplitude variation of the oscillating signal output of the LC oscillator by determining an optimum value of the tunable fractional gain of the replication block.

3. The arrangement of claim 2, wherein the calibration block comprises: a detector configured to detect the amplitude variation;a comparator configured to compare the amplitude variation with a reference voltage; anda controller connected to the comparator and configured to set the tunable fractional gain of the replication block during calibration.

4. The arrangement of claim 3, wherein during the minimizing of the amplitude variation, the reference voltage is set to a value larger than a minimum of the amplitude variation, and wherein the controller is configured to determine the optimum value of the tunable fractional gain as an average of a lower gain corresponding to a first output transition of the comparator and a higher gain corresponding to a second output transition of the comparator.

5. The arrangement of claim 1, wherein the current source is a MOS transistor.

6. The arrangement of claim 5, wherein the current source is a PMOS transistor, wherein the supply voltage is applied at a source terminal of the PMOS transistor, wherein the control voltage is applied at a gate terminal of the PMOS transistor, and wherein the supply current is drawn from a drain terminal of the PMOS transistor.

7. The arrangement of claim 2, wherein the tunable fractional gain is settable by a n-bit digital code, wherein n is a predetermined integer.

8. The arrangement of claim 7, wherein the replication block comprises a replicating part that provides unitary gain and a fractional part that provides the tunable fractional gain, wherein the fractional part comprises n injection blocks each individually switchable by an individual bit in the n-bit digital code.

9. The arrangement of claim 8, wherein the replicating part comprises a diode-connected PMOS transistor in series with two NMOS transistors forming a cascode, wherein each of the injection blocks comprises a current-source PMOS transistor in series with a switching PMOS transistor, a gate terminal of the switching PMOS transistor being connected to a corresponding the individual bit of the digital code, and a drain terminal of the switching PMOS transistor being connected to a node of the cascode.

10. The arrangement of claim 3, wherein the detector comprises a peak detector, an amplifier, and a low-pass filter.

11. The arrangement of claim 1, provided on a single chip.

12. A method of powering an LC oscillator, the method comprising: applying a supply voltage driving a current source, the supply voltage being subject to supply voltage ripple;generating, by way of a replication block, a replica of the supply voltage ripple directly from the supply voltage;applying a control voltage at the current source, the control voltage being overlaid with the replica; andsupplying the LC oscillator with a supply current from the current source.

13. The method of claim 12, wherein the replication block is configured to amplify the replica with a tunable fractional gain settable by a calibration block, wherein the calibration block is connected to an oscillating signal output of the LC oscillator, and wherein the calibration block is configured to minimize an amplitude variation of the oscillating signal output of the LC oscillator by determining an optimum value of the tunable fractional gain of the replication block.

14. The method of claim 13, wherein the calibration block comprises: a detector configured to detect the amplitude variation;a comparator configured to compare the amplitude variation with a reference voltage; anda controller connected to the comparator and configured to set said tunable fractional gain of the replication block during calibration.

15. The method of claim 14, wherein during the minimizing of the amplitude variation, the reference voltage is set to a value larger than a minimum of the amplitude variation, and wherein the controller is configured to determine the optimum value of the tunable fractional gain as an average of a lower gain corresponding to a first output transition of the comparator and a higher gain corresponding to a second output transition of the comparator.

16. The method of claim 12, wherein the current source is a MOS transistor.

17. The method of claim 16, wherein the current source is a PMOS transistor, wherein the supply voltage is applied at a source terminal of the PMOS transistor, wherein the control voltage is applied at a gate terminal of the PMOS transistor, and wherein the supply current is drawn from a drain terminal of the PMOS transistor.

18. The method of claim 13, wherein the tunable fractional gain is settable by a n-bit digital code, wherein n is a predetermined integer.

19. The method of claim 18, wherein the replication block comprises a replicating part that provides unitary gain and a fractional part that provides the tunable fractional gain, wherein the fractional part comprises n injection blocks each individually switchable by an individual bit in the n-bit digital code.

20. The method of claim 19, wherein the replicating part comprises a diode-connected PMOS transistor in series with two NMOS transistors forming a cascode, wherein each of the injection blocks comprises a current-source PMOS transistor in series with a switching PMOS transistor, a gate terminal of the switching PMOS transistor being connected to a corresponding the individual bit of the digital code and a drain terminal of the switching PMOS transistor being connected to a node of the cascode