LCD addressing system

Abstract

An addressing method and apparatus addresses faster responding liquid crystal display panels (LCDs) so that video rate, high information content LCDs having time constants on the order of 50 ms or less are perceived as having improved contrast by limiting peak voltage levels across the pixels. In a preferred embodiment, a first set of LCD electrodes is continuously driven with signals each comprising a train of pulses that are periodic in time, have a common period T, are independent of the information to be displayed, and are preferably orthonormal. Plural column signals are generated from the collective information states of the pixels defined by the overlap with a second electrode pattern. Each column signal is proportional to the sum, obtained by considering each pixel in the column, of the exclusive- or (XOR) products of the logic level of the amplitude of each row signal times the logic level of the information state of the pixel corresponding to that row. Hardware implementation comprises an external video source, a controller that receives and formats video data and timing information, a storage device that stores display data, a row signal generator, a column signal generator, and at least one LCD panel. Alternative embodiments provide circuits to reduce the number of column voltage levels required to generate a displayed image.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention pertains to a method and apparatus for addressing liquid crystal devices. More particularly the present invention pertains to a method and apparatus for addressing high information content, direct multiplexed, rms responding liquid crystal displays.

2. Discussion of the Prior Art

Examples of high information content direct multiplexed, rms-responding liquid crystal displays are systems that incorporate twisted nematic (TN), supertwisted nematic (STN), or superhomeotropic (SH) liquid crystal display (LCD) panels. In such panels, a nematic liquid crystal material is disposed between parallel-spaced, opposing glass plates or substrates. In one common embodiment, a matrix of transparent electrodes is applied to the inner surface of each plate, typically arranged in horizontal rows on one plate and vertical columns on the other plate to provide a picture element or "pixel" wherever a row electrode overlaps a column electrode.

High information content displays, such as those used in computer monitors, require large numbers of pixels to portray arbitrary information patterns in the form of text or graphic images. Matrix LCDs having 480 rows and 640 columns forming 307,200 pixels are commonplace, although it is expected that matrix LCDs may soon comprise several million pixels.

The optical state of a pixel, e.g. whether it will appear dark, bright or an intermediate shade, is determined by the orientation of the liquid crystal director within that pixel. In so-called rms responding displays, the direction of orientation can be changed by the application of an electric field across the pixel which field induces a dielectric torque on the director that is proportional to the square of the applied electric field. The applied electric field can be either a dc field or an ac field, and because of the square dependence, the sign of the torque does not change when the electric field changes sign. In the direct multiplexed addressing techniques typically used with matrix LCDs, the pixel sees an ac field which is proportional to the difference in voltages applied to the electrodes on the opposite sides of the pixel. Signals of appropriate frequency, phase and amplitude, determined by the information to be displayed, are applied to the row and column electrodes creating an ac electric field across each pixel which field places it in an optical state representative of the information to be displayed.

Liquid crystal panels have an inherent time constant .tau. which characterizes the time required for the liquid crystal director to return to its equilibrium state after it has been displaced away from it by an external torque. The time constant .tau. is defined by .tau.=.eta.d.sup.2 /K, where .eta. is an average viscosity of the liquid crystal, d is the cell gap spacing or pitch length and K is an average elastic constant of the liquid crystal. For a conventional liquid crystal material in a 7-10 .mu.m cell gap, typical for displays, the time constant .tau. is on the order of 200-400 ms.

If the time constant .tau. is long compared to the longest period of the ac voltage applied across the pixel, then the liquid crystal director is unable to respond to the instantaneous dielectric torques applied to it, and can respond only to a time-averaged torque. Since the instantaneous torque is proportional to the square of the electric field, the time-averaged torque is proportional to the time average of the electric field squared. Under these conditions the optical state of the pixel is determined by the root-mean-square or rms value of the applied voltage. This is the case in typical multiplexed displays where the liquid crystal panel time constant .tau. is 200-400 ms and the information is refreshed at a 60 Hz rate, corresponding to a frame period of 1/60 s or 16.7 ms.

One of the main disadvantages of conventional direct multiplex addressing schemes for high information content LCDs arises when the liquid crystal panel has a time constant approaching that of the frame period. (The frame period is approximately 16.7 ms). Recent technological improvements have decreased liquid crystal panel time constants (.tau.) from approximately 200-400 ms to below 50 ms by making the gap (d) between the substrates thinner and by the synthesis of liquid crystal material which has lower viscosities (.eta.) and higher elastic constants (K). If it is attempted to use conventional addressing methods for high information content displays with these faster-responding liquid crystal panels, display brightness and contrast ratio are degraded and in the case of SH displays, alignment instabilities are also introduced.

The decrease in display brightness and contrast ratio occurs in these faster panels because with conventional multiplexing schemes for high information content LCDs, each pixel is subjected to a short duration "selection" pulse that occurs once per frame period and has a peak amplitude that is typically 7-13 times higher than the rms voltage averaged over the frame period. Because of the shorter time constant .tau., the liquid crystal director instantaneously responds to this high-amplitude selection pulse resulting in a transient change in the pixel brightness, before returning to a quiescent state corresponding to the much lower rms voltage over the remainder of the frame period. Because the human eye tends to average out the brightness transients to a perceived level, the bright state appears darker and the dark state appears brighter. The degradation is referred to as "frame response". As the difference between a bright state and a dark state is reduced, the contrast ratio, the ratio of the transmitted luminance of a bright state to the transmitted luminance of a dark state, is also reduced.

Several approaches have been attempted to reduce frame response. Decreasing the frame period is one approach, but this approach is restricted by the upper frequency limit of the driver circuitry and the filtering effects on the drive waveforms caused by the electrode sheet resistance and the liquid crystal capacitance. Another approach is to decrease the relative amplitude of the selection pulse, i.e., decreasing the bias ratio, but this ultimately reduces the contrast ratio.

Other matrix addressing techniques are known which do not employ high-amplitude row selection pulses and therefore would not be expected to induce frame response in faster-responding panels. However, these techniques are applicable only to low information content LCDs where either there are just a few matrix rows or where the possible information patterns are somehow restricted, such as in allowing only one "off" pixel per column.

One advantage of the faster responding liquid crystal panels is that it makes video rate, high information content LCDs feasible for flat, "hang on the wall" TV screens. However, this advantage cannot be fully exploited with conventional direct multiplexing addressing schemes because of the degradation of brightness and contrast ratio and the introduction of alignment instabilities in these panels caused by frame response.

SUMMARY OF THE INVENTION

In accordance with the present invention, a novel addressing method and several preferred embodiments of an apparatus for addressing faster-responding, high-information content LCD panels are provided. The present addressing method and preferred embodiments provide a bright, high contrast, high information content, video rate display that is also free of alignment instabilities.

In the method of the present invention, the row electrodes of the matrix are continuously driven with row signals each comprising a train of pulses. The row signals are periodic in time and have a common period T which corresponds to the frame period. The row signals are independent of the information or data to be displayed and are preferably orthogonal and normalized, i.e., orthonormal. The term normalized denotes that all the row signals have the same rms amplitude integrated over the frame period while the term orthogonal denotes that if the amplitude of a signal applied to one row electrode is multiplied by the amplitude of a signal applied to another row electrode, then the integral of this product over the frame period is zero.

During each frame period T, multiple column signals are generated from the collective information state of the pixels in the columns. The pixels display arbitrary information patterns that correspond to pixel input data. The column voltage at any time t during frame period T is proportional to the sum obtained by considering each pixel in the column and adding the voltage of the row of that pixel at time t to the sum if the pixel is to be "off" and subtracting the voltage of the row of that pixel at time t from the sum if the pixel is to be "on". If the orthonormal row functions switch between only two voltage levels, the above sum may be represented as the sum of the exclusive- or (XOR) products of the logic level of each row signal at time t times the logic level of the information state of the pixel corresponding to that row.

When LCDs are addressed in the method of the present invention, frame response is drastically reduced because the ratio of the peak amplitude to the rms amplitude seen by each pixel is in the range of 2-5 which is much lower than with conventional multiplexing addressing schemes for high information content LCDs. For LCD panels that have time constants on the order of 50 ms, the pixels are perceived as having brighter bright states and darker dark states, and hence a higher contrast ratio. Alignment instabilities that are introduced by high peak amplitude signals are also eliminated.

Hardware implementation of the addressing method of the present invention comprises an external video source, a controller that receives and formats video data and timing information, a storage means for storing the display data, a row signal generator, a column signal generator, and at least one LCD panel.

The addressing method of the present invention may be extended to provide gray scale shading, where the information state of each pixel is no longer simply "on" or "off" but a multi-bit representation corresponding to the shade of the pixel. In this method each bit is used to generate a separate column signal, and the final optical state of the pixel is determined from a weighted average of the effect of each bit of the information state of the pixel.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagramatic view representing row and column addressing signals being applied to a LCD matrix in a display system according to this invention.

FIG. 2 is a partial cross-sectional view of the LCD matrix taken along line 2--2.

FIG. 3 is an example of a 32.times.32 Walsh function matrix utilized in connection with the invention of FIG. 1.

FIG. 4 represents Walsh function waveforms corresponding to the Walsh function matrix of FIG. 3.

FIG. 5 is a generalized form of the Walsh function matrix of FIG. 3.

FIG. 6 is a generalized representation of one embodiment of a circuit used to generate a pseudo-random binary sequence in accordance with the present invention.

FIG. 7 shows a voltage waveform across a pixel for several frame periods according to the addressing method of the present invention.

FIG. 8 represents the optical response of a pixel to the voltage waveform of FIG. 7.

FIG. 9 is a graph depicting the number of occurrences of D matches between the information vector and the Swift matrix vectors corresponding to one frame period for a 240 row display of this invention.

FIG. 10 is a block diagram of the apparatus of the present invention.

FIG. 11 is a flowchart of the basic operation of one embodiment of the apparatus of the present invention.

FIG. 12 is a block diagram of one embodiment of the present invention for addressing an LCD display system.

FIG. 13 is a block diagram of a row driver IC shown in FIG. 12.

FIG. 14 is a more detailed block diagram of the integrated column driver IC shown in FIG. 12.

FIG. 15 is a block diagram of one embodiment of the XOR sum generator shown in FIG. 14.

FIG. 16 is a block diagram of a second embodiment of the XOR sum generator.

FIG. 17 is a block diagram of the integrated driver of FIG. 14 with a third embodiment of the XOR sum generator.

FIG. 18 is a block diagram of a second embodiment of the present invention for addressing an LCD display system.

FIG. 19 is a block diagram showing the column signal computer of FIG. 18.

FIG. 20 is a block diagram showing an embodiment of the present invention of FIG. 14 incorporating gray shading.

FIG. 21 is a block diagram showing an embodiment of the present invention of FIG. 17 incorporating gray shading.

FIG. 22 is a block diagram showing an embodiment of the present invention of FIG. 19 incorporating gray shading.

FIG. 23 is a block diagram of one embodiment of the Swift function generator shown in FIG. 18.

FIG. 24 is a block diagram of a second embodiment of the Swift function generator which provides random inversion of the Swift functions.

FIG. 25 is a block diagram of a third embodiment of the Swift function generator which provides random reordering of the Swift functions.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

According to the principles of the present invention, a new addressing method for high information content, rms responding display systems is provided. In the addressing method of the present invention, the ratio of the magnitude of the peak voltage across an individual pixel during a frame period to the rms voltage averaged over one frame period is substantially lower than conventional addressing methods for high information content displays. In this way, the present addressing method improves display brightness and contrast ratio especially for displays using liquid crystal panels having time constants (.tau.) below 200 ms. Further, the addressing method eliminates the potentially damaging net dc component across the liquid crystal when averaged over a complete frame period so the displayed image may be advantageously changed every frame period. Still further, the present invention eliminates the occurrence of alignment instabilities.

Reference is now made to the drawings wherein like parts are shown with like reference characters throughout.

The addressing method may be best described in conjunction with a rms-responding liquid crystal display (LCD) depicted in FIGS. 1 and 2. A display system 10 is shown having a LCD display 12 preferably comprising a pair of closely spaced parallel glass plates 14 and 16, most clearly shown in FIG. 2. A seal 18 is placed around the plates 14 and 16 to create an enclosed cell having a gap 20 where gap 20 has a dimension (d) of between 4 .mu.m and 10 .mu.m , although both thinner and thicker cell gaps is known. Nematic liquid crystal material, illustrated at 21, is disposed in cell gap 20.

An NxM matrix of transparent conductive lines or electrodes is applied to the inner surfaces of plates 14 and 16. For illustration purposes, the horizontal electrodes shall be referred to generally as row electrodes 22.sub.1 -22.sub.N and the vertical electrodes as column electrodes 24.sub.1 -24.sub.M. In some instances, it will be necessary to refer to one or two specific electrodes. In those instances, a row electrode will be referred to as the i.sup.th electrode of the N row electrodes in the NxM matrix, e.g. 22.sub.i, where i=1 to N. Similarly, specific column electrodes will be referred to as the j.sup.th electrode of M column electrodes where j=1 to M. The same nomenclature will also be used to refer to some other matrix elements discussed below.

The electrode pattern shown in FIG. 1 comprises hundreds of rows and columns, and wherever a row and column electrode 22.sub.1 -22.sub.N and 24.sub.1 -24.sub.N overlap, for example where row electrode 22.sub.i overlaps column electrode 24.sub.j, a pixel 26.sub.ij is formed. It should be apparent that other electrode patterns are possible that may advantageously use the features of the addressing method to be described. By way of example, the electrodes may be arranged in a spiral pattern on one plate and in a radial pattern on the other plate, or, alternatively, they may be arranged as segments of an alpha-numeric display.

Each row electrode 22.sub.1 -22.sub.N of display 12 is driven with a periodic time-dependent row signals 28.sub.1 -28.sub.N, each having a common period T, known as the frame period. In the mathematical equations that follow, the amplitude of row signal 28.sub.i is referred to as F.sub.i (t). It is a sufficient condition for the addressing method of the present invention that row signals 28.sub.1 -28.sub.N be periodic and orthonormal over the frame period T.

The term "orthonormal" is a combination of "orthogonal" and "normal". In mathematical terms, normal refers to the property that row signals 28.sub.1 -28.sub.N are normalized so that all have the same rms amplitude. Orthogonal refers to the property that each row signal 28.sub.i when multiplied by a different row signal, 28.sub.i+3 for example, results in a signal whose integral over the frame period is zero.

The desired information state of pixels 26 can be represented by an information matrix I whose elements I.sub.ij correspond to the state of the pixel defined by the overlap of the i.sup.th row electrode with the j.sup.th column electrode. If, according to the desired information pattern, pixel 26.sub.ij is to be "on", then the pixel state is -1 and I.sub.ij =-1 (logic HIGH). If pixel 26.sub.ij is to be "off", then the pixel state is +1 and I.sub.ij =+1 (logic LOW). In FIG. 1, for example, the element I.sub.ij-2 of the information matrix refers to the pixel state of the pixel defined by the i.sup.th row and (j-2).sup.th column electrodes. This pixel state is set to a -1 and pixel 26 will be "on". An information vector I.sub.j may also be defined that is the j.sup.th column of the information matrix I. For the partial column j-2 illustrated in FIG. 1, the elements I.sub.ij of the information vector I.sub.j-2 are [-1, +1, -1, +1, +1] (for i=N-4 to N).

Each column electrode 24.sub.1 -24.sub.M has a column signal, such as, for example, signal 30.sub.j-2, applied thereto. The amplitude of column signal 30.sub.j-2 depends upon the information vector I.sub.j-2 that represents all of the pixels in the column and row signals 28.sub.1 -28.sub.N. Similarly, the amplitudes of all other column signals 30.sub.1 -30.sub.M depend on the corresponding information vector I.sub.j and row signals 28.sub.1 -28.sub.N. In the mathematical equations that follow, the amplitude of column signal 30.sub.j at time t for the j.sup.th column is referred to as G.sub.I.sbsb.j (t) where I.sub.j is the information vector for the j.sup.th column.

The voltage across pixel 26.sub.ij in the i.sup.th row and the j.sup.th column, U.sub.ij, is the difference between the amplitude F.sub.i (t) of the signal applied to row 22.sub.i and the amplitude G.sub.I.sbsb.j (t) of the signal applied to column 24.sub.j, that is

U.sub.ij (t)=F.sub.i (t)-G.sub.I.sbsb.j (t) (1

The root mean square value of the voltage, (i.e., the rms voltage) appearing across pixel 26.sub.ij is: ##EQU1## Substituting equation 1 into equation 2 yields: ##EQU2##

In the method of the present invention, column signals 30.sub.1 -30.sub.M are generated as a linear combination of all row signals 28.sub.1 -28.sub.N and coefficients of +1 or -1. The coefficients are the pixel states of the pixels in the column. Column signals 30.sub.1 -30.sub.M are therefore calculated for each column in the following manner: ##EQU3## where the I.sub.ij is the information state of the pixel in the j.sup.th column at the i.sup.th row and c is a constant of proportionality.

Substituting equation 4 into equation 3 and assuming that row signals 28.sub.1 -28.sub.N are orthonormal, i.e., ##EQU4## provides: ##EQU5##

For an "on" pixel, I.sub.ij =-1 and the "on" rms voltage across the pixel is therefore: ##EQU6##

For an "off" pixel, I.sub.ij =+1 and the "off" rms voltage across the pixel is therefore: ##EQU7##

The selection ratio R is the ratio of the "on" rms voltage to the "off" rms voltage that can occur across a pixel. That is: ##EQU8##

The maximum selection ratio can be found by substituting equations 7 and 8 into equation 9 and maximizing R with respect to the proportionality constant c. This results in: ##EQU9## Under some circumstances it may be advantageous to use a different value of c which does not maximize the theoretical selection ratio.

Substituting c from equation 11 into equation 8 and setting <U.sub.off >=1, i.e., normalizing all voltages with respect to the "off" rms voltage results in ##EQU10##

Substituting equation 11 into equation 4 gives the expression for the column voltage: ##EQU11##

Referring again to FIG. 1, where row signals 28.sub.1 -28.sub.N are analog signals that continuously vary in frequency and amplitude, equation 13 may be easily implemented in a variety of hardware embodiments. For example, display system 10 may incorporate a plurality of analog multipliers that multiply the amplitude F.sub.i (t) of each row signal 28.sub.i with the corresponding element of the information matrix I.sub.ij. An analog summer sums the output of each multiplier to provide a voltage to the corresponding column electrode 24.sub.1 -24.sub.M.

Those skilled in the art will recognize that a common signal H(t) could be superimposed on all row and column signals 28.sub.1 -28.sub.N and 30.sub.1 -30.sub.M to alter their outward appearances, but this does not change the principles of the present invention. This is so because, as equation 1 shows and as discussed earlier, it is the voltage difference across a pixel which determines its optical state and this difference is unaffected by superimposing a common signal on all row and column electrodes 22.sub.1 -22.sub.N and 24.sub.1 -24.sub.M.

Walsh Function Matrix Description

The generalized analog row signals 28.sub.1 -28.sub.N shown in FIG. 1 could be bilevel signals. Bilevel signals are advantageous because they are particularly easy to generate using standard digital techniques. Walsh functions are one example of bilevel, orthonormal functions that may be used as row addressing signals. Walsh row signals have the form:

F.sub.i (t)=F.multidot.W.sub.ik =F.multidot.W.sub.i (.DELTA.t.sub.k)(14) where the W.sub.ik are elements of a 2.sup.s .times.2.sup.s Walsh function matrix which are either +1 or -1. The index i corresponds to the i.sup.th row of the Walsh matrix as well as to the signal for the i.sup.th row of the display. The Walsh matrix columns correspond to a time axis consisting of 2.sup.s equal time intervals .DELTA.t over the frame period T, and the index k refers the k.sup.th time interval .DELTA.t.sub.k as indicated by the alternate notation in equation 14. The elements of the Walsh matrix are either +1 or -1, so that amplitude F.sub.i (t) assumes one of two values, i.e. either +F or -F over each of the time intervals .DELTA.t.sub.k.

Column signals 30.sub.1 -30.sub.M are obtained by substituting equation 14 into equation 13 to give: ##EQU12##

An example of a 32.times.32 (s=5) Walsh function matrix 40 is given in FIG. 3 and one period of the Walsh waves derived from corresponding rows of this matrix are shown in FIG. 4. At the end of each period the Walsh waves repeat. In the examples of FIG. 3 and 4 the Walsh functions have been ordered according to sequency with each succeeding Walsh wave having a sequency of one greater than the preceding Walsh wave. Sequency denotes the number of times each Walsh wave crosses the zero voltage line (or has a transition) during the frame period. The sequency has been noted in FIG. 4 to the left of each Walsh wave.

Walsh functions come in complete sets of 2.sup.s functions each having 2.sup.s time intervals. If the number of matrix rows N of display 12 is not a power of 2, then row signals 28.sub.1 -28.sub.N must be chosen from a Walsh function matrix having an order corresponding to the next higher power of two, that is 2.sup.s-1 <N>2.sup.s. The Walsh matrix must have an equal or greater number of rows than the display because the orthogonality condition prevents the same row signal 28.sub.i from being used more than once. For example, if N=480 (i.e., display 12 has 480 rows designated 22.sub.1 -22.sub.480), 480 different or unique row signals are selected from the set of 512 Walsh functions having 512 time intervals .DELTA.t. In this instance, s=9.

It should be apparent that it is possible for display 12 to be configured into several separately addressable screen portions. For example, if a 480 row display 12 were split into two equal portions, each portion of display 12 would be addressed as though it were a 240 row display. In this instance, N=240 and row signals 28.sub.1 -28.sub.N are selected from the set of 256 Walsh functions having 256 time intervals .DELTA.t.

The general form of the Walsh function matrix 42 is shown in FIG. 5. The elements W.sub.u,v (where u,v=0, 1, 2, . . . 2.sup.2-1) have the sequency ordering described above if each element is defined by the relation: ##EQU13## where subscript i refers to the i.sup.th digit of the binary representation of the decimal number u that denotes the row location or v that denotes the column location, i.e,

u.sub.decimal =(u.sub.s-1, u.sub.s-2, . . . u.sub.1, u.sub.0).sub.binary(17) and v.sub.decimal =(v.sub.s-1, v.sub.s-2, . . . v.sub.1, v.sub.0).sub.binary(18) where the u.sub.1 and v.sub.i are either 0 or 1; and ##EQU14##

If the sum in equation 16 is odd, then W.sub.u,v =-1 and if it is even, then W.sub.u,v =+1.

By using equations 16-19, any element in matrix 42 may be determined. For example, to determine the element in the 6.sup.th row and the 4.sup.th column (i.e., W.sub.5,3) in a Walsh matrix of order 8 (i.e., s=3), the operations indicated by equations 17 and 18 must be performed.

Specifically, since: u.sub.decimal =5=(101).sub.binary (20) then: u.sub.2 =1, u.sub.1 =0, u.sub.0 =1 (21) Similarly, v.sub.decimal =3=(011).sub.binary (22) and therefore: v.sub.2 =0, v.sub.1 =1, v.sub.0 =1 (23)

Substituting the above values for u as found in equation 21 into the appropriate equations 19 we obtain:

r.sub.0 (u)=u.sub.2 =1 r.sub.1 (u)=u.sub.2 +u.sub.1 =1+0=1 r.sub.2 (u)=u.sub.1 +u.sub.0 =0+1=1 (24) Combining equations 23 and 24, we obtain: v.sub.0 .multidot.r.sub.0 =1.multidot.1=1 v.sub.1 .multidot.r.sub.1 =1.multidot.1=1 v.sub.2 .multidot.r.sub.2 =0.multidot.1=0 (25) By summing the results (equation 16), it is found that .SIGMA.=2 and W.sub.5,3 =(-1).sup.2 =1.

The remaining elements of the matrix 42 may be determined by performing similar calculations. The above calculations may be performed in real time for each frame period or, preferably, the calculations may be performed once and stored in read-only memory for subsequent use. The Walsh function waves of matrix 42 form a complete set of orthonormal functions having the property: ##EQU15## where:

.delta..sub.ik =1 if i=k .delta..sub.ik =0 if i.noteq.k. (27)

Pseudo Random Binary Sequences

Another class of bilevel orthonormal row signals 28.sub.1 -28.sub.N may be obtained from a class of functions known as maximal length Pseudo Random Binary Sequences (PRBS) functions.

PRBS functions can be generated from the general shift register circuit 35 having a shift register 36 with exclusive- or feedback gates 37-39 shown in FIG. 6. Such a circuit can be practically implemented as such or it can be used as a model to generate the PRBS functions on a computer with the results stored in a ROM.

Starting with the shift register in some initial logic state designated by x.sub.1 -x.sub.s, clock pulses are applied to the register which successively shift the logic states of the various stages forward to the output stage and feed new logic states back to the input stage as determined by the connections to the exclusive- or gates. After a certain number of clock pulses, the shift register returns to its initial state and the binary sequence at the output stage starts to repeat. The length of the output sequence before it repeats is determined by the number and positions of the stages involved in the feedback loop. For an s-stage register, the maximum length L of the nonrepeating sequence is L=2.sup.s -1. Examples of feedback connections that generate maximal length sequences are summarized below.

TABLE 1______________________________________shift register feedback connections length of sequencestages s at stages L = 2.sup.s - 1______________________________________2 2,1 33 3,1 74 4,3 155 5,3 316 6,5 637 7,6 1278 8,6,5,4 2559 9,5 51110 10,7 102311 11,9 204712 12,11,8,6 409513 13,12,10,9 8191______________________________________

By considering the logic states as voltage levels, and substituting a +1 for the logic 0 and -1 for the logic 1, the exclusive- or operation is transformed to ordinary multiplication. We will adopt this latter definition of the logic states, as indicated in Table 2, throughout the remainder of this section.

TABLE 2______________________________________input 1 input 2 output______________________________________+1 +1 +1+1 -1 -1-1 +1 -1-1 -1 +1______________________________________

Consider the simple example of a 3 stage shift register with feedback connections at 3 and 1 as shown in Table 1. Starting from the initial logic state of -1, +1, +1 for the three stages, the subsequent states of the shift register can be determined from the recursive relations:

x.sub.1 (n+1)=x.sub.3 (n)x.sub.1 (n) x.sub.2 (n+1)=x.sub.1 (n) x.sub.3 (n+1)=x.sub.2 (n) (28) where x.sub.i (n) is the logic state of the i.sup.th stage in the register after application of the n.sup.th clock pulse assuming that the register is initialized with the first clock pulse. The state of the shift register after a first and subsequent clock pulses is summarized in Table 3. For this case, the state of the shift register and output binary sequence repeats after 7 cycles, i.e., x.sub.i (n)=x.sub.i (n+7). TABLE 3______________________________________clockpulse 1 2 3 4 5 6 7 8 9______________________________________x.sub.1 -1 -1 -1 +1 -1 +1 +1 -1 -1x.sub.2 +1 -1 -1 -1 +1 -1 +1 +1 -1x.sub.3 +1 +1 -1 -1 -1 +1 -1 +1 +1______________________________________

As another example, consider a 255 cycle maximal length PRBS function obtained from the following recursive equations based on an 8 stage shift register. Again, making the feedback connections recommended in Table 1 for s=8 gives: ##EQU16##

An LxL matrix of PRBS functions may be defined, where the first row is just the PRBS function itself, i.e, P.sub.1j =x.sub.s (j), and each subsequent matrix row is derived from the previous one by a cyclical shift of one cycle. Thus, the second row is P.sub.2j =x.sub.s (j+1) and the i.sup.th row is P.sub.ij =x.sub.s (j+i-1). Maximal length PRBS functions are interesting because of the property that they are nearly orthogonal to shifted versions of themselves i.e. ##EQU17## The expression for the column voltage using PRBS functions is similar to equation 15 for the Walsh functions except that the PRBS matrix elements P.sub.ik are substituted for the Walsh matrix elements W.sub.ik.

Swift Functions

As discussed above, analog row signals 28.sub.1 -28.sub.N of FIG. 1 may be implemented using waveforms generated with analog circuit elements. However, if row signals 28.sub.1 -28.sub.N are digital representations of Walsh or PRBS functions, hardware implementation of the present addressing method is possible using digital logic. Further, to improve display performance of display system 10, a fourth class of functions may be described which are called "Swift" functions. Swift functions may be derived, for example, from the Walsh functions or from the PRBS functions.

Swift functions based on Walsh functions:

A Swift matrix may be derived from Walsh matrix 42 by selecting N rows. Preferably the selected rows are derived from the set of sequency-ordered Walsh waves having the highest sequency.

One advantage of using the higher sequency rows is that the first row of Walsh matrix 42 need not be used. The first row is unique in that it is always +1 while all other rows have an equal number of positive amplitude and negative amplitude time intervals. Eliminating the first row eliminates the potentially damaging net dc component across the pixels of display 12 when the pixel voltage is averaged over a frame period. The average net dc component across a pixel is determined from the difference between the column voltage amplitude G.sub.I (t) and the row voltage amplitude F.sub.i (t) averaged over all the time intervals .DELTA.t of the period.

Since there is no potentially damaging net dc component when Swift waveforms S.sub.i are used, it is not necessary to invert row and column signals 28.sub.1 -28.sub.N, and 30.sub.1 -30.sub.M after every frame period. Further, with the present invention, display information may be advantageously changed after every frame period.

The Swift matrix may be further modified by randomly inverting a portion of the N rows in the Swift matrix. Inversion is accomplished by multiplying each element in the selected row by -1. In one preferred embodiment, a selected percentage that is preferably between 40% and 60% (e.g., 50%) of the rows in the Swift matrix is inverted. Thus for any time interval about half the rows receive a voltage of +F and the remaining rows receive a voltage of F F. For other time intervals, this proportion stays about the same except that different rows are selected for the +F and -F voltages.

Inverting the Swift waves in this way affects neither the orthogonal or normal property but eliminates the possibility that certain common information patterns would occur if, for example, stripes or checker-boards of various widths were displayed. Such contmon information patterns might produce an unusually high or low number of matches between information vector I.sub.j and the Swift function vector, and hence a large G.sub.I.sbsb.j voltage for certain time intervals.

The Swift matrix could also be modified by reordering the rows. This does not affect the orthonormal property, and under some circumstances could be used to reduce display streaking effects.

Swift functions based on maximal length PRBS:

Although maximal length PRBS functions are nearly orthogonal for large L, they still would induce crosstalk if used in this form for the matrix addressing of the present invention. To obtain theoretically orthogonal functions from the maximal length PRBS functions, a new set of Swift functions is created by adding an extra time interval to the PRBS functions and forcing the value of the Swift function to always be either +1 or -1 during this interval, i.e., P.sub.i(L+1) =+1 or -1. The resulting pulse sequence now has exactly 2.sup.s time intervals with the desired orthonormal properties: ##EQU18##

It is preferable to choose P.sub.i(L+1) =+1 in order to ensure that the functions will have no net dc value, i.e. ##EQU19##

Displays addressed with these Swift functions seem to give a more uniform appearance than displays addressed with Swift functions based on Walsh functions. This is so because the PRBS functions all have the same frequency content, and therefore the attenuation of the row waveforms by the RC load of the display is substantially the same for all rows.

In a similar manner to the Swift functions based on Walsh functions, preferably, about half of the rows of the present Swift matrix are inverted by multiplying these rows by -1.

Swift functions based on other orthonormal bilevel functions:

One skilled in the art will recognize that there is practically a limitless number of orthonormal bilevel functions that could be used for Swift functions. For example the Swift functions based on Walsh functions described above could be transformed into a completely different set of Swift functions simply by interchanging an arbitrary number of columns in the Swift matrix, a procedure which does not affect the orthonormal property. Of course the same holds true for the Swift functions based on maximal length PRBS functions. Swift functions could also be transformed by inverting an arbitrary number of columns, i.e. by multiplying them by -1. But this procedure would be less desirable because, even though the orthonormal property would be retained, this transformation generally would introduce a net dc voltage across the pixel which would necessitate inverting all drive levels every other frame period to remove it.

The expression for-the column voltage using Swift functions is similar to equation 15 derived for the Walsh functions except that the Swift matrix elements S.sub.ik are substituted for the Walsh matrix elements W.sub.ik.

Amplitude of the Column Signals:

Examination of the sum in equation 15 reveals that for any given time interval .DELTA.t.sub.k, the amplitude G.sub.I.sbsb.j (t) of column signal 30.sub.j is dependent upon the magnitude of the summation. The sum is the number of times an element in information vector I.sub.j matches an element in the Swift column vector S.sub.k (i.e., +1 matches +1 or -1 matches -1) minus the number of times there are mismatches (i.e., +1 and -1 or -1 and +1). Since the total number of matches and mismatches must add up to N, equation 15 becomes: ##EQU20## where D.sub.k is the number of matches between information vector I.sub.j and the k.sup.th column of the Walsh, Swift or PRBS function matrix. Thus the column voltage can be as large as +.sqroot.N.multidot.F or as small as -.sqroot.N.multidot.F depending upon whether there are N matches or zero matches. However, assuming that signs of the column elements in the matrix S.sub.ik are randomly distributed, as is true in the Swift matrix, the probability of all elements of information vector I.sub.j exactly matching or exactly mismatching the Swift matrix column S.sub.k is very low, especially when the number of rows N of display 12 is large, as is the case for a high information content display. The matching probability for certain Walsh matrix columns could be significantly higher for certain information patterns, and this is one reason why the use of a Swift function matrix is preferred.

The probability of D matches occurring P(D) can be expressed as ##EQU21## is the binomial coefficient giving the number of combinations of N distinct things taken D at a time, and is defined by: ##EQU22##

For large N and D, the binomial distribution may be approximated by the normal distribution. Thus, equation 34 becomes: ##EQU23##

It is clear from equation 36 that the most probable number of matches will occur for D=N/2 for which, referring to equation 33, the column voltage is zero. The more D deviates from the most probable value of N/2, the larger the magnitude of the column voltage, but this condition becomes less and less likely to occur. The largest column voltage that will occur, on the average, over one complete frame period (i.e., considering every time interval .DELTA.t.sub.k where 1.ltoreq.k.ltoreq.2.sup.s) can be obtained by solving equation 36 for the value of D' where P(D')=2.sup.-s and substituting this value into equation 33. The resultant most probable peak column signal voltage magnitude that will occur over a complete frame period, G.sub.peak, is then given by ##EQU24##

Since the voltage across the pixel is the difference between the row and column voltages (equation 1), the magnitude of the maximum voltage occurring across a pixel U.sub.peak is: ##EQU25## which is also the ratio of the magnitude of the peak voltage occurring during a frame period to the "off" rms voltage since <U.sub.off > has been normalized, i.e., <U.sub.off >=1. It is desirable that U.sub.peak be as close to <U.sub.off > as possible to minimize the effect of "frame response". By way of example, for a display having 240 multiplexed rows (N=240) s=8 and from equations 12 and 38, U.sub.peak /<U.sub.off >=2.39. Over many frame periods T, higher peak voltages are likely to occur. However, it is very unlikely that the ratio of U.sub.peak /<U.sub.off > will exceed 5:1. This ratio is dramatically lower than the value of 12.06 which results from the conventional addressing method for high information content LCDs. Optical Response to Swift Function Drive:

Referring now to FIGS. 7 and 8, a typical waveform U.sub.ij (t) across a pixel, such as pixel 26.sub.ij, of FIG. 1, is shown for several frame periods T for the case of Swift function drive where display 12 is a STN display. Waveform U.sub.ij (t) comprises a plurality of substantially low amplitude pulses such as pulses 31 and 32 that occur throughout the frame period. By providing the pixels with a plurality of low amplitude pulses throughout the entire frame period, frame response is substantially avoided. The resulting improvement in brightness and contrast ratio is especially noticeable for displays 12 having time constants below 200 ms.

FIG. 8 represents the optical response of pixel 26.sub.ij to waveform U.sub.ij (t). As shown by the superimposed designators 33 and 34, the transmitted luminance is relatively constant during frame periods FP1 and FP2 when pixel 26.sub.ij is in the "on" state and frame periods FP7 and FP8 when the pixel 26.sub.ij is in the "off" state. During frame periods FP1 and FP2, the transmitted luminance of pixel 26.sub.ij appears bright to an observer because the relatively constant luminance is the result of reduced frame response. Similarly, during frame periods FP7 and FP8, pixel 26.sub.ij appears darker than would a pixel exhibiting greater frame response.

Number of Levels Required for Column Signals:

From equation 33 it is seen that, for each time interval, G.sub.I.sbsb.j (.DELTA.t) assumes a discrete voltage level determined by the total number of matches, D, between corresponding elements in information vector I.sub.j and the Swift function vector. Since D generally can take any integral value between 0 and N, then there will be a maximum of N+1 possible voltage levels. However according to equations 34 and 36, not all values of D are equally probable, and more particularly values of D near N/2 are much more likely to occur than values of D near the extremes of 0 or N. Thus the actual number of levels required to practicably implement the addressing method of the present invention is considerably fewer than N+1. The minimum number of levels required would be those levels which, on the average, occur at least once during the frame period, i.e. after information vector I.sub.j has been compared with all 2.sup.s Swift vectors of the frame period. The average number of times that D matches will occur during one frame period, F(D), is determined by multiplying the 2.sup.s time intervals of the frame period by the probability function P(D) of equation 34 or 36. Thus the values of D that will occur at least once during the frame period are those values of D which satisfy the condition:

F(D)=2.sup.s P(D).gtoreq.1 (39)

Adding the number of different values of D that satisfy this condition gives the minimum number of voltage levels required. Making use of equation 36 results in: ##EQU26##

Substituting known values into equation 40 shows that only a small fraction of the maximum possible number of levels are actually needed for the addressing scheme of the present invention. For example, substituting N=240 and s=8 into equation 40 results in a minimum of 35 levels. This lies considerably below the maximum possible number of 241 levels.

In FIG. 9, F(D) is plotted versus the number of matches D in a 240 row matrix. The plot describes a bell-shaped curve showing that on the average there will be one occurrence of 103 matches for each frame period T. The number of occurrences increases to 13 at 120 matches and decreases again to one occurrence of 137 matches. In view of FIG. 9 a minimum of about 35 levels is required to substantially display a complete image during one frame rather than the 241 levels as would generally be expected.

Of course F(D)<1 does not mean that this value of D will never occur. It just means that more than one frame period must elapse before that value of D is likely to occur. F(D)=0.1 or 0.01, for example, implies that, on the average, 10 or 100 frame periods must elapse before that value of D is likely to occur. The very steep, exponential fall-off of the normal distribution curve insures that the number of levels required to practicably implement the addressing scheme of the present invention is not very much larger than the minimum number.

Reduction of number of levels for special Swift matrices:

With some embodiments of the present invention it may be advantageous to reduce the number of voltage levels presented to column electrodes 24.sub.1 -24.sub.M to the absolute minimum. This could be particularly important, for example, if column signals 30.sub.1 -30.sub.M were generated by the output of an analog multiplexer which is switched between a plurality of fixed voltage levels based on a digital input.

Some Swift matrices have the special property that the total number of +1 elements in any column vector is either always an even number or always an odd number. For example, in the 240 row Swift matrix based on the 256 row Walsh matrix with the 16 lowest sequency waves removed, every column has an even number of +1 elements. This result is preserved if the Swift matrix is modified further by inverting an even number of rows. If an odd number of rows is inverted then the total number of +1 elements in every column would be an odd number.

The number of voltage levels required by column signals 30.sub.1 -30.sub.M can be cut in half from the usual number by employing these special Swift matrices and forcing the number of +1 elements in information vector I.sub.j to be either always an even number or always an odd number. The number of levels is cut in half because under these conditions the number of matches, D, between Swift column vector S.sub.k and information column vector I.sub.j is forced to be either always an even number or always an odd number between 0 and N, inclusive. The possible combinations of column parity, information parity and row parity with their resulting match parity and number of reduced levels are summarized below in Table 4.

TABLE 4______________________________________no. of +1s number of resulting maximumin Swift +1s in in- number of number of numbercolumn formation matrix rows matches ofvector vector N D levels______________________________________odd odd odd odd (N + 1)/2odd odd even even (N + 2)/2even even odd odd (N + 1)/2even even even even (N + 2)/2even odd odd even N/2even odd even odd (N + 1)/2odd even odd even N/2odd even even odd (N + 1)/2______________________________________

Of course a general information vector I.sub.j is just as likely to have an even number of +1s is as an odd number of +1s. So in order to employ this level reduction scheme information vectors I.sub.1 -I.sub.M having the wrong parity must be changed to the right parity. One way to accomplish this would be to add an extra matrix row as a parity check and setting its corresponding column information elements to be either +1 or -1 to ensure the correct parity. The information pattern displayed on the last matrix row would necessarily be meaningless, but it could be masked off in order not to disturb the viewer. Or, alternatively, the last matrix row could be implemented as a "phantom" or "virtual" row which would exist electronically but not be connected to a real display row electrode.

Employing this level reduction scheme of the present invention to a 240 row display (N=240, s=8), for example, would reduce the minimum number of levels required from 35 to about 18.

Hardware Implementation and Description of Operation of the Present Invention

A Preferred General Embodiment:

Referring now to FIG. 10, a block diagram of one embodiment for implementing the present invention is shown. Although the embodiments are discussed using Swift functions, it is to be understood that other functions may be used.

Display system 10 comprises display 12, a column signal generator 50, a storage means 52, a controller 54, and a row signal generator 56. A data bus 58 electrically connects controller 54 with storage means 52. Similarly, a second data bus 60 connects storage means 52 with column signal generator 50. Timing and control bus 62 connects controller 54 with storage means 52, column signal generator 50 and row signal generator 56. A bus 68 provides row signal information from row signal generator 56 to column signal generator 50. Bus 68 also electrically connects row signal generator 56 with display 12. Controller 54 receives video signals from an external source (not shown) via an external bus 70.

The video signals on bus 70 include both video display data and timing and control signals. The timing and control signals may include horizontal and vertical sync information. Upon receipt of video signals, controller 54 formats the display data and transmits the formatted data to storage means 52. Data is subsequently transmitted from storage means 52 to column signal generator 50 via bus 60.

Timing and control signals are exchanged between controller 54, storage means 52, row signal generator 56 and column signal generator 50 along bus 62.

Referring now to FIG. 11, the operation of display system 10 will be described in conjunction with the embodiment shown in FIG. 10. FIG. 11 depicts a flowchart summary of the operating sequence or steps performed by the embodiment of FIG. 10.

As indicated at step 72, video data, timing and control information are received from the external video source by controller 54. Controller 54 accumulates a block of video data, formats the display data and transmits the formatted display data to storage means 52.

Storage means 52 comprises a first storage circuit 74 for accumulating the formatted display data transferred from controller 54 and a second storage circuit 76 that stores the display data for later use.

In response to control signals provided by controller 54, storage means 52 accumulates or stores the formatted display data (step 78) in storage circuit 74. Accumulating step 78 continues until display data corresponding to the N rows by M columns of pixels have been accumulated.

When an entire frame of display data has been accumulated, controller 54 generates a control signal that initiates transfer of data from storage circuit 74 to storage circuit 76 during transfer step 80.

At this point in the operation of display system 10, controller 54 initiates three operations that occur substantially in parallel. First, controller 54 begins accepting new video data (step 72) and accumulating a new frame of data (step 78) in storage circuit 74. Second, controller 54 initiates the process for converting the display data stored in storage circuit 76 into column signals 30.sub.1 -30.sub.M having amplitudes G.sub.I.sbsb.1 (.DELTA.t.sub.k)-G.sub.I.sbsb.M (.DELTA..sub.k) beginning at step 82. Third, controller 54 instructs row signal generator 56 to supply a Swift vector S(.DELTA.t.sub.k) for time interval .DELTA.t.sub.k to column signal generator 50 and to display 12. The third operation is referred to as the Swift function vector generation step 84 during which a Swift function vector S(.DELTA.t.sub.k) is generated or otherwise selectively provided to column signal generator 50. Swift function vector S(.DELTA.t.sub.k) is also provided directly to display 12.

As described above, N Swift functions S.sub.i are provided by row signal generator 56, one Swift function for each row. The N Swift functions S.sub.i are periodic in time and the period is divided into at least 2.sup.s time intervals, .DELTA.t.sub.k (where k=1 to 2.sup.s). Therefore, there are a total of N unique Swift functions S.sub.i, one for each row 22 of display 12, with each divided into 2.sup.s time intervals .DELTA.t.sub.k. A Swift function vector S(.DELTA.t.sub.k) is comprised of all N Swift functions S.sub.i at a specific time interval .DELTA.t.sub.k. Because there are at least 2.sup.s time intervals .DELTA.t.sub.k, there are at least 2.sup.s Swift function vectors S(.DELTA.t.sub.k). Swift function vector S(.DELTA.t.sub.k) are applied to rows 22 of display 12 by row signal generator 56 so that each element S.sub.i of Swift function vector S(.DELTA.t.sub.k) is applied to the corresponding row 22.sub.i of display 12 at time interval .DELTA.t.sub.k. Swift function vectors S(.DELTA.t.sub.k) are also used by column signal generator 50 in generating column signals 30.sub.1 -30.sub.M each having a corresponding amplitude G.sub.I.sbsb.1 (.DELTA.t.sub.k) through G.sub.I.sbsb.M (.DELTA.t.sub.k).

Display data stored in storage circuit 76 are provided to the column signal generator 50 at step 82. In this manner, an information vector I.sub.j is provided to column signal generator 50 such that each element I.sub.ij of information vector I.sub.j represents the display state of a corresponding pixel in the j.sup.th column. An information vector I.sub.j is provided for each of the M columns of pixels of display 12.

During column signal generation step 86, each information vector I.sub.j is combined with the Swift function vector S(.DELTA.t.sub.k) to generate a column signal 30.sub.j for the j.sup.th column during the k.sup.th time interval. Column signals 30.sub.1 -30.sub.M, each having amplitude G.sub.I.sbsb.j (.DELTA.t.sub.k), are generated for each of the M columns of display 12 for each time interval .DELTA.t.sub.k. When the amplitude G.sub.I.sbsb.j (.DELTA.t.sub.k) for all column signals 30.sub.1 -30.sub.M is calculated for time interval .DELTA.t.sub.k, all column signals 30.sub.1 -30.sub.M are presented, in parallel, to column electrodes 24.sub.1 -24.sub.M during time interval .DELTA.t.sub.k via bus 69. At the same time, the k.sup.th Swift function vector S(.DELTA.t.sub.k) is applied to row electrodes 22.sub.1 -22.sub.N of display 12 via bus 68 as indicated by step 88.

After column signals 30.sub.1 -30.sub.M have been presented, the k+1 Swift vector S(.DELTA.t.sub.k+1) is selected and steps 82-88 are repeated as indicated by the "no" branch of decision step 89. When all 2.sup.s Swift function vectors S(.DELTA.t.sub.k) have been combined with all information vectors I.sub.1 -I.sub.M, the "yes" branch of decision step 89 instructs controller to return to step 80 and transfer the accumulated frame of information vectors I.sub.1 -I.sub.M to storage means 76 (step 80) and the entire process is repeated.

Integrated Driver Embodiment:

Referring now to FIG. 12, another preferred embodiment of display system 10 is shown where storage means 52 (FIG. 10) is incorporated with column signal generator 50 in a circuit 90. Circuit 90 comprises a plurality of integrated driver integrated circuits (ICs) 91.sub.1 -91.sub.4. Row signal generator 56 is shown as comprising a Swift function generator 96 and a plurality of row driver integrated circuits (ICs) 98.sub.1 -98.sub.3. It should be apparent to one skilled in the art that the actual number of ICs 91.sub.1 -91.sub.4 and 98.sub.1 -98.sub.3 depends on the number of rows and columns of display 12.

Swift function generator 96 may include circuits, such as the circuit of FIG. 6, to generate Swift function vectors S(.DELTA.t.sub.k) for each time interval .DELTA.t.sub.k. Preferably, however, Swift function generator 96 comprises a read-only memory (ROM) having the Swift functions stored therein. Output bus 97 of Swift function generator 96 is connected to integrated driver ICs 91.sub.1 -91.sub.4 and to row driver ICs 98.sub.1 -98.sub.3.

Row driver ICs 98.sub.1 -98.sub.3 are preferably similar to the integrated circuit having the part number HD66107T, available from Hitachi America Ltd. In FIG. 12, each row driver IC 98.sub.1 -98.sub.3 is capable of driving 160 rows of display 12. For the case of N=480, three such row driver ICs 98.sub.1 -98.sub.3 are required. Row driver ICs 98.sub.1 -98.sub.3 are connected to row electrodes 22.sub.1 -22.sub.N of display 12 in a known manner as indicated by electrical interconnections 101.sub.1 -101.sub.3. Similarly, driver ICs 91.sub.1 -91.sub.4 are connected to column electrodes 24.sub.1 -24.sub.M in a known manner as indicated by electrical interconnections 104.sub.1 -104.sub.4.

As in the previous embodiment of FIG. 10, controller 54 receives video data and control signals via bus 70 from the external video source, formats the video data and provides timing control and control signals to integrated driver ICs 91.sub.1 -91.sub.4, Swift function generator 96 and row driver ICs 98.sub.1 -98.sub.3. Controller 54 is connected to integrated driver ICs 91.sub.1 -91.sub.4 by control bus 62 and formatted data bus 58. Controller 54 is also connected to row driver ICs 98.sub.1 -98.sub.3 and to Swift function generator 96 by control bus 62. Signals on control bus 62 cause Swift function generator 96 to provide the next sequentially following Swift function vector S(.DELTA.t.sub.k+1) to integrated driver ICs 91.sub.1 -91.sub.4 and to row driver ICs 98.sub.1 -98.sub.3.

Operation of row driver IC 98.sub.1 is now described in conjunction with FIG. 13. Although only row driver 98.sub.1 is described, it is understood that row driver ICs 98.sub.1 -98.sub.3 operate in a similar manner.

Row driver IC 98.sub.1 comprises an n-element shift register 110 electrically connected to an n-element latch 111 by bus 112. Latch 111 is in turn electrically connected to an n-element level shifter 113 by bus 114. Preferably, the n-element registers 110, latches 111, and level shifters 113 are large enough to accommodate all N rows of the display with one row driver IC, that is, n=N. However, a plurality of row driver ICs may be used so that the number of row driver ICs multiplied by n is at least N. In such case, a chip enable input is provided on control line 141 which allows multiple row driver ICs to be cascaded.

A Swift function vector S(.DELTA.t.sub.k) is serially shifted into shift register 110, element by element, from Swift function generator 96 on output bus 97 in response to a clock signal from controller 54 on Swift function clock line 143. When a complete Swift function vector S(.DELTA.t.sub.k) is shifted into shift register 110, the vector is transferred from the shift register 110 to latch 111 in response to a clock pulse provided by controller 54 on Swift function latch line 145. Clock line 143 and latch line 145, as is control line 141, are all elements of control bus 62.

The outputs of the n-element Swift function latch 111 are electrically connected to the corresponding inputs of an n-element level shifter 113, which translates the logical value of each element S.sub.i (.DELTA.t.sub.k) of the current Swift function vector S(.DELTA.t.sub.k) into either a first or a second voltage level, depending on the logical value of S.sub.i (.DELTA.t.sub.k). The resulting level-shifted Swift function vector, which now has values of either first or second voltages, is applied directly to the corresponding row electrodes 22.sub.1 through 22.sub.n for the duration of time interval .DELTA.t.sub.k via electrical connections 101.sub.1.

The design and operation of integrated driver ICs 91.sub.1 -91.sub.4 is more easily understood with reference to FIG. 14 where integrated driver IC 91.sub.1 is shown in greater detail. It is understood that integrated drivers 91.sub.2 -91.sub.4 operate in a similar manner.

Integrated driver IC 91.sub.1 receives formatted data from controller 54 on data bus 58 and control and timing signals on control and clock lines 116, 118, 123, 128, 140 and 142. Control and clock lines 116, 118, 123, 128, 140 and 142 are elements of bus 62. The Swift function vector S(.DELTA.t.sub.k) is received by IC 91.sub.1 from Swift function generator 96 on output bus 97.

Shift register 115 is adapted to receive the formatted data when enabled by control line 116. The data are transferred into register 115 at a rate determined by the clock signal provided by controller 54 on clock line 118. In the preferred embodiment, register 115 is m bits in length, so that the number of integrated driver ICs 91.sub. -91.sub.4 multiplied by m is at least M, the number of column electrodes 24.sub.1 -24.sub.M in display 12.

It should be understood that when register 115 is full with m bits (where m<M), the corresponding register 115 of integrated driver IC 91.sub.2 is enabled to receive formatted data. Similarly, the remaining integrated driver ICs 91.sub.3 and 91.sub.4 are sequentially enabled and formatted data is directed into appropriate registers. In this manner, one row of formatted data comprising M bits of formatted data are transferred from controller 54 to integrated driver ICs 91.sub.1-91.sub.4.

The contents of register 115 are then transferred in parallel to a plurality of N-element shift registers 119.sub.1 -119.sub.m via connections 125.sub.1 -125.sub.m in response to a write enable signal provided by controller 54 on control line 123. In the preferred embodiment, there are m shift registers in each integrated driver IC 91.sub.1 -91.sub.4 so that the number of integrated driver ICs 91.sub.1 -91.sub.4 multiplied by m provides a shift register corresponding to each of the M columns of display 12.

When registers 119.sub.1 -119.sub.m are full, each register 119.sub.1 -119.sub.m contains an information vector I.sub.j for the j.sub.th column. Each bit I.sub.ij of information vector I.sub.j corresponds to the display state of the i.sup.th pixel in the j.sup.th column. Information vector I.sub.j is then transferred to a corresponding latch 124.sub.1 -124.sub.m via bus 134.sub.1 -134.sub.m. One latch 124.sub.1 -124.sub.m is provided for each of the m column registers 119.sub.1 -119.sub.m. A latch enable signal on control line 128 initiates the transfer from registers 119.sub.1 -119.sub.m to the corresponding latch 124.sub.1 -124.sub.m. Latches 124.sub.1 -124.sub.m have N inputs and N outputs and store information vectors I.sub.1 -I.sub.m (that is, one column of N bits for each column j) that represent the display states of the pixels 26 of the corresponding column of display 12 for one frame period T.

The N outputs of latches 124.sub.1 -124.sub.m are electrically connected by buses 135.sub.1 -135.sub.m to corresponding exclusive- or (XOR) sum generators 130.sub.1 -130.sub.m at a first set of N inputs. Each XOR sum generator 130.sub.1 -130.sub.m has a second set of N inputs connected to corresponding outputs of an N-element latch 136 by bus 139. Latch 136 provides the Swift function vector S(.DELTA.t.sub.k) to each of the XOR sum generators 130.sub.1 -130.sub.m to enable generation of column signals 30.

Latch 136 has N inputs electrically connected via bus 137 to an N-element shift register 138. Output bus 97 connects Swift function generator 96 (FIG. 12) to register 138. In response to a Swift function clock 140 provided by controller 54, a Swift function vector S(.DELTA.t.sub.k) is sequentially clocked into register 138 via output bus 97 in a manner similar to that described above.

For each frame period, the first Swift function vector S(.DELTA.t.sub.1) is transferred, in response to a clock signal on control line 142, to latch 136. Following the transfer to latch 136, the second Swift function vector S(.DELTA.t.sub.2) is clocked into register 138 while the first Swift function vector S(.DELTA.t.sub.1) is combined by XOR sum generators 130.sub.1 -130.sub.m with information vectors I.sub.1 -I.sub.m in latches 124.sub.1 -124.sub.m to generate column signals 30.sub.1 -30.sub.M each having an amplitude G.sub.I.sbsb.j (.DELTA.t.sub.1). Column signals 30.sub.1 -30.sub.M are output on connections 104.sub.11 -104.sub.1m during the time interval .DELTA.t.sub.1. At the same time, the Swift function vector S(.DELTA.t.sub.k) is output on electrical connections 101.sub.1 -101.sub.3.

The process of transferring the Swift function vector S(.DELTA.t.sub.k) to latch 136, clocking in the next Swift function vector S(.DELTA.t.sub.k+1) into register 138 and combining the Swift function vector S(.DELTA.t.sub.k) with infomation vector I.sub.j and outputting the resulting column signals 30.sub.1 -30.sub.M to the column electrodes 24.sub.1 -24.sub.M and outputting the corresponding Swift function vector S(.DELTA.t.sub.k) to row electrodes 22.sub.1 -22.sub.N continues until all Swift function vectors S(.DELTA.t.sub.k) (i.e., until k=2.sup.s) have been combined with the current column information vectors I.sub.1 -I.sub.m held in latches 124.sub.1 -124.sub.m. At this point, a new frame of information vectors I.sub.1 -I.sub.M is transferred from registers 119.sub.1 -119.sub.m to latches 124.sub.1 -124.sub.m and the process is repeated for the next frame period T+1.

Exclusive-Or (XOR) Sum Generators:

There are various possible embodiments for implementing the XOR summation performed by XOR sum generators 130.sub.1 -130.sub.m which is also as a correlator. A first embodiment is shown in FIG. 15. For the purpose of explanation, only one XOR sum generator 130.sub.1, will be discussed, it being understood that all m XOR sum generators 130.sub.2 -130.sub.m operate in like manner.

The first set of inputs of XOR sum generator 130.sub.1 electrically connect, via bus 135.sub.11 -135.sub.1N, each output of latch 124.sub.1 to a corresponding input of N two-input XOR logic gates 144.sub.1 -144.sub.N. The second input of each XOR gate 144.sub.1 -144.sub.N is electrically connected to a corresponding bit of latch 136 by bus 139.sub.1 -139.sub.N.

The output of each XOR gate 144.sub.1 -144.sub.N is connected to a corresponding input of a current source, designated 146.sub.1 -146.sub.N. The outputs of current sources 146.sub.1 -146.sub.N are connected in parallel at a common node 148. The single input of a current-to-voltage converter 150 is also connected to node 148.

Current sources 146.sub.1 -146.sub.N are designed to provide either a first or second current output level depending on the combination of the inputs at each corresponding XOR gate 146.sub.1 -146.sub.N. If the output of the corresponding XOR gate is logic low, the first current output level is provided to common node 148. Similarly, if the output is logic high, the second current output level is provided. In this manner, the magnitude of current at node 148 is the sum of the current levels generated by the N current sources 146.sub.1 -146.sub.N. As discussed above, the magnitude of the current will depend on the number of matches D between the Swift vector S(.DELTA.t.sub.k) and information vector I.sub.j. Bus 145 routes power to each current source 146.sub.1 -146.sub.N.

Converter 150 converts the total current level at node 148 to a proportional voltage output. The voltage output of converter 150 is the amplitude G.sub.I.sbsb.j (.DELTA.t.sub.k) of column signal 30.sub.j for the j.sup.th column of display 12 at output 157.

In a slightly different embodiment, an A/D converter 156 converts the analog voltage at output 157 to a digital value representative of column signal 30.sub.j. The output of A/D converter 156 is provided on output 154.

As noted above, there are various embodiments for implementing the XOR sum generators 130.sub.1 -130.sub.m of FIG. 14. One such embodiment, shown in FIG. 16, eliminates the N current sources 146.sub.1 -146.sub.N by using a digital summing circuit 152. A multi-bit digital word, which is the digital representation of the sum of the outputs of XOR gates 144.sub.1 -144.sub.N, is output on bus 154. The digital representation is subsequently processed to generate column signal 30.sub.j. The width of digital word output by circuit 152 will depend on the number of rows in display 12 and the number of discrete voltage levels that will be needed to represent column signals 30.sub.1 -30.sub.M.

The digital word provided on bus 154 may be subsequently processed by a digital-to-analog converter (DAC) 155 shown in FIG. 16. DAC 155 produces an analog voltage at its output 157 that is proportional to the value of the digital word on bus 154. This may be done with a conventional digital-to-analog converter, or by using an analog multiplexer to select from a plurality of voltages.

Another embodiment of XOR sum generator 130.sub.1 -130.sub.N is shown in FIG. 17. In this embodiment register 138 and latch 136 are eliminated as are the N current sources 146.sub.1 -146.sub.N. Register 115 receives formatted data from controller 54 and registers 119.sub.1 -119.sub.m are filled in the manner described for the embodiment of FIG. 14. However, when registers 119.sub.1 -119.sub.m are filled, the contents are transferred in parallel via buses 134.sub.1 -134.sub.m to a second set of N-element shift registers 158.sub.1 -158.sub.m in response to a shift register enable signal provided by controller 54 on control line 128. As before, registers 119.sub.1 -119.sub.m are available to be updated with the next frame of formatted data.

The output of each register 158.sub.1 -158.sub.m is electrically connected to one input of a corresponding two-input XOR gate 164.sub.1 -164.sub.m. The second input of each XOR gate 164.sub.1 -164.sub.m are connected in parallel to output bus 97 of Swift function generator 96.

For each time interval .DELTA.t.sub.k, the contents of registers 158.sub.1 -158.sub.m are sequentially shifted out in response to a series of clock pulses on control line 163. Simultaneously, a Swift function vector S(.DELTA.t.sub.k) is presented, element by element to the second input of XOR gates 164.sub.1 -164.sub.m. The XOR product of each information vector I.sub.j times the Swift function vector S(.DELTA.t.sub.k) is therefore sequentially determined by XOR gates 164.sub.1 -164.sub.m.

To preserve the contents of registers 158.sub.1 -158.sub.m for the entire duration of frame period T, the bits shifted out of registers 158.sub.1 -158.sub.m are fed back in via buses 168.sub.1 -168.sub.m. Each information vector I.sub.j is recirculated until a new frame of information vectors I.sub.1 -I.sub.m are transferred from registers 119.sub.1 -119.sub.m at the start of the next frame period T+1. In this manner, each information vector I.sub.j is preserved for the duration of the respective frame period T.

The outputs of XOR gates 164.sub.1 -164.sub.m are electrically connected to the corresponding inputs of a plurality of integrators 170.sub.1 -170.sub.m. Integrators 170.sub.1 -170.sub.m integrate the output signals of XOR gates 164.sub.1 -164.sub.m during time interval .DELTA.t.sub.k. By integrating the plurality of pulses generated by XOR gates 164.sub.1 -164.sub.m, the output of integrators 170.sub.1 -170.sub.m will be at a voltage proportional to the sum of the XOR products. At the end of time interval .DELTA.t.sub.k, a corresponding plurality of sample and hold circuits 176.sub.1 -176.sub.m are enabled. After sample and hold circuits 176.sub.1 -176.sub.m have stored the amplitude G.sub.I.sbsb.j (.DELTA.t.sub.k) of column signals 30.sub.1 -30.sub.M, a pulse on initialize line 186 provided by controller 54, at the beginning of the next time interval .DELTA.t.sub.k+1, resets the integrators 170.sub.1 -170.sub.m to a common initial condition.

Sample and hold circuits 176.sub.1 -176.sub.m each comprise a pass transistor 180.sub.1 -180.sub.m controlled by a signal provided by controller 54 on control line 185. Transistors 180.sub.1 -180.sub.m permit the voltage output of integrators 170.sub.1 -170.sub.m to be selectively stored by capacitors 187.sub.1 -187.sub.m.

The sample and hold circuits 176.sub.1 -176.sub.m are followed by buffers 192.sub.1 -192.sub.m each of which applies a voltage signal to a corresponding one of column electrodes 24.sub.1 -24.sub.M of display 12 (FIG. 1). The voltage provided by buffers 192.sub.1 -192.sub.m is proportional to the sum of the XOR products. This voltage corresponds to the amplitude G.sub.I.sbsb.j (.DELTA.t.sub.k) of column signal 30.sub.j. Sample and hold circuits 176.sub.1 -176.sub.m hold the XOR sum for the entire duration of the next time interval .DELTA.t.sub.k+1 and therefore, buffers 192.sub.1 -192.sub.m apply the respective signals for the same duration. The Swift function vector S(.DELTA.t.sub.k) is applied to the row electrodes 22.sub.1 -22.sub.N by row drivers 98.sub.1 -98.sub.3 during time interval .DELTA.t.sub.k+1.

After the XOR sums for the first time interval .DELTA.t.sub.k are generated, the process is repeated for the next time interval .DELTA.t.sub.k+1 except that a new Swift function vector S(.DELTA.t.sub.k+1) is used for the XOR sum. The process is repeated until all Swift function vectors have been used in a single frame period T. At this point, a new frame period begins and the entire process repeats with a new frame of display information.

In the above embodiments of the XOR sum generators 130.sub.1 -130.sub.m, it may be advantageous to either limit the amplitude G.sub.I.sbsb.j (.DELTA.t.sub.k) of the generated column signals 30.sub.1 -30.sub.M or limit the total number of discrete levels column signals 30.sub.1 -30.sub.M may assume or both. Such limiting, while not significantly degrading the displayed image, may reduce the overall cost of display system 10.

Of course, the embodiment of the XOR sum generators 130.sub.1 -130.sub.m is not limited to those presented here, and those skilled in the art can envision many embodiments that perform the XOR sum generation function.

Column Signal Computer Embodiment:

A second embodiment for the addressing display system 10 is shown in FIG. 18. This embodiment comprises display 12, controller 54, row signal generator 56, and a column signal generator 90.

Row signal generator 56 comprises Swift function generator 96 and plurality of row driver ICs 98.sub.1 -98.sub.3. Row signal generator 56 has been previously discussed in conjunction with FIG. 12; however, its operation is again described in conjunction with the operation of display system 10 in FIG. 18.

Column signal generator 90 comprises a column signal computer 200 and a plurality of column driver ICs 202.sub.1 -202.sub.4. Column signal computer 200 is electrically connected to controller 54 by data bus 58 and to ICs 202.sub.1 -202.sub.4 by output bus 208. It should be apparent to one skilled in the art that the actual number of ICs 202.sub.1 -202.sub.4 and 98.sub.1 -98.sub.3 depends on the number of rows and columns of display 12.

Control bus 62 electrically connects controller 54 with column signal computer 200 and drivers 202.sub.1 -202.sub.4. Output bus 97 connects Swift function generator 96 with column signal computer 200. Output bus 97 also connects Swift function generator 96 with row drivers 98.sub.1 -98.sub.3.

Referring now to FIG. 19, column signal computer 200 is shown in greater detail. As in the integrated driver embodiment 90 of FIGS. 12 and 14, column signal computer 200 comprises an m-element shift register 115 that receives formatted data from controller 54 via data bus 58. Preferably, register 115 is capable of receiving a complete line of M bits (i.e., m=M where M is the number of column electrodes 24.sub.1 -24.sub.M of display 12) of formatted data. Data are transferred at a rate determined by the signal on clock line 118. A chip enable control line 116 provides the capability to interface multiple column signal computers 200 with controller 54 and display 12.

Column signal computer 200 also has a Swift function vector register 138 coupled to a latch 136 via bus 137. A Swift function vector S(.DELTA.t.sub.k) is shifted into register 138 via output bus 97 at a rate determined by the Swift function clock on line 140. As noted above, once a complete Swift function vector S(.DELTA.t.sub.k) has been shifted into register 138, its contents are shifted in parallel to latch 136 in response to a latch clock signal on control line 142. The outputs of latch 136 are connected to one set of inputs of XOR sum generator 130 via bus 139.

Column signal computer 200 further comprises a plurality of shift registers 119.sub.1 -119.sub.m electrically connected to shift register 115 via connections 125.sub.1 -125.sub.m. The contents of shift register 115 are transferred in parallel to shift registers 119.sub.1 -119.sub.m in response to a write enable signal provided by controller 54 on control line 123. Shift registers 119.sub.1 -119.sub.m are filled from shift register 115 in the same manner as was described for the embodiment shown in FIGS. 12 and 14.

The outputs of shift registers 119.sub.1 -119.sub.m are electrically connected to a plurality of latches 124.sub.1 -124.sub.m via buses 134.sub.1 -134.sub.m. The contents of shift registers 119.sub.1 -119.sub.m are transferred to latches 124.sub.1 -124.sub.m in response to a latch enable signal provided by controller 54 on control line 128. As was the case for the embodiment shown in FIGS. 12 and 14, this transfer is effected by controller 54 when shift registers 119.sub.1 -119.sub.m are full with one frame (or partial frame if m<M) of information vectors I.sub.1 -I.sub.m.

The N outputs of latches 124.sub.1 -124.sub.m are electrically connected to a bus 135 having N lines where each line connects the N outputs of latches 124.sub.1 -124.sub.m to a corresponding one of N inputs of exclusive- or (XOR) sum generator 130. The XOR sum generator 130 has a second set of N inputs connected to corresponding outputs of latch 136. As in the previous embodiments, latch 136 provides the Swift function vector S(.DELTA.t.sub.k) to XOR sum generator 130 to enable generation column signals 30.sub.1 -30.sub.M having amplitudes of G.sub.I.sbsb.1 (.DELTA.t.sub.k) through G.sub.I.sbsb.M (.DELTA.t.sub.k), respectively.

An m-element column enable shift register 218, connected to latches 124.sub.1 -124.sub.m via connections 127.sub.1 -127.sub.m, is used to sequentially enable the N outputs of latches 124.sub.1 -124.sub.m. A pulse provided on column enable in line 224 by the controller 54 in conjunction with a clock pulse on column enable clock line 226, also provided by controller 54, shifts an enable pulse into the first element of shift register 218. This enable pulse releases the contents of the first latch 124.sub.1 to bus 135, thus providing XOR sum generator 130 with information vector I.sub.1 of enabled latch 124.sub.1. The absence of an enable pulse in the remaining elements of shift register 218 forces the outputs of latches 124.sub.2 -124.sub.m to be in a high impedance state. Subsequent clock pulses on column enable clock line 226 provided by the controller 54 shift the enable pulse sequentially through the shift register 218, enabling the latches 124.sub.2 -124.sub.m and sequentially providing all column information vectors I.sub.1 -I.sub.m to XOR sum generator 130.

When information vector I.sub.j (j=1, for example) is provided, XOR sum generator 130 uses information vector I.sub.j in conjunction with the current Swift function vector S(.DELTA.t.sub.k) provided by latch 136 to generate column signal 30.sub.j of amplitude G.sub.I.sbsb.j (.DELTA.t.sub.k) as described above. Column signal 30.sub.j is output on output bus 208. Column signal 30.sub.j is released to column drivers 202.sub.1 -202.sub.4, which stores the amplitude G.sub.I.sbsb.j (.DELTA.t.sub.k) of column signal 30.sub.j in a shift register internal (not shown) to column drivers 202.sub.1 -202.sub.4 in response to control signals generated by controller 54.

As column information vectors I.sub.2 -I.sub.m are provided to XOR sum generator 130, new column signals 30.sub.2 -30.sub.m are generated and released to column drivers 202.sub.1 -202.sub.4 where each column signal 30.sub.2 -30.sub.m is stored in the internal shift register (not shown) of column drivers 202.sub.1 -202.sub.4. When all m latches 124.sub.1 -124.sub.m have been enabled by shift register 218 and hence all m information vectors I.sub.1 -I.sub.m stored in latches 124.sub.1 -124.sub.m have been provided to XOR sum generator 130, the m column signals 30.sub.1 -30.sub.m having amplitude G.sub.I.sbsb.1 (.DELTA.t.sub.k)-G.sub.I.sbsb.M (.DELTA.t.sub.k), respectively, will have been generated and released to column drivers 202.sub.1 -202.sub.4. At this point, the column drivers 202.sub.1 -202.sub.4 simultaneously apply all m column signals 30.sub.1 -30.sub.m to column electrodes 24.sub.1 -24.sub.m of the display 12 in response to a control signal from controller 54 for the duration of time interval .DELTA.t.sub.k+1. Substantially simultaneous with the application of the column signals 30.sub.1 -30.sub.m to column electrodes 24.sub.1 -24.sub.m, the Swift function vector S(.DELTA.t.sub.k) is applied to the row electrodes 22.sub.1 -22.sub.N by row drivers 98.sub.1 -98.sub.3.

While column signals 30.sub.1 -30.sub.m are being generated as described above for time interval .DELTA.t.sub.k, a new Swift function vector S(.DELTA.t.sub.k+1) is shifted into latch 138 in response to input signals provided by the Swift function generator 96 on Swift function output bus 97 and clock pulses on Swift function clock line 140. After column signals 30.sub.1 -30.sub.m have been generated and applied to the column electrodes 24.sub.1 -24.sub.m, the new Swift function vector S(.DELTA.t.sub.k+1) is transferred from register 138 to latch 136 in response to a pulse on Swift function latch line 142 and the process of generating and applying column signals 30.sub.1 -30.sub.m each having an amplitude of G.sub.I.sbsb.1 (.DELTA.t.sub.k+1) through G.sub.I.sbsb.M (.DELTA.t.sub.k+1) for time interval .DELTA.t.sub.k+1 is repeated as described above.

The above process is repeated for all 2.sup.s time intervals of the frame period, at which point a new frame of information vectors I.sub.1 -I.sub.m is transferred from shift registers 119.sub.1 -119.sub.m to latches 124.sub.1 -124.sub.m, and the entire process is repeated.

Additional Enhancements of the Various Embodiments of the Present Invention

Gray Scale Shading:

Additional embodiments of the present invention allow for addressing individual pixels to include intermediate optical states between the "on" and "off" state. In this way, different gray shades or hues may be displayed.

A first gray scale method for addressing display 12 uses a technique known as frame modulation, where several frame periods T of display information are used to control the duration of time that a pixel is "on" compared with the time a pixel is "off". In this manner, a pixel may be addressed to an intermediate optical state. For example, four frame periods may be used during which a pixel is "on" for two periods and "off" for the other two periods. If the time constant of the panel is long compared to several frame periods, then the pixel will assume an average intermediate optical state between fully "on" and fully "off". With the frame modulation method, the various embodiments of the present invention require no modification. Rather, the external video source must be capable of providing the proper on/off sequence for each pixel within the several frame periods so as to cause the pixels to be in the desired optical state.

If the time constant (.tau.) of display 12 is short compared to several frame periods T, the frame modulation method may be improved by decreasing the duration of the frame period T so as to increase the frame rate.

Referring now to FIG. 20, another gray scale embodiment is shown which uses a technique known as a pulse width modulation. In the embodiments described up to this point, the information state of a pixel is either "on" or "off", and the information states of the pixels are represented by the elements of information vectors I.sub.1 -I.sub.m as single bit words. However, in the present gray scale embodiment, the information state of a pixel may not only be "on" or "off", but may be a multitude of intermediate levels or shades between "on" and "off". The information states of the pixels in the present embodiment are therefore represented by elements of information vector I.sub.1 -I.sub.m as multi-bit words indicating the states of the pixels. Implementing the present embodiment requires that each storage element in storage means 52 (FIG. 10) be expanded from single bit words to multi-bit words of depth G. In typical applications, G will be between 2 and 8 and the number of displayed levels is 2.sup.G, including "on" and "off". It should be understood the notation I.sub.j when used in describing the gray scale embodiments includes all G bits of the multi-bit word. Additionally, the notation I.sub.jg refers to g.sup.th plane of bits of information vector I.sub.j.

In the present embodiment, each time interval at .DELTA.t.sub.k is subdivided into G smaller time intervals .DELTA.t.sub.kg of equal or differing duration, where the sum of the durations of subintervals .DELTA.t.sub.k1 through .DELTA.t.sub.kG is the same as the duration of time interval .DELTA.t.sub.k. Column signals 30.sub.1g -30.sub.mg are generated for each time subinterval .DELTA.t.sub.kg (where g=1 to G). In the preferred embodiment, the duration of .DELTA.t.sub.kg is approximately half the duration of .DELTA.t.sub.kg+1.

For any particular column (for instance j=7), column signal 30.sub.71 during time subinterval .DELTA.t.sub.k1 is generated using information vector I.sub.71 obtained by considering only the least significant bits of the multi-bit words of information vector 17. The next column signal 30.sub.72 is generated using information vector I.sub.72 obtained by considering only the second to the least significant bits of the multi-bit words of information vector I.sub.7 during the time subinterval .DELTA.t.sub.k2. Subsequent column signals 30.sub.7g -30.sub.7G are similarly generated until all G column signals 30.sub.71 -30.sub.7G have been generated.

The present embodiment is similar to the embodiment shown in FIG. 14. The differences being that the single bit storage element of shift register 227, shift registers 228.sub.1 -228.sub.m, and latches 229.sub.1 -229.sub.m are expanded to multi-bit word storage elements of depth G, and a plurality of N-element 1-of-G multiplexers 233.sub.1 -233.sub.m are added.

Operation of the present embodiment parallels that of the embodiment of FIG. 14 except that the display data are multi-bit words stored in a NxmxG information matrix I. Shift registers 228.sub.1 -228.sub.m are filled in the manner described above and the contents are transferred to latches 229.sub.1 -229.sub.m. Likewise, Swift function vectors S(.DELTA.t.sub.k) are shifted into register 138 and then transferred into latch 136.

Once information vectors I.sub.1 -I.sub.m are transferred to latches 229.sub.1 -229.sub.m in each of the G planes, multiplexers 233.sub.1 -233.sub.m, in response to a control signal provided by controller 54 on gray shade select line 298, sequentially present the G bits of column information vectors I.sub.1 -I.sub.m to XOR sum generators 130.sub.1 -130.sub.m, starting with the least significant bits during the time subinterval .DELTA.t.sub.k1 and ending with the most significant bits G during time subinterval .DELTA.t.sub.kG. In this way, G column signals 30.sup.j1 -30.sub.jG having amplitudes of G.sub.I.sbsb.j1 (.DELTA.t.sub.k1)-G.sub.I.sbsb.jG (.DELTA.t.sub.kG) are generated for each column electrode 24.sub.j (j=1 to m).

Similar expansions of the embodiments shown in FIGS. 17 and 19 may be implemented to provide pulse width modulated intermediate or gray scale shading. FIG. 21 shows an expansion of the embodiment of FIG. 17 that provides pulse width modulated intermediate shades. Registers 228.sub.1 -228.sub.m and 258.sub.1 -258.sub.m have been expanded from single bit to order G, and N-element 1-of-G multiplexers 235.sub.1 -235.sub.m have been added to select the proper significant bits of column information vectors I.sub.1 -I.sub.m.

FIG. 22 shows an embodiment similar to the embodiment of FIG. 19 that provides pulse width modulated capabilities for the display of intermediate shades. In this embodiment, a mXG-element shift register 227 receives formatted video data from bus 58. As described above, the elements of register 227 are transferred to a plurality of NXG shift registers 228.sub.1 -228.sub.m via buses 230.sub.1 -230.sub.m. Buses 230.sub.1 -230.sub.m are each one bit wide by G bits deep so that the contents of register 227 are transferred in parallel. The outputs of shift registers 228.sub.1 -228.sub.m are electrically connected to a plurality of latches 229.sub.1 -229.sub.m via buses 231.sub.1 -231.sub.m.

The N outputs of latches 229.sub.1 -229.sub.m are electrically connected to a bus 242 having a width of N and a depth of G so that each outputs of latches 229.sub.1 -229.sub.m is connected to an N-element 1-of-G multiplexer 233. Multiplexer 233 selects the proper significant bits (or plane) of column information vectors I.sub.1 -I.sub.m. The remainder of the operation is similar to that described above for FIG. 19.

The frame modulation and pulse width modulation methods may be advantageously combined to provide an even greater number of distinct intermediate optical states of pixels 26 of display system 10.

Swift Function Generator Embodiments:

Referring now to FIGS. 23-25, various embodiments of Swift function vector generator 96 of FIGS. 12 and 18 are suggested.

One basic embodiment, shown in FIG. 23, for Swift function generator 96 may comprise an address counter 302 and a Swift function generator ROM 304 connected by a control and address bus 306. As discussed above, control bus 62 electrically connects controller 54 and Swift function generator 96 while output bus 97 routes the outgoing Swift function vector S(.DELTA.t.sub.k) to the appropriate circuits.

In the embodiment of FIG. 23, a matrix of Swift functions S.sub.i are stored in ROM 304. In response to control signals supplied by controller 54 on bus 62, Swift function vector S(.DELTA.t.sub.k) are selected by the address signals on bus 306. The selected Swift function vector S(.DELTA.t.sub.k) is read out of ROM 304 onto output bus 97.

As was noted above, it is often desirable to randomly invert some rows of the Swift function matrix S to prevent display data consisting of regular patterns from causing unusually high amplitude (G.sub.I.sbsb.j (.DELTA.t.sub.k)) column signals 30.sub.1 -30.sub.M. Alternatively, it may be desirable to randomly reorder Swift functions S.sub.i to prevent streaking in the displayed image. Finally, it may be desirable to both randomly invert and randomly reorder the Swift functions S.sub.i for the best performance.

FIG. 24 shows another preferred embodiment of Swift function generator 96 which randomly inverts Swift functions S.sub.i. Controller 54 provides control signals on control bus 62 and more specifically on control line 307 and clock line 308 to a multiplexer 310, a random (or pseudo-random) generator 312 and an N-element shift register 314. Random generator 312 generates a random N-bit sequence of logic ones and logic zeros which are routed to a first input of multiplexer 310. Multiplexer 310, in response to control signals on control line 307, selects the input connected to generator 312 so that the random sequence of bits are shifted into register 314 in response to a clock signal on clock line 308. When register 314 is full, multiplexer 310 selects the input connected to the output of register 314 by bus 316. A new bit pattern is preferably provided from generator 312 for each frame period T.

The first element of register 314 is clocked out and provided to the first input of a two-input XOR gate 318. The output from register 314 is also recirculated back into register 314 through multiplexer 310 so that the random bit pattern is maintained for an entire frame period.

Each element stored in register 314 corresponds to one element of the Swift function vector S(.DELTA.t.sub.k) and is clocked, element by element, to the second input of XOR gate 318. The logical combination of corresponding elements from register 312 and the Swift function vector S(.DELTA.t.sub.k) by XOR gate 318 either inverts the Swift functions S.sub.i or passes the Swift functions S.sub.i without inversion.

The embodiment of FIG. 24 has been described for the random inversion of Swift function vectors S(.DELTA.t) that are transmitted on output bus 97 in a serial manner. However, one skilled in the art may expand the present embodiment by providing additional planes of circuitry by duplicating elements 310, 312, 314 and 318. In this manner, a plurality of Swift function vector S(.DELTA.t) bits may be inverted and transmitted in parallel.

Referring now to FIG. 25, a further embodiment for the Swift function generator 96 is shown that randomly (or pseudo-randomly) changes the order of the Swift functions S.sub.i of matrix 40. Depending on the type of Swift functions used, it may be desireable to randomize the order every few frame periods. Preferably it is desireable to randomize the order every frame period T.

The order is changed by an address randomizer 320 that remaps the address supplied from address counter 302 every frame period T. In this manner, the order in which the Swift functions S.sub.i are selected may be randomly changed. Address randomizer 320 is connected to address counter 302 by bus 322 and to ROM 304 by bus 324.

In another embodiment (not shown), the embodiments of FIGS. 24 and 25 are combined in a single circuit.

It should be apparent that the invention may be embodied in other specific forms without departing from its spirit or essential characteristics. Liquid crystal displays, for example, form only part of the broader category of liquid crystal electro-optical devices, such as print heads for hard copy devices and spatial filters for optical computing, to which this invention could be applied. The described embodiments are to be considered in all respects only as illustrated and not restrictive and the scope of the invention is, therefore, indicated by the appended claims.

Claims

1. A system for addressing an rms-responding display of a type that displays arbitrary information patterns, the display including overlapping first and second electrodes positioned on opposite sides of an rms-responding material to define an array of pixels that display arbitrary information patterns corresponding to pixel input data, the system comprising:

a first signal generator for generating and applying a set of first signals to corresponding first electrodes during a frame period that is divided into time intervals, the first signals having amplitudes, and each one of the first signals in the set causing multiple selections of its corresponding first electrode, the multiple selections taking place during different ones of the time intervals and being distributed over the frame period;

each of the first signals provides a number of the time intervals over the frame period that is less than an expotential function of the number of first electrodes;

storage sites for storing the pixel input data;

a second signal generator for generating second signals, the second signal generator including a correlator for correlating the first signals and the stored pixel input data to determine the second signals, and each of the second signals having an amplitude at a particular time interval during the frame period, the amplitude being determined by both the amplitudes of more than one of the first signals causing selections at the particular time interval and the corresponding pixel input data;

the amplitudes of multiple second signals being determined by contributions of the multiple selections by each one of the first signals in the set that are distributed over the frame period so as to reduce the frame response of the display; and

output connection means for applying all the second signals to the second electrodes substantially simultaneously to the application of all the first signals to the first electrodes.

2. The addressing system of claim 1 in which the first signal generator includes first signal storage sites that store the first signals.

3. The addressing system of claim 2 in which the first signal storage sites comprise a read only memory.

4. The addressing system of claim 1 in which the first signal generator includes a Pseudo Random Binary Sequence generator.

5. The addressing system of claim 1 in which the correlator performs a dot product of the first signals and the pixel input data.

6. A system for addressing an rms-responding display of a type that displays arbitrary information patterns, the display including overlapping first and second electrodes positioned on opposite sides of an rms-responding material to define an array of pixels that display arbitrary information patterns corresponding to pixel input data, the system comprising:

a first signal generator for generating and applying a set of first signals to corresponding first electrodes during a frame period that is divided into time intervals, the first signals having amplitudes, and each one of the first signals in the set causing multiple selections of its corresponding first electrode, the multiple selections taking place during different ones of the time intervals and being distributed over the frame period;

each of the first signals provides a number of the time intervals over the frame period that is less than an exponential function of the number of first electrodes;

storage sites for storing the pixel input data; and

a second signal generator for generating second signals and output connection means for applying all the second signals to the second electrodes substantially simultaneously to the application of all the first signals to the first electrodes, the second signals having amplitudes and the second signal generator including a correlator for correlating the first signals and the stored pixel input data to determine the second signals so that contributions of the multiple selections by each one of the first signals in the set to determinations of the amplitudes of multiple second signals are distributed over the frame period so as to reduce the frame response of the display, the correlator including data transfer signal means for writing into and reading from the storage sites sets of pixel input data, each of the sets of pixel input data corresponding to pixels defined by a different one of the second electrodes; multiplying means for multiplying the first signals and the sets of pixel input data to derive product signals; and summing means for summing the product signals derived for each set of pixel input data to produce the second signals for delivery to the output connection means.

7. The addressing system of claim 6 in which the multiplying means accomplishes multiplication by an exclusive- or logic operation.

8. The addressing system of claim 6 in which the storage sites reside in a memory device having sufficient storage capacity to store sets of the pixel input data, and the data transfer signal means provides data read signals to the memory device to selectively provide the sets of pixel input data to the multiplying means.

9. The addressing system of claim 8, further comprising:

a multiplier input shift register that cooperates with the memory device to present the sets of pixel input data to the multiplying means and sequentially produce the second signals; and

second signal storage sites that store the second signals and thereby permit a simultaneous application of the second signals by the output connection means to the second electrodes.

10. The addressing system of claim 9 in which the multiplying means includes a single multiplying device that receives all of the first signals in the set of first signals and all of the sets of pixel input data to derive the product signals.

11. The addressing system of claim 9 in which the memory device includes multiple shift register devices, each of the shift register devices including a shift register and a latch circuit, the shift register receiving in serial manner a set of pixel input data and the latch circuit storing the pixel input data received by the shift register, the latch circuit receiving the data read signals to selectively provide one of the sets of pixel input data to the multiplying means.

12. The addressing system of claim 8 in which

the multiplying means and summing means comprise respective plural multiplying devices and summing devices and in which the memory device comprises multiple shift register devices, each of the shift register devices being associated with a different pair of the multiplying and summing devices to produce a second signal; and

the data read signals cause simultaneous production of the second signals for application to the second electrodes.

13. The addressing system of claim 1 in which the first signals are derived from a set of Walsh functions.

14. A system for addressing rms-responding information storage elements that store arbitrary information patterns, the system including overlapping first and second electrodes positioned on opposite sides of an rms-responding material to define an array of information storage elements that store arbitrary information patterns corresponding to information input data, the system comprising:

a first signal generator for generating and applying a set of first signals to corresponding first electrodes during a frame period that is divided into time intervals, the first signals having amplitudes, and the amplitude of each one of the first signals in the set including two nonzero signal levels causing multiple selections of its corresponding first electrode, the multiple selections taking place during different ones of the time intervals and being distributed over the frame period;

each of the first signals provides a number of the time intervals over the frame period that is less than an exponential function of the number of first electrodes;

storage sites for storing the information input data;

a second signal generator for generating second signals, the second signal generator including a correlator for correlating the first signals and the stored information input data to determine the second signals, and each of the second signals having an amplitude at a particular time interval during the frame period, the amplitude being determined by both the amplitudes of more than one of the first signals causing selections at the particular time interval and the corresponding information input data;

the amplitudes of multiple second signals being determined by contributions of the multiple selections by each one of the first signals in the set that are distributed over the frame period so as to reduce the frame response of the system; and

output connection means for applying all the second signals to the second electrodes substantially simultaneously to the application of all the first signals to the first electrodes.

15. The addressing system of claim 14 in which the first signals are derived from a set of Walsh functions.

16. The addressing system of claim 15 in which the set of Walsh functions is sequency-ordered.

17. The addressing system of claim 16 in which the sequency-ordered set of Walsh functions is of the highest sequency.

18. The addressing system of claim 14 in which the first signals are derived from a set of pseudo random functions.

19. A system for addressing rms-responding information storage elements that store arbitrary information patterns, the system including overlapping first and second electrodes positioned on opposite sides of an rms-responding material to define an array of information storage elements that store arbitrary information patterns corresponding to information input data, the system comprising:

a first signal generator for generating and applying a set of first signals to corresponding first electrodes during a frame period that is divided into time intervals, the first signals having amplitudes, and each one of the first signals in the set causing multiple selections of its corresponding first electrode, the multiple selections taking place during different ones of the time intervals and being distributed over the frame period;

each of the first signals provides a number of the time intervals over the frame period that is less than an expotential function of the number of first electrodes.

storage sites for storing the information input data; and

a second signal generator for generating second signals and output connection means for applying all the second signals to the second electrodes substantially simultaneously to the application of all the first signals to the first electrodes, the second signals having amplitudes and the second signal generator including a correlator for correlating the first signals and the stored information input data to determine the second signals so that contributions of the multiple selections by each one of the first signals in the set to determinations of the amplitudes of multiple second signals are distributed over the frame period so as to reduce the frame response of the system, the correlator including data transfer signal means for writing into and reading from the storage sites sets of information input data, each of the sets of information input data corresponding to information storage elements defined by a different one of the second electrodes; multiplying means for multiplying the first signals and the sets of information input data to derive product signals; and summing means for summing the product signals derived for each set of information input data to produce the second signals for delivery to the output connection means.

20. A system for addressing rms-responding information storage elements that store arbitrary information patterns, the system including overlapping first and second electrodes positioned on opposite sides of an rms-responding material to define an array of information storage elements that store arbitrary information patterns corresponding to information input data, the system comprising:

a first signal generator for generating and applying a set of first signals to corresponding first electrodes during a frame period that is divided into time intervals, the first signals having amplitudes, and each one of the first signals in the set causing multiple selections of its corresponding first electrode, the multiple selections taking place during different ones of the time intervals and being distributed over the frame period;

each of the first signals provides a number of the time intervals over the frame period that is less than an exponential function of the number of first electrodes;

storage sites for storing the information input data, the storage sites residing in a memory device that stores sets of information input data, and each of the sets of information input data corresponding to information storage elements defined by a different one of the second electrodes; and

a second signal generator for generating second signals and output connection means for applying all the second signals to the second electrodes substantially simultaneously to the application of all the first signals to the first electrodes, the second signals having amplitudes and the second signal generator including a correlator for correlating the first signals and the stored information input data to determine the second signals so that contributions of the multiple selections by each one of the first signals in the set to determinations of the amplitudes of multiple second signals are distributed over the frame period so as to reduce the frame response of the system, and the correlator including multiplying means for multiplying the first signals and the sets of information input data to derive product signals; summing means for summing the product signals derived for each set of information input data to produce the second signals for delivery to the output connection means; a multiplier input shift register that cooperates with the memory device to present the sets of information input data to the multiplying means and sequentially produce the second signals; and second signal storage sites that store the second signals and thereby permit a simultaneous application of the second signals by the output connection means to the second electrodes.

21. The addressing system of claim 14 in which the correlator performs a dot product of the first signals and the information input data.

22. The addressing system of claim 21 in which the multiplying means accomplishes multiplication by an exclusive- or logic operation.

23. The addressing system of claim 14 in which the amplitudes of the first signals have in a time order discrete values associated with each of the time intervals, the addressing system further comprising means for arranging the time order of the amplitude values of the first signals to reduce crosstalk among the information storage elements in the array.

24. The addressing system of claim 14, further comprising means for inverting the amplitudes of a certain proportion of the first signals to reduce the maximum amplitudes of the second signals.

25. The addressing system of claim 24 in which the proportion of inverted first signals is between about 40% and 60%.

26. In a system for displaying data on an rms-responding display in which overlapping row and column electrodes positioned on opposite sides of an rms-responding material provide an array of pixels, each of the pixels having a pixel information state, and which receives a video signal having control components and data information components, the data information components representing the data to be displayed by the pixels, an apparatus for addressing the display, comprising:

a row signal generator for generating and applying a set of row signals to corresponding row electrodes during a common frame period that is divided into time intervals, the row signals having amplitudes, and each one of the row signals in the set causing multiple selections of the row electrode to which the one of the row signals corresponds, the multiple selections taking place during different ones of the time intervals and being distributed over the common frame period;

each of the row signals provides a number of the time intervals over the common frame period that is less than an exponential function of the number of row electrodes;

a column signal generator for generating and applying a column signal to each of the column electrodes;

storage means for receiving and storing the data information components;

a controller in communication with the row signal generator, column signal generator, and storage means, the controller receiving the video signal and providing the data information components thereof to the storage means and the control components thereof to the row signal generator, column signal generator, and storage means; and

the column signal generator communicating with the storage means to receive the data information components according to the control components, communicating with the row signal generator to receive the row signals according to the control components, and during the common frame period generating for each column a column signal having an amplitude that is derived from both the row signals causing selections and the pixel information states of the corresponding pixels;

the amplitudes of multiple column signals being derived by contributions of the multiple selections by each one of the row signals in the set that are distributed over the frame period so as to reduce the frame response of the display.

27. The system of claim 26 in which the amplitude of each column signal is proportional to the sum of the products of the amplitude of each row signal causing a selection times the pixel information state of the corresponding pixel.

28. The system of claim 26 in which the row signals are normalized to a common value.

29. The system of claim 26 in which the row signals are orthogonal to one another.

30. The system of claim 26 in which the amplitudes of at least some of the row signals include two nonzero signal levels to effect the multiple selections of the corresponding row electrodes.

31. The system of claim 30 in which the amplitude of each one of the column signals is proportional to a sum of exclusive- or products of logic levels representative of the two nonzero signal levels of the row signals and logic levels representative of the pixel information states of pixels defined by the corresponding row electrodes.

32. The system of claim 26 in which the row signals have logic levels, the pixel information states comprise logic states, and the amplitude of each column signal is proportional to the sum of exclusive- or products of the logic level of each row signal causing a selection at a particular time interval and the logic state of the corresponding pixel in the column.

33. In a system for displaying data on an rms-responding display in which overlapping row and column electrodes positioned on opposite sides of an rms-responding material provide an array of pixels, each of the pixels having a pixel logic state, and which receives a video signal having control components and data information components, the data information components representing the data to be displayed by the pixels, an apparatus for addressing the display, comprising:

a row signal generator for generating a set of row signals representing orthonormal function vectors and applying the row signals to corresponding row electrodes during a common frame period that is divided into time intervals, the row signals having logic levels and each one of the row signals in the set causing multiple selections of the electrode to which the one of the row signals corresponds, the multiple selections taking place during different ones of the time intervals and being distributed over the common frame period;

each of the row signals provides a number of the time intervals over the common frame period that is less than an exponential function of the number of row electrodes;

a column signal generator for generating and applying a column signal to each of the column electrodes;

storage means for receiving and storing the data information components;

a controller in communication with the row signal generator, column signal generator, and storage means, the controller receiving the video signal and providing the data information components thereof to the storage means and the control components thereof to the row signal generator, column signal generator, and storage means;

the column signal generator communicating with the storage means to receive the data information components according to the control components, communicating with the row signal generator to receive according to the control components the orthonormal function vectors in sequence to generate multiple column signals, and during the common frame period generating for each column a column signal having an amplitude that is proportional to the sum of exclusive- or products of the logic level of each row signal causing a selection at a particular time and the logic state of the corresponding pixel;

the amplitudes of multiple column signals being generated by contributions of the multiple selections by each one of the row signals in the set that are distributed over the frame period so as to reduce the frame response of the display; and

the row signal generator transmitting the orthonormal function vectors to the row electrodes for application to the row electrodes substantially simultaneously with the application of the column signals to the column electrodes.

34. The system of claim 33 further comprising means for periodically changing the order of transmission of the orthonormal function vectors.

35. The system of claim 33 further comprising means for randomly inverting a plurality of the orthonormal functions prior to their transmission.

36. The system of claim 35 in which the inverted plurality of orthonormal functions is approximately 50% of the orthonormal functions.

37. The system of claim 33 in which the column signal generator further comprises:

at least one exclusive- or sum generator having a plurality of exclusive- or logic gates, a corresponding plurality of electrical current sources each having a control terminal and having an output connected to a common node, and a current-to-voltage converter;

latching means for receiving and latching the orthonormal function vectors;

each exclusive- or sum generator having a first input connected to the latching means, a second input connected to the storage means, and an output connected to the control terminal of one of the current sources;

each of the current sources being capable of producing first or second current levels in response to a signal level present on the control terminal; and

the current-to-voltage converter having an input connected to the common node and an output connected to one of the column electrodes, the converter being adapted to convert the current at the common node to a proportional voltage, and thereby produce one of the column signals, and to provide the voltage to the one of the column electrodes so that all of the column signals are applied to corresponding column electrodes substantially simultaneously with the application of corresponding row signals to the row electrodes.

38. The system of claim 33 in which the exclusive- or products are generated for each column of the display by a plurality of exclusive- or gates whose outputs are summed by a digital summing network so as to provide a digital representation that is proportional to the number of matching elements of the orthonormal function vector and the logic states of the selected pixels in each column, and in which the system further comprises converting means for converting the digital representation to an analog signal.

39. The system of claim 38 in which the converting means comprises a digital-to-analog converter.

40. The system of claim 38 in which the converting means comprises an analog multiplexer that provides a selected one of a plurality of discrete voltage levels to the column electrodes.

41. The system of claim 33 in which the column signal generator further comprises:

at least one exclusive- or sum generator having a plurality of exclusive- or logic gates, a corresponding plurality of electrical current sources each having a control terminal and having an output connected to a common node, a current-to-voltage converter, and column driver circuits;

latching means for receiving and latching the orthonormal function vectors;

each exclusive- or generator having a first input connected to the latching means, a second input connected to the storage means, and an output connected to the control terminal of one of the current sources;

each of the current sources being capable of producing first or second current levels in response to a signal level present on the control terminal; and

the current-to-voltage converter having an input connected to the common node and an output connected to the column driver circuits, the converter being adapted to convert the current at the common node to a proportional voltage and thereby produce one of the column signals and to provide the voltage to the column driver circuits;

whereby each column signal is sequentially generated and all of the column signals are applied to a corresponding column electrode substantially simultaneously with the application of corresponding row signals to the row electrodes.

42. The system of claim 33 in which the column signal generator further comprises:

an exclusive- or gate having an input adapted to receive in sequence the logic states of selected pixels in one of the columns, an input adapted to receive in sequence the orthonormal function vector elements representing row signals causing selections, and an output adapted to generate a sequence of pulses;

an integrator circuit having an input and an output and being capable of integrating a sequence of pulses received at its input from the exclusive- or gate to provide an output voltage that is proportional to the number of pulses received in a selected time interval;

a sample and hold circuit having an input and an output, the input connected to the output of the integrator circuit, the output of the integrator being adapted for selective sampling and retention for a selected time interval;

an output buffer having an input connected to the output of the sample and hold circuit and a plurality of outputs connected to the column electrodes so that a retained output may be substantially simultaneously provided to the column electrodes for a selected time interval.