Patent Application
20120013589
1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) and circuit architecture thereof, and more particularly, to an LCD improving power and signal supplies for source driver chips and circuit architecture thereof.
2. Description of Prior Art
With a rapid development of monitor types, novel and colorful monitors with high resolution, e.g., liquid crystal displays (LCDs), are indispensable components used in various electronic products such as monitors for notebook computers, personal digital assistants (PDAs), digital cameras, and projectors. The demands for the novel and colorful monitors have increased tremendously.
There are three ways to connect substrates and driver ICs during an LCD manufacturing process: a tape automated bonding (TAB), a chip on film (COF), and a chip on glass (COG). For the TAB and the COF technologies, driver ICs are bonded onto flexible printed circuits (FPCs) which are bonded onto glass substrates. As for the COG technology, driver ICs are directly bonded onto glass substrates.
The TAB basically consists of three layers, using polyimide (PI) as a substrate and adhesive to bond polyimide (PI) and copper foil. The inner lead bonding (ILB) adopts an eutectic bonding technology; the contact structure is protected with underfill dispensing; the outer lead bonding (OLB) adopts a package mode that glass panels are bonded with tape. Thus, the TAB is mainly applied to large-sized panels and related products.
The COF, consists of a two-layered FPC, does not have an adhesive layer as a traditional TAB does, so it is relatively thinner and softer and can offer better flexibility. Basically, the COF uses flip-chip bonding technology; that is, one or more chips, passive elements, or active elements are packaged on tapes. Driver ICs packaged with the flip-chip bonding technology will become multifunctional integrated chipsets and further, be able to reduce size.
For improving overall image quality and reducing the overall cost, a number of pins of driver ICs increases while the conductor spaces shorten. So the bonding process is the key to the whole manufacturing process for driver ICs, which implies that the bonding process takes high proportion of the total production cost. Thus, it is a critical issue to manage how to reduce the cost.
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Therefore, the main object of the present invention is to provide an LCD and circuit architecture thereof to simplify PCB and LC panel designs and to reduce PCB size. PCBs can remain the same size no matter what size of a panel. Besides, transmitting signals are consistent so modules can be reused. This can save on costs of materials.
According to the present invention, a liquid crystal display comprises a liquid crystal display panel, a printed circuit board, a first thin film substrate, a plurality of second thin film substrates, and a plurality of source driver chips. The printed circuit board comprises an input interface, two power signal lines, two data signal lines, and two control signal lines. The two power signal lines, the two data signal lines, and the two control signal lines are used to respectively transmit power signal, data signal, and control signal from the input interface. The first thin film substrate comprises one end connected to the liquid crystal display panel, and the other end connected to the printed circuit board. The two power signal lines, the two data signal lines, and the two control signal lines are disposed on the first thin film substrate. The plurality of second thin film substrates are connected to one end of the liquid crystal display panel. The first thin film substrate is positioned among the plurality of second thin film substrates. Each source driver chip is positioned on one of the second thin film substrate. The power signal, the data signal, and the control signal are transmitted between two source driver chips through the two power signal lines, the two data signal lines, and the two control signal lines on the second thin film substrate and the liquid crystal display panel. The two power signal lines, the two data signal lines, and the two control signal lines are disposed between every two second thin film substrates on the liquid crystal display panel.
In one aspect of the present invention, a plurality of gate driver chips and a plurality of third thin film substrates are connected to the liquid crystal display. Each gate driver chip is disposed on one of the third thin film substrates, and the plurality of third thin film substrates are connected to the liquid crystal display. One of the gate driver chips transmits the power signal and the control signal through the power signal lines and the control signal lines on the second thin film substrate. The first thin film substrate is positioned among the plurality of second thin film substrates at a position which forms a route for delivering the control signal and the power signal from the input interface to all source driver chips in a least period of time.
In another aspect of the present invention, the first thin film substrate is positioned in a middle alignment of the source drivers.
In still another one aspect of the present invention, the plurality of source driver chips comprises a first set of source driver chips and a second set of source driver chips, and the first thin film substrate is disposed in between the first set of source driver chips and the second set of source driver chips which are disposed on the plurality of second thin film substrates.
According to the present invention, a circuit architecture of providing power and signal to source driver chips is proposed, The circuit architecture comprises a liquid crystal display panel, a printed circuit board, a first thin film substrate, a plurality of second thin film substrates, and a plurality of source driver chips. The printed circuit board comprises an input interface, two power signal lines, two data signal lines, and two control signal lines. The two power signal lines, the two data signal lines, and the two control signal lines are used to respectively transmit power signal, data signal, and control signal from the input interface. The first thin film substrate comprises one end connected to the liquid crystal display panel, and the other end connected to the printed circuit board. The two power signal lines, the two data signal lines, and the two control signal lines are disposed on the first thin film substrate. The plurality of second thin film substrates are connected to one end of the liquid crystal display panel. The first thin film substrate is positioned among the plurality of second thin film substrates. Each source driver chip is positioned on one of the second thin film substrate. The power signal, the data signal, and the control signal are transmitted between two source driver chips through the two power signal lines, the two data signal lines, and the two control signal lines on the second thin film substrate and the liquid crystal display panel. The two power signal lines, the two data signal lines, and the two control signal lines between every two second thin film substrates are disposed on the liquid crystal display panel.
Compared with the prior art, the present invention provides an LCD and circuit architecture thereof to simplify PCB and LC panel designs and to reduce the area of PCBs and the amount of anisotropic conductive film (ACF), which is now only required to apply between a first thin film substrate and a PCB. That the size of PCBs does not change with the variations of the size of panels and that modules are reusable under conditions of consistent transmitting signals used, reduces manufacturing costs. Moreover, that PCBs are connected to a reasonable position shortens data transfer time and further improves the response time of panels.
These and other objectives of the present invention will become apparent to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
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The source driver chips 216a-216c and 226a-226c, and the plurality of gate driver chips 208 are disposed on the second thin film substrate 232 and the third thin film substrates 233 based on the COF technology. The plurality of source driver chips are enabled from two ends; that is, the source driver chips 216a-216c and 226a-226c are divided into a first set of source driver chips and a second set of source driver chips. The first set of source driver chips 216a-216c is connected in serial; similarly, the second set of source driver chips 226a-226c is connected in serial as well. The source driver chip of the first source driver chipset 216a is connected to the input interface 204, and the source driver chip of the second source driver chipset 226a is also electrically connected to the input interface 204. The control signals, data signals, and power signals which are generated by the input interface 204 are transmitted to the source driver chip 216a via the control signal line 240a, the data signal line 242a, and the power signal line 244a. Afterwards, the three types of signals are sequentially transmitted to the remaining of the first source driver chips 216b-216c. Similarly, the control signals, data signals, and power signals which are generated by the input interface 204 are transmitted to the source driver chip 226a via the control signal line 240b, the data signal line 242b, and the power signal line 244b. Afterwards, the three types of signals are sequentially transmitted to the second source driver chips 226b-226c. The input interface 204 also generates the control signal and the power signal to the gate driver chips 208 on the third thin film substrate 233 to enable and control the operation of the gate driver chips 208. A control signal line and power signal line between the third thin film substrates 233 are disposed on the conductive glass substrate of the LC panel 202.
The gate driver chips 208 generate scanning signals to the LC panel 202, and afterwards, the pixels in each row of the LC panel 202 are sequentially turned on. Meanwhile, the input interface 204 emits the control signals, power signals, and data signals to the source driver chip 216a. Upon receiving the power signals, the source driver chip 216a enables and receives the data signals transmitted from the input interface 204 and then transmits the control signals to the next source driver chip 216b. Similarly, upon receiving the power signals, the source driver chip 216b enables and receives the data signals transmitted from the input interface 204 and then transmits the control signals to the next source driver chip 216c. The process is repeated until the control signals are transmitted to the last source driver chip. The data signals, power signals, and control signals are transmitted by the source driver chips 226a-226c in a similar manner. Finally, the data signals which are outputted by the source driver chips 216a-216c and 226a-226c, are received by the straight-rowed pixels of the LC panel 202. The straight-rowed pixels are charged to each pixel's individually required voltage to show various gray scales.
Preferably, both the first thin film substrate 230 and the PCB 214 are positioned, but not limited to be, in a middle alignment of the source driver chips 216a-216c and 226a-226c. In another embodiment, the first thin film substrate 230 is positioned at a position which forms a route for delivering the control signal and the power signal from the input interface 204 to all source driver chips 216a-216c and 226a-226c in a least period of time. As a person skilled in this art is aware, the position relating to the least period of time depends on the size of the LCD panel and the material of the signal lines, and is thus not discussed in detailed in this application. For example, if the period of time for delivering a signal from the input interface 204 through the source driver chips 226a, 226b, 216a-216c, and the signal delivering route is shortest from the source driver chip 226c to the last gate driver chip 208, then positioning the first thin film substrate 230 and the PCB 214 between the source driver chips 226b and 226c is optional.
The first thin film substrate 230 and the PCB 214 are positioned in a middle alignment of the source driver chips 216a-216c and 226a-226c, so the data transfer time of the present invention is shorter than that of a traditional LCD. The response time of panels can be improved accordingly.
Although the present invention has been explained by the embodiments shown in the drawings described above, it should be understood to the ordinary skilled person in the art that the invention is not limited to the embodiments, but rather various changes or modifications thereof are possible without departing from the spirit of the invention. Accordingly, the scope of the invention shall be determined only by the appended claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201010230801.9 | Jul 2010 | CN | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/CN10/76546 | 9/1/2010 | WO | 00 | 12/13/2010 |
