Patent Application
20240248502
The present inventive concepts relate to a low-dropout (LDO) regulator and a system-on-chip including the same.
A supply voltage is provided to electronic components to provide power for operations of the electronic components. For example, a system-on-chip such as a mobile application processor (AP) have increased the number of powers to be supplied to the AP due to complexity of the AP. As a result, the number of routing lines connected from a power management integrated circuit (PMIC) to the AP and the number of off-chip elements such as an off-chip load capacitor and an inductor are also increasing.
The development focus of products is on merging power domains of AP cores. However, this may make it difficult to achieve per-core retention of a plurality of cores included in an AP for dynamic voltage scaling (DVS).
Example embodiments provide a low-dropout (LDO) regulator, securing an operation even in a dynamic voltage scaling (DVS) environment supplying power over a wide range of voltage fluctuation, and a system-on-chip including the same.
Example embodiments of inventive concepts provide a system-on-chip including a low-dropout (LDO) regulator configured to regulate a voltage of input power and to supply operation power to a core through an output mode, the core configured to receive the operation power to perform an operation, and a power supply circuit configured to supply the input power to the LDO regulator, wherein the power supply circuit is configured to receive a first power and a second power having different voltage characteristics and is further configured to supply a third power having a higher voltage of the first power and the second power, and the second power to the LDO regulator as the input power.
Example embodiments of inventive concepts provide a method of operating a system-on-chip comprising a low-dropout (LDO) regulator, the method including receiving first power and second power having different voltage characteristics, comparing the first power and the second power with each other to determine power having a higher voltage as third power, and supplying the third power and the second power to the LDO regulator through different power lines as input power.
Example embodiments of inventive concepts provide a low-dropout (LDO) regulator including an error amplifier configured to receive a feedback voltage and a reference voltage and to amplify and output a difference between the feedback voltage and the reference voltage based on bias power, a pass transistor having a gate node configured to receive an output of the error amplifier as a driving signal, a source node configured to receive input power, and a drain node connected to an output node and configured to adjust a voltage of the input power to provide an output voltage to the output node, and a power supply circuit configured to supply the input power of the pass transistor and the bias power of the error amplifier, wherein the power supply circuit is configured to receive first power and second power having different voltage differences, supply power having a higher voltage of the first power and the second power as the bias power, and supply the second power as the input power of the pass transistor.
Some example embodiments of inventive concepts will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings.
Hereinafter, various example embodiments will be described with reference to the accompanying drawings.
It will be understood that elements and/or properties thereof may be recited herein as being “the same” or “equal” as other elements or properties, and it will be further understood that elements and/or properties thereof recited herein as being “the same” as, or “equal” to other elements may be “the same” as, or “equal” to, other elements and/or properties thereof. Elements and/or properties thereof that are “the same” or “equal” as to other elements and/or properties thereof will be understood to include elements and/or properties thereof that are identical to, the same as, or equal to the other elements and/or properties thereof within manufacturing tolerances and/or material tolerances. Elements and/or properties thereof that are “the same” or “equal” as to other elements and/or properties may be structurally the same or substantially the same, functionally the same or substantially the same, and/or compositionally the same or substantially the same.
The system-on-chip 1000 may be an application processor (AP) used in a mobile device such as a smartphone or a tablet PC, or a central processing unit (CPU) and a graphics processing unit (GPU) of a general-purpose computer. The core 300 may be a logic circuit performing tasks such as calculation and computation of a processor, and may be a core circuit of a CPU, a GPU, or an AP, but example embodiments are not limited thereto.
In an example embodiment, the LDO regulator 200 may receive a plurality of powers having different voltage characteristics from the power supply circuit 100 and a may use the received powers as input powers. The LDO regulator 200 may regulate a voltage of one of the plurality of powers received, and may output the regulated voltage to an output node. An output power voltage VOUT may provide current, corresponding to current consumed to perform an operation such as calculation or computation in the core 300, to the core 300.
In an example embodiment, the power supply circuit 100 may receive first power VIN_1 and second power VIN_2, the plurality of powers having different voltage characteristics, from a power management integrated circuit (PMIC), and may determine power having a higher voltage, of the received powers, as third power VIN_3 and provide the third power VIN_3 to the LDO regulator 200 together with the second power VIN_2.
The first power VIN_1, received from the PMIC by the power supply circuit 100, may be power having a fixed magnitude of voltage and the second power VIN_2, received from the PMIC by the power supply circuit 100, may be power having a dynamic voltage magnitude. For example, the first power VIN_1 may be power having a fixed magnitude of voltage used for operation of a static random access memory (SRAM). The second power VIN2 may be a dynamic voltage scaling (DVS) power having a time-varying voltage magnitude for per-core retention of a core. Accordingly, in some example embodiments, even when fixed power having a high voltage (for example, fixed power of 1.2 V according to conventional arts) is not provided due to introduction of an ultra-fine process into the core, an operation of the core in a DVS environment, according to some example embodiments, may be secured.
In some example embodiments, the power supply circuit 100 and the LDO regulator 200 may be used with an analog LDO regulator. Alternatively, in some example embodiments, the power supply circuit 100 and the LDO regulator 200 may be used with an analog LDO regulator of a hybrid LDO regulator including an analog LDO regulator and a digital LDO regulator.
In an example embodiment, the LDO regulator 200 may receive a plurality of powers (e.g., the second power VIN_2 and the third power VIN_3) from the power supply circuit 100 as input powers.
The second power VIN_2 may be DVS power received from the PMIC by the power supply circuit 100 and having a voltage magnitude varying with time for per-core retention of a core. The LDO regulator 200 may regulate the second power VIN_2 as an output voltage to supply operating power of the core 300 to an output node.
The output voltage VOUT of the pass transistor may provide a voltage at which per-core retention of the core 300 may be achieved by changing a ratio of resistances of a plurality of resistance elements R1 and R2 connected in series to the output node. Some resistors R1 may be variable resistors.
The third power VIN_3 may be power determined to have a higher voltage of the fixed power having the fixed magnitude of voltage (e.g., the first power VIN_1) and the DVS power having a voltage magnitude varying with time (e.g., the second power VIN_2). The error amplifier, receiving a feedback voltage VFB and a reference voltage VREF, and amplifying, and outputting a difference between the feedback voltage VFB and the reference voltage VREF based on bias power, may use the third power VIN_3 as the bias power. A voltage of the first power VIN_1 may be within a range of variation of the variable voltage of the second power VIN_2.
Accordingly, in some example embodiments, the system-on-chip 1000 and the LDO regulator 200, included in the system-on-chip 1000, may use a power having a higher voltage, among a plurality of powers, as bias power of the error amplifier to reliably turn off the pass transistor. As a result, in some example embodiments, unrequired current may be prevented from being supplied to the core 300 through the pass transistor even in a no load state or a low load state of the core 300.
In some example embodiments, the LDO regulator 200 may secure an operation of a core even when fixed power of 1.2 V is not provided due to an ultra-fine process, compared with the LDO regulator 2000, according to conventional arts (e.g.,
In some example embodiments, to improve and/or increase power efficiency of an LDO regulator, it is advantageous and/or beneficial to reduce and/or decrease a difference between an output voltage and an input voltage. However, in some example embodiments, in the case of an LDO regulator using single power, an operation of an LDO regulator including an error amplifier cannot be secured when an input voltage, lower than or equal to a predetermined (e.g., desired) voltage, is used.
In conventional arts, when the LDO regulator 2000 uses the fixed power of 1.2 V supplied to a core as input power, an operation and per-core retention of the LDO regulator are secured, but power efficiency is low. In addition, in conventional arts, when the fixed power of 1.2 V supplied to the core is not provided due to an ultra-fine process in the future, the LDO regulator 2000 cannot secure a stable operation in a DVS environment with supplied powers. For example, in conventional arts, when DVS power of a core supplied from a PMIC is used as input power of the LDO regulator of
In conventional arts, even an LDO regulator having dual powers using additional power as bias power of the error amplifier cannot secure an operation of the LDO regulator when the fixed power of 1.2 V supplied to the core is not provided due to an ultra-fine process in the future. For example, in conventional arts power having a fixed voltage used for operation of an SRAM may be used as bias power of an error amplifier, and a DVS power having a variable voltage may be used as input power of a pass transistor. For example, when a voltage of the DVS power is greater than a voltage of the bias power of the pass transistor, the pass transistor cannot be completely turned off. Accordingly, unrequired current may be provided a core to prevent or alternatively reduce, per-core retention from being achieved.
In some example embodiments, the system-on-chip 1000 may supply power having a higher voltage, among a plurality of powers, to the power supply circuit 100 as bias power of the LDO regulator 200. For example, the bias power of the LDO regulator 200 always has a voltage greater than or equal to the input voltage of the pass transistor, so that the pass transistor may be completely turned off, but example embodiments are not limited thereto, and, in some example embodiments, the bias power of the LDO regulator 200 may have a voltage greater than or equal to the input voltage of the pass transistor, so that the pass transistor may be turned off. For example, a voltage at which an error amplifier is operable may be applied as bias power to secure a stable operation of the error amplifier.
In some example embodiments, the power supply circuit 100 may include a current comparison circuit 110, a switch driving circuit 130, and a power select circuit 150.
The current comparison circuit 110 may compare voltage magnitudes of the first power VIN_1 and the second power VIN_2 based on comparison of current magnitudes. The current comparison circuit 110 may be connected to the first power VIN_1 and the second power VIN_2 to output a comparison signal ICOMP obtained by comparing the magnitudes of currents IN1 and IN2 provided from the first power VIN_1 and VIN_2. Power lines, provided with the currents IN1 and IN2 provided from the first power VIN_1 and the second power VIN_2, are each illustrated as being a single power line in
The switch driving circuit 130 may control a plurality of switches STrA and STrB included in the power select circuit 150 based on the comparison signal ICOMP output from the current comparison circuit 110. The plurality of switches STrA and STrB may include a P-channel metal-oxide-semiconductor (PMOS) transistor.
The switch driving circuit 130 may include an element, such as an inverter, to generate a signal controlling the PMOS switches STrA and STrB included in the power select circuit 150 based on the comparison signal ICOMP output from the current comparison circuit 110. The switch driving circuit 130 will be described below through various example embodiments.
In some example embodiments, when the current IN2 provided from the second power VIN_2 is greater than the current IN1 provided from the first power VIN_1, the switch driving circuit 130 may transmit a low signal from the PMOS switch STrB, connected to the second power VIN_2 of the power select circuit 150, to a gate node to turn of the switch STrB. For example, the transmitting the low signal may be decreasing or reducing a gate voltage V2 to be lower than a source voltage of the switch STrB. In this case, in some example embodiments, the switch driving circuit 130 may transmit a high signal to the PMOS switch STrA connected to the first power VIN_1 of the power select circuit 150 to the gate node to turn off the switch STrB.
The plurality of switches STrA and STrB of the power select circuit 150, in which a source node is connected to each of the first power VIN_1 and the second power VIN_2, may be complementarily turned on or turned off. Thus, in some example embodiments, each of the plurality of switches STrA and STrB may output the connected first power VIN_1 or second power VIN_2 as third power VIN_3.
In some example embodiments, each of the plurality of switches STrA and STrB of the power select circuit 150 is implemented as an n-channel MOS (NMOS) transistor. For example, in this case, when a magnitude of the fixed voltage of the first power VIN_1 is within a range of a variable voltage of the second power VIN_2, each switch may not be completely turned off. Accordingly, in some example embodiments, the plurality of switches STrA and STrB of the power select circuit 150 include PMOS transistors, so that the power select circuit 150 may stably operate in a DVS environment of ultra-fine process.
The switch driving circuit 130 may transmit control signals ISEL_A and ISEL_B, complementarily turning on or turning off a plurality of PMOS switches of the power select circuit 150, to the power select circuit 150.
The switch driving circuit 130 may include a first switch driving circuit 130_1, providing a driving signal ISEL_A of a first switch, connected to a first power VIN_1, among a plurality of switches, and a second switch driving circuit 130_2 providing a driving signal ISEL_B of a second switch, connected to a second power VIN_2, among the plurality of switches.
In some example embodiment, the first switch driving circuit 130_1 and the second switch driving circuit 130_2 may generate a signal controlling PMOS switches, to which each switch corresponds, based on a comparison signal ICOMP of currents IN1 and IN2 provided from the first power VIN_1 and the second power VIN_2. The first switch driving circuit 130_1 and the second switch driving circuit 130_2 may include a logic element such as an inverter based on gate-source voltage characteristics of the PMOS switch and the comparison signal ICOMP to generate a control signal.
In some example embodiments, the first switch driving circuit 130_1 and the second switch driving circuit 130_2 may receive an operating voltage from power, different from power connected to a corresponding switch. For example, the first switch driving circuit 130_1, transmitting a control signal ISEL_A to a first switch STrA connected to the first power VIN_1, may receive an operating voltage from second power. Similarly, in some example embodiments, the second switch driving circuit 130_2, transmitting the control signal ISEL_B to the second switch STrB connected to the second power VIN_2, may receive an operating voltage from the first power VIN_1.
Among the PMOS switches of the power select circuit 150, a turned-off switch is in a state of being connected to lower power than a turned-on switch. Accordingly, in some example embodiments, turning off the PMOS switch of the power select circuit 150 should be based on a voltage of power, other than power transmitted by itself.
The first switch driving circuit 130_1 and the second switch driving circuit 130_2 may selectively include a level shifter according to changes in voltage level of a received input signal and output level (high or low) of logic circuits Logic1 and Logic2. For example, when the voltage level of the logic circuits Logic1 and Logic2 is lower than an operating voltage level of the logic circuits Logic1 and Logic2 and an activation level (High) output of the logic circuits Logic1 and Logic2 is required, a level shifter may be provided to prevent short-current of the logic circuit element. Accordingly, in some example embodiments, the first switch driving circuit 130_1 and the second switch driving circuit 130_2 may selectively include a level shifter according to the voltage level of the input signal, the operating voltage level of the logic circuit, and the configurations of the logic circuits Logic1 and Logic2. The level shifter may also be selectively included in the example embodiments of
In some example embodiments, the switch driving circuit 130 may selectively include a Schmitt trigger circuit to provide hysteresis to input signals of the first switch driving circuit 130_1 and the second switch driving circuit 130_2.
In some example embodiments, the power supply circuit 101 may include a current comparison circuit 111, PMOS switches STr1 and STr2, and a switch driving circuit 131. The current comparison circuit 111 may compare voltage magnitudes of the first power VIN_1 and the second power VIN_2 based on the current comparison. The PMOS switches STr1 and STr2 may be connected to the first power VIN_1 and the second power VIN_2, respectively. The switch driving circuit 131 may transmit a driving signal to the PMOS switches STr1 and STr2.
The current comparison circuit 111 may include transistors Tr1, Tr2, and Tr4 and transistors Tr3 and Tr5. The transistors Tr1, Tr2, and Tr4 may receive input currents I1, I2, and I4 from the first power VIN_1. The transistors Tr3 and Tr5 may receive input currents I3 and I5 from the second power VIN_2. The current comparison circuit 111 may include a constant current source I connected to the transistor Tr1. Some transistors Tr1 and Tr2 may constitute a current mirror circuit M1, and other transistors Tr4 and Tr5 may constitute another current mirror circuit M2.
Due to the constant current source I, current I corresponding to the constant current source I may flow as output current I1 of the transistor Tr1 connected to first power VIN_1.
In addition, in some example embodiments, due to a configuration of a current mirror circuit M1, the same current I may flow as output current I2 of the transistor Tr2. Due to the output current I2 of the transistor Tr2, the same current I may flow as output current I4 of the transistor Tr4 and the same current I may also flow as output current I5 of the transistor Tr5 constituting the current mirror circuit M2 with the transistor Tr4.
For example, when a voltage of second power VIN_2 is higher than a voltage of the first power VIN_1, a gate source voltage of the transistor Tr3 is greater than a gate source voltage of the transistor Tr2, so that current greater than current I of the transistor Tr5 may flow as output current I3 of the transistor Tr3. Accordingly, in some example embodiments, output current IS of the current comparison circuit 111 may transmit current corresponding to a high level, as a result of comparison, to the switch driving circuit 131.
A second switch driving circuit 131_2 of the switch driving circuit 131 may invert the output current IS corresponding to the high level and may transmit the inverted output current to a second switch Str2 to turn on the second switch Str2 and to output the second power VIN_2 as third power VIN_3. A first switch driving circuit 131_1 may transmit a signal IS1, obtained by reinverting a low signal of the second switch driving circuit 131_2, to the first switch Str1 to turn off the first switch Str1. As described above, in some example embodiments, an operating voltage of the first switch driving circuit 131_1 is provided from the second power VIN_2 having a higher voltage than the first power VIN_1, so that the first switch Str1, a PMOS switch, may be reliably turned off.
For example, when the voltage of the second power VIN_2 is lower than the voltage of the first power VIN_1, the source gate voltage of the transistor Tr3 is lower than the source gate voltage of the transistor Tr2, so that current lower than the current I of the transistor Tr5 may flow as output current I3 of the lower transistor Tr3. Accordingly, in some example embodiments, the output current IS of the current comparison circuit 111 may transmit current corresponding to a low level, as a result of comparison, to the switch driving circuit 131. In contrast to what has been described above, the switch driving circuit 131 may transmit a low signal IS1 to the first switch Str1 to turn on the first switch Str1 and may transmit a high signal IS2 to the second switch Str2 to turn off the second switch Str2.
In some example embodiments, the power supply circuit 102 may include a current comparison circuit 112 based on comparison of current magnitudes to compare voltage magnitudes of the first power VIN_1 and the second power VIN_2, PMOS switches STr3 and STr4, respectively connected to the first power VIN_1 and the second power VIN_2, and a switch driving circuit 132 transmitting driving signals to the PMOS switches STr3 and STr4.
The current comparison circuit 112 may include a transistor Tr6, receiving input current I6 from the first power VIN_1, and a transistor Tr7 receiving input current I7 from the second power VIN_2. The current comparison circuit 112 may include a plurality of constant current sources I, respectively connected to transistors Tr6 and Tr7. A gate node of the transistor Tr6 may be connected to an output of a drain node on a constant current source side.
Current I corresponding to the constant current source I flows as output current I6 of the transistor Tr6 connected to first power VIN_1 due to the constant current source I, and a gate source voltage of the transistor Tr7 is greater than a gate source voltage of the transistor Tr6 when a voltage of the second power VIN_2 is higher than a voltage of the first power VIN_1. For example, current greater than the current I6 of the transistor Tr6 may flow as output current I7 of the transistor Tr7. Accordingly, in some example embodiments, output current ISS of the current comparison circuit 112 may transmit current corresponding to a high level, as a result of comparison, to the switch driving circuit 132.
A second switch driving circuit 132_2 of the switch driving circuit 133 may invert the output current ISS corresponding to a high level and may transmit a low signal Is4 to the second switch Str4 to turn on the second Str4 and to output the second power VIN_2 as third power VIN_3. The first switch driving circuit 132_1 may transmit a signal IS3, obtained by reinverting the low signal of the second switch driving circuit 132_2, to the first switch Str3 to turn off the first switch Str3. An operating voltage of the first switch driving circuit 132_1 may be received from the second power VIN_2 having a higher voltage than the first power VIN_1.
For example, when the voltage of the second power VIN_2 is lower than the voltage of the first power VIN_1, a gate source voltage of the transistor Tr7 is lower than a gate source voltage of the transistor Tr6, so that current having a lower magnitude than the current I6 of the transistor Tr6 may flow as output current I7 of the transistor Tr7. Accordingly, in some example embodiments, the output current ISS of the current comparison circuit 112 may transmit current corresponding to a low level, as a result of comparison, to the switch driving circuit 132.
The switch driving circuit 133 may transmit a low signal IS3 to the first switch Str3 to turn on the first switch Str3, and may transmit a high signal IS4 to the second switch Str4 to turn off the second switch Str4.
Referring to
Accordingly, in some example embodiments, the current comparison circuit may have hysteresis illustrated in
The circuits 110_1 and 110_2 having hysteresis in
In some example embodiments, the current comparison circuit having hysteresis may include a first metal-oxide-semiconductor field-effect transistor (MOSFET) circuit 110_1, in which one of a source node and a drain node receives current supplied from the first power VIN_1, and a second MOSFET circuit 110_2 in which one of the source node and the drain node receives current supplied from the second power VIN_2.
A gate node of the first MOSFET circuit 110_1 and a gate node of the second MOSFET circuit 110_2 of the current comparison circuit may be connected to each other, and a resistance magnitude ratio of the first MOSFET circuit 110_1 and the second MOSFET circuit 110_2 may vary based on a comparison signal ICOMP of the current comparison circuit.
A transistor Tr_A included in the first MOSFET circuit 110_1 and transistors Tr_B and Tr_C included in the second MOSFET circuit 110_2 may each be a transistor set in which a plurality of transistors are connected in parallel. The transistor Tr_A and the transistor Tr_B may have different resistance magnitude ratios. The resistance may be voltage-dependent resistance of a transistor. For example, gate-source voltages of the transistors may be different from each other, or the number of transistors connected in parallel and included in the transistor set may vary.
A switch SW may be closed by a switch control signal ISW generated by a switch driving circuit 133 and the transistor Tr_C of the second MOSFET circuit 110_2 may be connected in parallel to the transistor Tr_B after outputting the comparison signal ICOMP indicating that a voltage of the second power VIN_2 is higher than a voltage of the first voltage VIN_1. The switch control signal ISW may be a signal to close a switch SW when a control signal ISEL_B, driving a switch connected to the second power VIN_2 in the power select circuit, is low. As in the above-described example embodiments, the control signals ISEL_A and ISEL_B driving the switches of the power select circuit may be generated based on the comparison signal ICOMP of the current comparison circuit.
A magnitude of power-dependent resistance of a transistor Tr_9 connected to first power VIN_1 of a hysteresis unit H1 of a current comparison circuit 113 may be different from a magnitude of power-dependent resistance of a transistor Tr_10 connected to a second power VIN_2. For example, when a voltage of the second power VIN_2 is greater than a voltage of the first power VIN_1 by a predetermined or desired difference or more, a comparison signal ISSS indicating the voltage of the second power VIN_2 is greater than the voltage of the first power VIN_1 may be generated within the predetermined or desired difference depending on the magnitude ratio of the power-dependent resistance.
For example, when the voltage of the second power VIN_2 is determined to be greater than the voltage of the first power VIN_1, a switch driving circuit 133 may transmit a control signal IS6 to a switch SW for closing the switch SW and a transistor Tr11 may be connected in parallel to a transistor Tr10. Accordingly, in some example embodiments, a ratio of voltage-dependent resistance of the transistors Tr10 and Tr11, connected in parallel to each other, to voltage-dependent resistance of the transistor Tr9 may be changed. Then, for example, when the voltage of the second power VIN_2 is determined to be smaller than the voltage of the first power VIN_1 while the changed ratio of the voltage-dependent resistance of the transistors Tr10 and Tr11 to the voltage-dependent resistance of the transistor Tr9 is maintained, the circuit 133 may transmit the control signal IS6 to the switch SW for opening the switch SW.
Similarly to what has been described with reference to
In some example embodiments, the power supply circuit 105 may include a voltage comparison circuit based on voltage magnitude comparison to compare the magnitudes of the voltages of the first power VIN_1 and the second power VIN_2, PMOS switches STr9 and STr10, respectively connected to the first power VIN_1 and VIN_2, and a switch driving circuit 135 transmitting driving signals to the PMOS switches STr9 and STr10.
The voltage comparator circuit may include a plurality of resistor sets RA1 and RA2 connected in series and receiving a voltage from the first power VIN_1, a plurality of resistor sets RB1 and RB2 connected in series and receiving a voltage from the second power VIN_2, and a voltage comparator 1310. The voltage comparator 1310 may include hysteresis therein.
The switch driving circuit 135 of the power select circuit may be the same as the switch driving circuit 130 of
The switch driving circuit 135 may receive a voltage magnitude comparison signal ICOMP to changes a voltage level, and may provide a driving signal to the switches STr9 and STr10 through a logic operation such as inversion. The switches STr9 and STr10 may output power, to which they are connected, as third power VIN_3 based on the driving signal.
Referring to
The error amplifier 2200 may receive a feedback voltage and a reference voltage, and may amplify a difference between the feedback voltage and the reference voltage based on a bias power and transmit the amplified difference to a gate node of the pass transistor 2300. The LDO regulator 2000 may be provided inside a system-on-chip such as a mobile application processor (AP).
In an example embodiment, the error amplifier 2200 may receive power having a higher voltage of first power VIN_1 and second power VIN_2 having different voltage characteristics from a power select circuit 2100 as a bias voltage of the error amplifier 2200.
The pass transistor 2300 may include a gate node receiving an output of the error amplifier 2200 as a driving signal, a source node receiving input power, and a drain node connected to the output node, and may adjust a voltage of the input power to provide an output voltage VOUT to the output node. Input power of the pass transistor 2300 may receive the second power VIN_2.
In an example embodiment, the power select circuit 2100 may be connected to the first power VIN_1 having a fixed voltage magnitude and the second power VIN_2 having a variable voltage magnitude. The second power VIN_2 may be DVS power. The power select circuit 2100 may supply power having a higher voltage of the first power VIN_1 and the second power VIN_2 as third power VIN_3, bias power of the error amplifier 2200, based on a comparison signal obtained by comparing magnitudes of currents provided from the first power VIN_1 and the second power VIN_2.
In operation S110, the system-on-chip may receive first power VIN_1 and a second power VIN_2 having different voltage characteristics. For example, the system-on-chip may receive first power VIN_1 having a fixed voltage magnitude and second power VIN_2 having a variable voltage magnitude.
In operation S120, the system-on-chip may compare the first power VIN_1 and the second power VIN_2 to determine power having a higher voltage as third power VIN_3. In operation S130, the system-on-chip may supply the third power VIN_3 and the second power
VIN_2 to the LDO regulator. The third power VIN_3 provided to the LDO regulator may be provided as bias power of an error amplifier of the LDO regulator.
The system-on-chip may compare magnitudes of currents provided from the first power VIN_1 and the second power VIN_2 to determine power having a higher voltage of the first power VIN_1 and the second power VIN_2 as the third power VIN_3. In this case, the current magnitude comparison may be performed by a current comparison circuit having hysteresis.
The system-on-chip may be connected to one of the first power VIN_1 and the second power VIN_2, and may transmit a control signal based on the current magnitude comparison to a gate node of each of a plurality of switch elements including a PMOS transistor. For example, only one of the plurality of switch elements may be complementarily turned on to output power, to which the only one power is connected, as the third power VIN_3.
As set forth above, according to some example embodiments, an LDO regulator and a system-on-chip including the LDO regulator may secure an operation even in a DVS environment, in which power within a wide voltage variation range is supplied, and may maintain an output voltage provided to a core even in a no load sate of the core.
One or more of the elements disclosed above may include or be implemented in one or more processing circuitries such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitries more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FGPA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc.
While some example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present inventive concepts as defined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0008950 | Jan 2023 | KR | national |
| 10-2023-0040183 | Mar 2023 | KR | national |
This application claims benefit of priority to Korean Patent Application No. 10-2023-0008950, filed on Jan. 20, 2023, and 10-2023-0040183, filed on Mar. 28, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety.
