Patent Grant
12147255
A low-dropout regulator (LDO) is a DC linear voltage regulator that can regulate the output voltage even when the supply voltage is very close to the output voltage. Low dropout regulators may be advantageous over other DC to DC regulators based on their absence of switching noise, potential for smaller device sizes, and simplified overall designs.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in some various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between some various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Some embodiments of the disclosure are described. Additional operations can be provided before, during, and/or after the stages described in these embodiments. Some of the stages that are described can be replaced or eliminated for different embodiments. Additional features can be added to the circuit. Some of the features described below can be replaced or eliminated for different embodiments. Although some embodiments are discussed with operations performed in a particular order, these operations may be performed in another logical order.
Voltage reference devices such as LDOs and bandgap voltage references are used in a wide variety of applications including integrated circuits to provide a stable, predictable desired voltage. It is thus sometimes desirable that LDOs and bandgap voltage references maintain a precise fixed voltage over a range of conditions such as temperature changes, power supply variations, and changes in circuit loading any devices being driven. As these voltage references are commonly used as power supplies for a wide variety of devices and integrated circuits, they are often implemented along with a circuit to conveniently and safely start up and power down. It is often desirable that any such circuitry maintains the as-designed fixed voltage of the voltage reference device it controls (e.g., ±0.1%, ±1.0%, ±5.0%) during start up and power down and can do so frequently with a high degree of reliability and durability.
Meeting these requirements can become a challenge, e.g., as the operating voltage of the circuit increases, such as at voltages around 1.2 volts and greater. When start-up and power-down circuitry for voltage regulators are implemented by electrically coupling the voltage regulator to a supply voltage and a ground directly by core-only power components at each junction, anomalous behavior may result. In certain implementations, each transistor's gate is electrically coupled to a status voltage signal indicating whether the voltage regulator should be powered on or powered down, which thereby controls those transistors. The voltage regulator's output is coupled to the supply voltage by an output driver transistor and to ground by a voltage divider. The voltage regulator is powered down by setting the status voltage signal to an appropriate voltage to turn the core-only power components on or off in such a way that it causes the output driver transistor to turn off, resulting in the voltage regulator's output being pulled down to ground through the voltage divider while the status voltage signal remains in the power-down state. Conversely, the voltage regulator may be started up by setting the status voltage signal to an appropriate voltage to turn the core-only power components on or off so that the output driver transistor is turned on, allowing the voltage regulator to operate normally while the status voltage signal remains in the start-up state.
This “rail-to-rail” operation of the circuit may become problematic at higher voltages (e.g., of 1.2 volts or greater) because it results in a relatively large voltage drop over individual components. For example, an output driver transistor may at times subjected to a high voltage (e.g., the full 1.2 or more volts across it), such as when the circuit is in power-down mode and outputting 0 volts.
Subjecting components of the voltage regulator circuit to relatively high voltages can result in a variety of issues, including damage to power control and output driver circuitry. Systems and methods as described herein can mitigate certain of these issues, which include risk of dielectric breakdown of circuit components exposed to high voltages, resulting in unwanted breakdown and leakage current. Such behavior is particularly problematic when it affects an output value of the voltage regulation circuit, which is the circuit's primary purpose.
Systems and methods as described herein can mitigate issues by controlling voltage drop across individual components of the circuit, resulting in limited leakage current, and consequently increasing the circuit's reliability, performance and longevity by reducing voltage breakdown across individual components. In embodiments, the device of the present disclosure is implemented with smaller components, which can result in a desirably small footprint for the circuit.
In embodiments, systems and methods disclosed herein achieves some or all of these benefits by keeping gate-source and drain-source voltage differentials for all IO and output driving devices at a limited level (e.g., under 0.75 volts) throughout both power-down and normal modes of operation. Maintaining this relatively low voltage differential improves performance and reliability of the circuit and allows the circuit to be used to drive a wider variety of loads (e.g., analog loops such as PLL and ADCs that may provide sudden current draws from the LDO, which can result in large voltage differentials across certain LDO components if not properly protected).
The power down control circuit 112 is configured to provide output transistor 211 a constant voltage PDG 251 at all times while the circuit is active. PDG 251 is set to a predetermined value (for example, 0.5 volts) such that output transistor 211 acts as a MOS resistor to provide a desired output voltage level 233 by acting as a voltage divider with resistors 240 and 241. Thus, when the circuit is operating in an active mode, it will provide an output voltage 233 proportional to the sum resistance of resistors 240 and 241 divided by the total sum resistance of output transistor 211 and resistors 240 and 241. The utilization of output transistor 211, which acts as a voltage tunable resistor, in series between output driver 210 and output 233, reduces the voltage drop experienced by output driver transistor 210 by the amount of the voltage drop experienced across output transistor 211. As noted above, reducing voltage drop across power control circuitry 110 and the output driver 106 is an example benefit provided in embodiments herein. Such a reduction in such voltage drops across these components increases reliability, performance, and longevity of the device by ultimately reducing leakage current across the components. Additionally, this reduction in voltage difference across the output driver transistor 210 allows the output driver transistor 210 to potentially be implemented with a smaller sized transistor component. Finally, the use of output transistor 211 as a voltage tunable resistor allows output voltage 233 to be easily configured by modifying the output tuning signal PDG 251, which is output by the power down control circuit 112.
A top portion of power control circuitry 110 includes transistors 221 and 222 are also represented in
The bottom portion of power control circuitry 110 includes transistors 223 and 224 that are implemented with NMOS transistors. Each of power control circuitry transistors 223 and 224 has a drain terminal electrically coupled to signals from LDO 100 and each has a gate terminal electrically coupled to a status voltage signal 231 (PDNB) received from the power down control circuit 112. Each power control circuitry transistor 223 and 224 has a source terminal electrically coupled to electrical ground 235.
When inverse status voltage signal 230 (PDPB) is set to a high voltage level (e.g., near the supply voltage 234), the circuit is set to a “normal operation mode,” in which power control circuitry transistors 221 and 222 are turned off. During that time, the status voltage signal 231 (PDNB) is set to its low value of 0 volts. This turns off power control circuitry devices 223 and 224. With all power control circuitry devices 221, 222, 223 and 224 turned off in normal operation mode, the LDO 100 operates normally without interference.
In normal operation mode, the output 236 of LDO 100 controls the gate of output transistor 210. When output driver 210 is turned on, its drain terminal functions provides current to the output 233 of the circuit via output transistor 211, which functions as a tunable resistor as commanded by PDG 251. While output driver 210 is turned on, current flows from the supply voltage 234 through output driver 210 and output transistor 211 and then over resistors 240 and 241 to electrical ground 235, where resistors 240 and 241 pull up the voltage of output 233.
When in a normal operating mode, such that transistor 222 has no impact on node 236, and when the output 236 of LDO 100 is a low voltage, it turns the output driver 210 on, allowing current to flow from the supply voltage 234, through output driver transistor 210, through output transistor 211, and through resistors 240 and 241 to ground. When this occurs, the output 233 is equal to the output driver's current multiplied by the ratio of the sum of the resistance of resistors 240 and 241 divided by the total sum of the resistance of the output transistor 211 and resistors 240 and 241.
When the power down control circuit 112 sets the status voltage signal 231 (PDNB) to its high value (e.g., 0.75 volts) and inverse status voltage signal 230 (PDPB) is consequently set to its low value (e.g., 0.75 volts), all four of the power control circuitry devices 221, 222, 223 and 224 are turned on. This has the effect of putting the circuit in “power-down mode.” Most significantly, the power control circuitry transistor 222 supplies the gate of output transistor 210 with a high voltage at LDO output 236. When output driver transistor 210 is supplied with a high voltage to its gate terminal, it turns off, disconnecting the supply voltage 234 from supplying voltage and current through output transistor 211 and resistors 240 and 241 to electrical ground 235. Thus, output 233 is pulled to 0 volts through resistors 240 and 241 to electrical ground 235. Additionally, power control circuitry transistors 223 and 224 are turned on by receiving the 0.75 volt status voltage signal 231 to their gate terminals, draining charge from LDO 100 to ground 235. Thus, the circuit achieves power-down mode with its output 233 set to 0 volts and charge drained from the LDO 100.
The inverse status voltage signal 330 is generated by a circuit 310. The inverse status voltage signal 330 is electrically coupled to the supply voltage 334 through a first resistor 311. The inverse status voltage signal 330 is also electrically coupled to a drain of a first NMOS transistor 313 through a second resistor 312. The output tuning signal 351 is electrically coupled to the a gate terminal of the first NMOS transistor 313 and a source terminal of the first NMOS transistor 313 is electrically coupled to a drain of a second NMOS transistor 314. The second NMOS transistor 314 has a source terminal electrically coupled to electronic ground 335 and a gate terminal electronically coupled to a power-down input signal 340. Of note, when a power down command is received by the power down control circuit 112 (i.e., PD goes high), transistor 314 turns on and pulls the inverse status voltage signal 330 (PDPB) down from the supply voltage 334, as depicted in
The status voltage signal 331 is generated by a circuit 320. The status voltage signal 331 is electrically coupled to the supply voltage 334 through a first resistor 321. The status voltage signal 331 is also electrically coupled to electronic ground 335 through a second resistor 322 in parallel with an NMOS transistor 323, which has a source terminal electrically coupled with electronic ground and a drain terminal electronically coupled with the status voltage signal 331. The NMOS transistor 323 is controlled by the power-down input signal 340.
While the power down signal 531 is low, the second transistor 514 is off, resulting in the gate terminal 515 of the tuning transistor 512 having a high voltage, which results in the tuning transistor 512 being turned off. While the tuning transistor 512 is off, the inverse status voltage signal 530 outputs a voltage equivalent to the supply voltage 534. Of note, the passive resistor element 511 is implemented as a passive resistor to pull the voltage of the inverse status voltage signal 530 up to the supply voltage 534 while the tuning transistor 512 is turned off. When the power down signal 531 goes high, the second transistor 514 is turned on, which pulls down the gate terminal 515 of the tuning transistor 512. When the tuning transistor 512 is turned on, current flows through the power-down control circuit 510 from the source voltage 534 to the drain 535, which pulls down the inverse status voltage signal 530 to its low voltage state. The voltage value of the low voltage state of the inverse status voltage signal 530 is defined by the threshold voltage of tuning transistor 512.
The breakdown protection NMOS transistor 615 and the first NMOS transistor 613 are each controlled by a gate voltage 633 and 632, respectively, which are generated by a voltage divider 620. The voltage divider 620 comprises the supply voltage 634 electrically coupled to the gate voltage 633 of the breakdown protection NMOS transistor 615 through a first resistive element 621. The gate voltage 633 of the breakdown protection NMOS transistor 615 is electrically coupled to the gate voltage 632 of the first NMOS transistor 613 through a second resistive element 622. The gate voltage 632 is electrically coupled to electrical ground 635 through a third resistive element 623.
The resistive elements 621, 622, and 623 of the voltage divider 620 may be selected to provide desired gate voltages 633 and 632. The gate voltage 632 for the first NMOS transistor is determined by the following equation: V 632=(VDD 634−GND 635)/(R 621+R 622+R 623)×R 623, and the gate voltage 633 for the breakdown protection NMOS transistor 615 is determined by the following equation: V 633=(VDD 634−GND 635)/(R 621+R 622+R 623)×(R 623+R 622), wherein V 632 and V 633 represent voltage values of the gate voltages 632 and 633 respectively, and R 621, R 622, and R 623 represent the resistance values of resistive elements 621, 622, and 623 respectively.
In some embodiments, the inclusion of the breakdown protection NMOS transistor 615 reduces the occurrence and magnitude of breakdown current in power-down control circuit 610 by reducing voltage drop across the first NMOS transistor 613 and the second NMOS transistor 614.
A source terminal of each cross-coupled latch transistor 751 and 752 is electrically coupled to a source voltage 734. The source voltage 734 is also electrically coupled to a drain terminal of cross-coupled latch transistor 751 through resistive element 753 and to a drain terminal of cross-coupled latch transistor 752 through resistive element 754. A gate terminal of cross-coupled latch transistor 751 is electrically coupled to the drain terminal of cross-coupled latch transistor 752. A gate terminal of cross-coupled latch transistor 752 is similarly electrically coupled to the drain terminal of cross-coupled latch transistor 751. The drain terminal of cross-coupled latch transistor 751 is electrically coupled to the inverse status voltage 730.
The drain terminal of cross-coupled latch transistor 751 is electrically coupled to a drain terminal of a first NMOS transistor 703. The first NMOS transistor 703 has a source terminal connected to electrical ground 735 through a second NMOS transistor 704. The first NMOS transistor 703 has a gate terminal connected to an output tuning signal 732. The second NMOS transistor 704 has a gate terminal electrically coupled to a power-down input signal 731.
Similarly, the drain terminal of cross-coupled latch transistor 752 is electrically coupled to a drain terminal of a third NMOS transistor 705. The third NMOS transistor 705 has a source terminal connected to electrical ground 735 through a fourth NMOS transistor 706. The third NMOS transistor 705 has a gate terminal connected to an output tuning signal 732. The fourth NMOS transistor 706 has a gate terminal electrically coupled to an inverse power-down input signal 733.
A source terminal of each cross-coupled latch transistor 761 and 762 is electrically coupled to a source voltage 734. The source voltage 734 is also electrically coupled to a drain terminal of cross-coupled latch transistor 761 through resistive element 763 and to a drain terminal of cross-coupled latch transistor 762 through resistive element 764. A gate terminal of cross-coupled latch transistor 761 is electrically coupled to the drain terminal of cross-coupled latch transistor 762. A gate terminal of cross-coupled latch transistor 762 is similarly electrically coupled to the drain terminal of cross-coupled latch transistor 761. The drain terminal of cross-coupled latch transistor 761 is electrically coupled to the inverse status voltage 730.
The drain terminal of cross-coupled latch transistor 761 is electrically coupled to a drain terminal of a first NMOS transistor 713. The first NMOS transistor 713 has a source terminal electrically coupled to a drain terminal of a second NMOS transistor 714. The first NMOS transistor 713 has a gate terminal electrically coupled to an output tuning signal 732. The second NMOS transistor has a gate terminal electrically coupled to a power-down input signal 731 and a source terminal electrically coupled to both a gate and a drain terminal of a grounding NMOS transistor 780, which has a source terminal electrically coupled to the electrical ground 735.
Similarly, the drain terminal of cross-coupled latch transistor 762 is electrically coupled to a drain terminal of a third NMOS transistor 715. The third NMOS transistor 715 has a source terminal electrically coupled to a drain terminal of a fourth NMOS transistor 716. The third NMOS transistor 715 has a gate terminal electrically coupled to an output tuning signal 732. The fourth NMOS transistor has a gate terminal electrically coupled to an inverse power-down input signal 733 and a source terminal electrically coupled to both a gate and a drain terminal of the grounding NMOS transistor 780.
A source terminal of each cross-coupled latch transistor 771 and 772 is electrically coupled to a source voltage 734. The source voltage 734 is also electrically coupled to a drain terminal of cross-coupled latch transistor 771 through resistive element 773 and to a drain terminal of cross-coupled latch transistor 762 through resistive element 774. A gate terminal of cross-coupled latch transistor 771 is electrically coupled to the drain terminal of cross-coupled latch transistor 772. A gate terminal of cross-coupled latch transistor 772 is similarly electrically coupled to the drain terminal of cross-coupled latch transistor 771. The drain terminal of cross-coupled latch transistor 771 is electrically coupled to the inverse status voltage 730.
The drain terminal of cross-coupled latch transistor 771 is electrically coupled to a drain terminal of a first NMOS transistor 723. The first NMOS transistor 723 has a source terminal electrically coupled to a drain terminal of a second NMOS transistor 724. The first NMOS transistor 723 has a gate terminal electrically coupled to the drain terminal of the first cross-coupled latch transistor 771. The second NMOS transistor has a gate terminal electrically coupled to a power-down input signal 731 and a source terminal electrically coupled to both a gate and a drain terminal of a grounding NMOS transistor 781, which has a source terminal electrically coupled to the electrical ground 735.
Similarly, the drain terminal of cross-coupled latch transistor 772 is electrically coupled to both a drain terminal and a gate terminal of a third NMOS transistor 725. The third NMOS transistor 725 has a source terminal electrically coupled to a drain terminal of a fourth NMOS transistor 726. The fourth NMOS transistor has a gate terminal electrically coupled to an inverse status voltage signal 733 and a source terminal electrically coupled to both a gate and a drain terminal of the grounding NMOS transistor 781.
In some embodiments, the power-down control circuit 800 comprises a cross-latch comprising a first cross-latch transistor 811 and a second cross-latch transistor 812. A source terminal of each cross-latch transistor 811 and 812 is electrically coupled to a supply voltage 834. A gate terminal of cross-latch transistor 811 is electrically coupled to a drain terminal of cross-latch transistor 812, and a gate terminal of cross-latch transistor 812 is electrically coupled to a drain terminal of cross-latch transistor 811.
The drain terminal of cross-latch transistor 811 is electrically coupled to a drain of a first buffer transistor 813, which has a gate voltage electrically coupled to the supply voltage 834. The buffer transistor 813 has a source terminal electrically coupled to a drain terminal of a grounding transistor 814, which has a source terminal electrically coupled to the high-ground 835 and a gate terminal electrically coupled to a power down input signal 831.
The drain terminal of cross-latch transistor 812 is electrically coupled to a drain of a first buffer transistor 815, which has a gate voltage electrically coupled to the supply voltage 834. The buffer transistor 815 has a source terminal electrically coupled to a drain terminal of a grounding transistor 816, which has a source terminal electrically coupled to the high-ground 835 and a gate terminal electrically coupled to an inverse power down input signal 832.
The source terminal of the buffer transistor 815 is electrically coupled to a gate terminal of an inverse status voltage signal driver transistor 817, which has a source terminal electrically coupled to the supply voltage 834 and a drain terminal electrically coupled to the drain terminal of the cross-latch transistor 811.
The source terminal of the buffer transistor 813 is electrically coupled to a gate terminal of a status voltage signal driver transistor 818, which has a source terminal electrically coupled to the supply voltage 834 and a drain terminal electrically coupled to the drain terminal of the cross-latch transistor 812.
The drain terminal of the cross-latch transistor 812 is electrically coupled to a gate of an output driver transistor 819 and a gate of an output high-grounding transistor 820. The output driver transistor 819 has a source terminal electrically coupled to the supply voltage 834 and a drain terminal electrically coupled to a drain terminal of the output high-grounding transistor 820. The output high-grounding transistor 820 has a source terminal electrically coupled to the high-ground 835.
During operation, when the power-down input signal 831 is set to high, it pulls the gate voltage of transistor 818 low, which turns transistor 818 on, pulling status voltage 821 high. In some embodiments, the buffer transistors 813 and 815 act as resistors, which ensure that transistors 817 and 818 are activated before the cross-latch transistors 811 and 812 are activated to allow for a fast response to changing input voltage from power-down input voltage signal 831.
The core start-up circuit 1204 also receives the supply voltage 1235 to a first end of a resistive element bank 1209. In some embodiments, the resistive element bank 1209 can be implemented either with resistors or with MOSFET diodes with their drain and source terminals electrically coupled. Implementing the resistive element bank 1209 using MOSFET devices may have the advantage of saving space in some embodiments. The resistive element bank 1209 has a second end, which is electrically coupled to a drain terminal of a third NMOS transistor 1210. The third NMOS transistor 1210 has a source terminal electrically coupled to a gate terminal of the second NMOS transistor 1218. The third NMOS transistor 1210 has a gate terminal electrically coupled to control input voltage 1236. The source terminal of the third NMOS transistor 1210 is also electrically coupled to a drain terminal of a fourth NMOS transistor 1211. The fourth NMOS transistor 1211 has a source terminal electrically coupled to a drain terminal of a second NMOS grounding transistor 1212, which has a source terminal electrically coupled to electronic ground 1234. The second NMOS grounding transistor 1212 also has a gate terminal electrically coupled to the status voltage signal 1203.
The LDO feedback amplifier bias circuit receives the supply voltage 1235 at a source terminal for a first and second PMOS transistors 1213 and 1214, respectively. The first PMOS transistor 1213 and the second PMOS transistor 1214 have gate terminals electrically coupled to the drain terminal of the power control transistor 1221. The gate terminal of PMOS transistor 1214 is electrically coupled to a drain terminal of PMOS transistor 1214. The drain terminal of PMOS transistor 1213 is electrically coupled to a drain terminal of a third grounding NMOS transistor 1215. The third grounding NMOS transistor 1215 has a gate terminal 1216 electrically coupled to the drain terminal of grounding NMOS transistor 1215 and to a gate terminal of the fourth NMOS transistor 1211. The third grounding NMOS transistor 1215 has a source terminal electrically coupled to electronic ground 1234.
Before starting up the circuit, the gate voltage of PMOS transistor 1213 and the gate voltage 1216 for transistors 1211 and 1215 is near to the electronic ground voltage 1234. In this state, PMOS transistor 1213 is turned off and the voltage at the drain terminal of transistor 1210 is near to the supply voltage 1235. The voltage at the gate of transistor 1218 correlates with the control input voltage 1236. Therefore, as the control input voltage 1236 increases, transistor 1218 turns on, which pulls down the gate voltage of transistors 1213 and 1214, turning them both on, resulting in current being injected into grounding transistor 1215 and activating transistor 1214. As current flows through grounding transistor 1215, the voltage 1216 of the gate terminal of transistor 1215 increases, which turns on transistor 1211, resulting in the circuit completing its start-up sequence.
When powering on, the first PMOS transistor 1401 is turned on first, which results in current being injected into the BJT cells 1412. This results in the voltage of the gate of the second PMOS transistor 1402 dropping from its initial state at the supply voltage due to the current draw by the BJT cells 1412. As the gate of PMOS transistor 1402 is electrically coupled to the gate terminal of the first NMOS transistor 1403, the first NMOS transistor 1403 is turned on, which pulls up the gate of the first PMOS transistor 1401, which shuts down the first PMOS transistor 1401 without disturbing the current balance.
Systems and methods as described herein may take a variety of forms. In one example, systems and methods are provided for a circuit for powering a voltage regulator. A voltage regulator circuit has an output electrically coupled to a gate of an output driver transistor, the output driver transistor having a first terminal electrically coupled to a voltage source and a second terminal electrically coupled to a first terminal of a voltage divider, the voltage divider having an second terminal electrically coupled to ground, and the voltage divider having an output of a stepped down voltage. A power control circuitry transistor has a first terminal electrically coupled to the voltage source, the power control circuitry transistor having a second terminal electrically coupled to the gate terminal of the output driver transistor, and the power control circuitry transistor having a gate terminal electrically coupled to a status voltage signal.
In another example, in a method for starting up and powering down a voltage regulator circuit, a reference voltage is generated in a voltage regulator circuit. An output driver transistor is modulated based upon the reference voltage generated by the voltage regulator circuit. A status voltage signal is received, and the output driver transistor is turned on or off based upon the value of the status voltage signal.
As a further example, a circuit includes a voltage divider circuit having a first terminal electrically coupled with a voltage source and a second terminal electrically coupled to ground. A first and second PMOS transistor are included, where the first PMOS transistor has a gate terminal electrically coupled to a midpoint of the voltage divider and a first terminal of a first NMOS transistor of a current-mirror pair, the first NMOS transistor having a second terminal electrically coupled to the voltage source, and the second PMOS transistor having a gate terminal electrically coupled to a gate terminal of the first NMOS transistor and a first terminal of the first PMOS transistor, and the voltage source and a first terminal of the second PMOS transistor as well as a first terminal of a BJT having a first and second terminal. The second terminal of the BJT is electrically coupled to a second terminal of the first PMOS transistor through a resistor. The second terminal of the first PMOS transistor is electrically coupled to a first terminal of the second NMOS transistor of the current-mirror pair. The second NMOS transistor of the current-mirror pair has a second terminal electrically coupled to the voltage source and a gate terminal electrically coupled to the gate terminal of the first NMOS and a first terminal of a power control circuitry PMOS transistor, and the power control circuitry PMOS transistor has a second terminal electrically coupled to the voltage source and a gate terminal electrically coupled to a power-down signal input.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
This application is a continuation of U.S. patent application Ser. No. 17/458,707, filed Aug. 27, 2021, which is incorporated herein by reference in its entirety.
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| Number | Date | Country | |
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| Number | Date | Country | |
|---|---|---|---|
| Parent | 17458707 | Aug 2021 | US |
| Child | 18296474 | US |
