Lead cutter and method of fabricating semiconductor device

Abstract

Aimed at stably forming sheared surfaces of leads of semiconductor devices, and at raising ratio of formation of plated layers onto the sheared surfaces of the leads, a lead cutter has a die 106, and a cutting punch 110 having a cutting edge at least on the surface facing the die, wherein clearance T between the die 106 and the cutting punch 110 is set within the range from not smaller than 2.3% and smaller than 14.0% of the total thickness of the leads to be cut and plated layers formed on the upper and the lower surfaces thereof.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

FIGS. 1A and 1B are sectional views showing a configuration of the lead cutter in one embodiment of the present invention;

FIG. 2 is an enlarged sectional view showing clearance between the cutting punch and the die;

FIG. 3 is a side elevation showing a configuration of a semiconductor device having the outer leads cut in the end portions thereof by the lead cutter in the embodiment of the present invention;

FIG. 4 is a sectional view showing a detail of the outer lead of the semiconductor device shown in FIG. 3;

FIGS. 5A and 5B are enlarged views of the end portion of the outer lead of the semiconductor device shown in FIG. 3;

FIG. 6 is a sectional view showing a state of mounting of a semiconductor device on a mounting board, with the outer lead thereof fixed by a solder fillet to the mounting board;

FIGS. 7A and 7B are sectional views showing a state of mounting of other semiconductor devices onto a mounting board, with the outer leads thereof fixed by a solder fillet to the mounting board;

FIGS. 8A and 8B are drawings showing a method of cutting the outer lead, while punching out a portion destined for producing cut debris;

FIGS. 9A to 9C are drawings showing a method of cutting the outer lead, without punching out the portion destined for producing cut debris, while supporting the cut debris;

FIGS. 10A and 10B are drawings showing another method of cutting the outer lead, without punching out the portion destined for producing cut debris, while supporting the cut debris;

FIGS. 11A and 11B are drawings showing still another method of cutting the outer lead, without punching out the portion destined for producing cut debris, and without supporting the cut debris;

FIG. 12 is a drawing showing an end portion of the outer lead formed by the cutting method shown in FIGS. 11A and 11B;

FIG. 13 is a chart showing results of Example 1;

FIG. 14 is a chart showing results of Example 2; and

FIGS. 15A and 15B are charts showing results of Example 3.

Claims

1. A lead cutter comprising a die, and a cutting punch having a cutting edge at least on the surface facing said die, wherein the clearance between said die and said cutting punch is set within the range from not smaller than 2.3% and smaller than 14.0% of the total thickness of one of the leads to be cut and plated layers formed on the upper and the lower surfaces of said lead.

2. The lead cutter as claimed in claim 1, wherein surface roughness Ra value of said cutting edge is adjusted to 0.05 or smaller.

3. The lead cutter as claimed in claim 1, further comprising a cutoff-side die on which portions of the leads to be cut off from a semiconductor device is placed, wherein said cutting punch further comprises a cutting edge provided on the surface facing said cutoff-side die,the clearance between said cutoff-side die and said cutting punch is set within the range from not smaller than 2.3% and smaller than 14.0% of the total thickness of one of said leads to be cut and plated layers formed on the upper and the lower surfaces of said lead.

4. The lead cutter as claimed in claim 2, further comprising a cutoff-side die on which portions of the leads to be cut off from a semiconductor device is placed, wherein said cutting punch further comprises a cutting edge provided on the surface facing said cutoff-side die,the clearance between said cutoff-side die and said cutting punch is set within the range from not smaller than 2.3% and smaller than 14.0% of the total thickness of one of said leads to be cut and plated layers formed on the upper and the lower surfaces of said lead.

5. The lead cutter as claimed in claim 3, wherein the clearance between said cutoff-side die and said cutting punch is set substantially equal to the clearance between said die and said cutting punch.

6. The lead cutter as claimed in claim 1, further comprising a support component configured as being movable in synchronization with said cutting punch, while supporting the cutoff portions of said leads to be cut off from a semiconductor device, so that said cutoff portions are horizontally kept when said leads are cut using said cutting punch.

7. The lead cutter as claimed in claim 2, further comprising a support component configured as being movable in synchronization with said cutting punch, while supporting the cutoff portions of said leads to be cut off from a semiconductor device, so that said cutoff portions are horizontally kept when said leads are cut using said cutting punch.

8. The lead cutter as claimed in claim 1, further comprising a support component configured as supporting and fixing cutoff portions of said leads to be cut off from a semiconductor device,wherein said cutting punch has an inclined surface ascending in a direction departing from the surface of said cutting punch facing said die, while setting an acute angle ↓ formed between said surface of said cutting punch facing said die and said inclined surface to an angle capable of preventing the surface of said cutting punch opposite to said surface of said cutting punch facing said die from contacting with said portions to be cut off, when said portions to be cut off are cut off from said semiconductor device.

9. The lead cutter as claimed in claim 2, further comprising a support component configured as supporting and fixing cutoff portions of said leads to be cut off from a semiconductor device,wherein said cutting punch has an inclined surface ascending in a direction departing from the surface of said cutting punch facing said die, while setting an acute angle ↓ formed between said surface of said cutting punch facing said die and said inclined surface to an angle capable of preventing the surface of said cutting punch opposite to said surface of said cutting punch facing said die from contacting with said portions to be cut off, when said portions to be cut off are cut off from said semiconductor device.

10. A method of fabricating a semiconductor device comprising: cutting leads of a semiconductor device, each of said leads having plated layers formed on the upper and the lower surfaces thereof, with a lead cutter including a die, and a cutting punch having a cutting edge at least on the surface facing said die, wherein the clearance between said die and said cutting punch is set within the range from not smaller than 2.3% and smaller than 14.0% of the total thickness of one of the leads to be cut and plated layers formed on the upper and the lower surfaces of said lead.

11. The method of fabricating a semiconductor device as claimed in claim 10, wherein the thickness of the plated layers formed on the upper and the lower surfaces of each of said leads is respectively 5 μor smaller.

12. The method of fabricating a semiconductor device as claimed in claim 10, said plated layers are composed of a lead-free solder.

13. The method of fabricating a semiconductor device as claimed in claim 10, said plated layers are composed of nickel/gold, nickel/palladium, or nickel/palladium/gold.