Claims
- 1. An integrated circuit comprising:
a core block comprised of a plurality of high threshold voltage (high-Vt) field effect transistor (FET) devices; a peripheral block comprised of a plurality of low threshold voltage (low-Vt) FET devices; and at least one switch coupled to the peripheral block and operable to power on or off the peripheral block.
- 2. The integrated circuit of claim 1, wherein the peripheral block is powered on in an operational mode and powered off in a standby mode.
- 3. The integrated circuit of claim 1, further comprising:
a retention block comprised of at least one FET device operable to maintain at least one control signal at a predetermined level when the peripheral block is powered off.
- 4. The integrated circuit of claim 1, wherein the core block includes memory cells and the peripheral block includes support circuitry for the memory cells.
- 5. The integrated circuit of claim 1, wherein the core block is directly coupled to a power supply and circuit ground.
- 6. The integrated circuit of claim 1, wherein the at least one switch includes a head switch coupled between a power supply and the peripheral block.
- 7. The integrated circuit of claim 6, wherein the at least one switch further includes a foot switch coupled between the peripheral block and circuit ground.
- 8. A memory unit comprising:
a core block comprised of a plurality of high threshold voltage (high-Vt) field effect transistor (FET) devices configured to implement memory cells; a peripheral block comprised of a plurality of low threshold voltage (low-Vt) FET devices configured to implement support circuitry for the memory cells; and at least one switch coupled to the peripheral block and operable to power on or off the peripheral block.
- 9. The memory unit of claim 8, wherein the memory unit is implemented as static random access memory (SRAM).
- 10. The memory unit of claim 8, wherein the memory unit is implemented as dynamic random access memory (DRAM).
- 11. The memory unit of claim 8, further comprising:
a retention block operable to maintain a set of control signals at a predetermined level when the peripheral block is powered off.
- 12. The memory unit of claim 11, wherein the retention block comprises a plurality of pull-up FET devices operable to maintain the set of control signals at the predetermined level to retain data within the memory cells.
- 13. The memory unit of claim 11, wherein the set of control signals is a set of word lines for the memory cells and is maintained at logic low when the peripheral block is powered off.
- 14. The memory unit of claim 8, wherein the at least one switch includes
a head switch coupled between a power supply and the peripheral block, and a foot switch coupled between the peripheral block and circuit ground.
- 15. The memory unit of claim 8, wherein the memory cells are dual-bank memory cells.
- 16. The memory unit of claim 8, wherein the peripheral block includes word line drivers for the memory cells in the core block.
- 17. The memory unit of claim 8, wherein a clock signal for the peripheral block is disabled Tpd seconds prior to powering down the peripheral block and is enabled Tup seconds after powering up the peripheral block, where Tpd and Tup each denotes a non-zero time period.
- 18. A wireless device comprising an integrated circuit having
a core block comprised of a plurality of high threshold voltage (high-Vt) field effect transistor (FET) devices; a peripheral block comprised of a plurality of low threshold voltage (low-Vt) FET devices; and at least one switch coupled to the peripheral block and operable to power on or off the peripheral block.
- 19. The wireless device of claim 18, wherein the integrated circuit further includes a retention block operable to maintain at least one control signal at a predetermined level.
- 20. The wireless device of claim 18, wherein the integrated circuit implements a static random access memory (SRAM).
- 21. The wireless device of claim 18, wherein the integrated circuit implements a digital signal processor (DSP).
- 22. The wireless device of claim 18, wherein the integrated circuit implements a controller.
- 23. The wireless device of claim 18 and operable in a code division multiple access (CDMA) communication system.
- 24. An apparatus comprising:
a core block comprised of a plurality of high threshold voltage (high-Vt) field effect transistor (FET) devices; a peripheral block comprised of a plurality of low threshold voltage (low-Vt) FET devices; means for powering on and off the peripheral block; and means for maintaining at least one control signal at a predetermined level when the peripheral block is powered off.
- 25. A method of operating an integrated circuit, comprising:
maintaining power to a core block comprised of a plurality of high threshold voltage (high-Vt) field effect transistor (FET) devices; powering on a peripheral block with at least one switch in an operational mode, wherein the peripheral block comprises a plurality of low threshold voltage (low-Vt) FET devices; and powering off the peripheral block with the at least one switch in a standby mode.
- 26. The method of claim 25, further comprising:
maintaining internal states of the core block when the peripheral block is powered off.
- 27. The method of claim 25, further comprising:
maintaining at least one control signal for the core block at a predetermined level with a retention block when the peripheral block is powered off.
- 28. The method of claim 25, further comprising:
preparing the peripheral block to transition between a power-on state and a power-off state.
- 29. The method of claim 25, wherein the core block includes memory cells and the peripheral block includes support circuitry for the memory cells.
Parent Case Info
[0001] This application claims the benefit of provisional U.S. Application Serial No. 60/460,157, entitled “SRAM Leakage Reduction,” filed Apr. 2, 2003.
Provisional Applications (1)
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Number |
Date |
Country |
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60460157 |
Apr 2003 |
US |