Learning aid or game having miniature electronic speech synthesis chip

BACKGROUND OF THE INVENTION
This invention relates to electronic learning aids, teaching machines and electronic games. More particularly, this invention relates to electronic learning aids, teaching machines or games having means for producing synthesized speech implemented in a minature semiconductor chip.
In the prior art various electronic teaching devices and games are known. For example, a small electronic learning aid for teaching arithmetic to children using randomly selected problems is disclosed in U.S. Pat. No. 3,584,398. Further, teaching machines are known which rely on traditional movie film or video tape techniques for presenting both audio and visual information to a student and would include means for posing questions to the student and receiving and correcting answers from the student. A proposal for such an automatic teaching device is found in the Paul K. Weimer article in "IRE Transactions on Education" of June 1958. It should be evident, however, that a teaching machine employing movie projectors or video tape machines is bulky, heavy and fairly expensive to manufacture. Furthermore, it is desirable to at least partially randomize the questions posed by the learning aid; this function is, of course, difficult to implement using conventional audio or video tape machines or movie projectors.
The prior art also suggests various techniques for synthesizing human speech from digital data. For instance, some of the techniques used are briefly described in "Voice Signals: Bit by Bit" at pages 28-34 of the Oct. 1973 issue of IEEE Spectrum. An important technique for synthesizing human speech, and the technique used by the speech synthesizer chip described herein, is called linear predictive coding. For a detailed discussion of this technique, see "Speech Analysis and Synthesis by Linear Prediction of the Speech Wave" by B. S. Atal and Suzanne L. Hanauer which appears at pp. 637-50 of Volume 50, No. 2 (part 2) (1971) of the Journal of the Acoustical Society of America.
In U.S. patent application Ser. No. 807,461 filed June 17, 1977, abandoned in favor of continuation application Ser. No. 905,328 filed May 12, 1978, now U.S. Pat. No. 4,209,844 issued June 24, 1980, a lattice filter capable of being implemented on a single semiconductor chip as described. The speech synthesis chip described herein makes use of the lattice filter described in the aforementioned U.S. Pat. No. 4,209,844.
It is one object of this invention that the learning aid or game be equipped to audibly ask questions of the user thereof.
It is another object of this invention that the teaching machine receive an answer to a posed question from the opertor and to inform the operator whether or not the inputted answer is correct.
It is still yet another object of this invention that the questions posed be randomly selectable.
It is yet another object of this invention that speech synthesis circuits be implemented on a miniature semiconductor chip so that the entire talking learning aid be simply constructable as a portable device.
The foregoing objects are achieved as is now described. The questions to be posed by the machine are stored as digital codes in a memory device. This memory is preferably of the non-volatile type so that the questions posed are not erased when power is disconnected from the apparatus. A speech synthesizer circuit is connected to the output of the memory for selectively converting the digital signals stored therein to speech signals from which audible speech is generated. Several types of speech synthesis circuits are known. In the disclosed embodiment, the speech synthesizer is implemented using linear predictive coding and integrated on a single semiconductor chip. A speaker or earphone and an amplifier (if needed) are provided to convert the output from the speech synthesizer to audible sounds. A keyboard and display, both of which preferably are capable of accommodating alphanumeric characters, are preferably provided. The display and keyboard are preferably coupled to the speech synthesis circuit and memory via a controller circuit. In the embodiment disclosed, the controller circuit is an appropriately programmed microprocessor device. The controller circuit controls the memory to read out the digital signals corresponding to a question to be posed, the question preferably being randomly selected from a plurality of questions stored therein. The question posed is converted to audible signals by means of the synthesizer circuit in combination with the speaker or earphone. The memory also preferably stores data indicative of the correct answer to the question posed, which data is supplied to the controller circuit. When the operator answers the questions posed by inputting his or her answer at the keyboard, the controller compares the inputted answer with the answer stored in the memory and the operator is informed of the results of this comparison. The operator may be so informed either visually via the display or audibly via the speech synthesis circuit and speaker or earphone, to inform the operator "very good", for example, if the operator gave an incorrect answer. The question posed may, of course, be either a rather complex, lengthy question or alternatively, as in the case of the disclosed embodiment, may be as simple as speaking a word and awaiting a correct spelling thereof. Of course, the shorter the questions posed the greater the number of questions storable in a memory of given capacity. The learning aid is preferably arranged to have several levels of difficulty. Thus the easiest level might have such words as "dog", "cat", "time", and the like while the next level might have words such as "mother", "flower", and the like and so forth. Of course, the particular words selected for any given library are a design choice. The controller circuit preferably controls from which difficulty level the posed question is to be randomly selected. The particular difficulty level used is selected based on instructions inputted at the keyboard or by other means. After the operator gives a correct answer, e.g. the correct spelling of the word "spoken" then the learning aid goes on to preferably select another random word. When an incorrect answer is given, the controller circuit preferably causes the word to be posed again after the operator is informed that the answer is incorrect and if the operator continues to give an incorrect answer, the controller circuit provides via the display or the speech synthesis circuit the correct answer and then goes on to randomly select another word or question to be posed. The learning aid is installed in an easily portable case. The size of the speech synthesis chip is on the order of 45,000 square mils using conventional MOS design rules and a conventional P-MOS processing technique. Of course, using C-MOS processing would tend to increase the size of the chip somewhat.
In the embodiment disclosed, the learning aid is preferably equipped with other modes of operation which are described in detail.

BRIEF DESCRIPTION OF THE DRAWINGS
The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objects and advantages thereof, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
FIG. 1 is a front view of a talking learning aid;
FIG. 2 depicts the segment details of the display;
FIG. 3 is a block diagram of the major components preferably making up the learning aid;
FIG. 4a and 4b form a composite block diagram (when placed side by side) of the speech synthesizer chip;
FIG. 5 is a timing diagram of various timing signals preferably used on the synthesizer;
FIG. 6 pictorially shows the data compression scheme preferably used to reduce the data rate required by the synthesizer;
FIGS. 7a-7d form a composite logic diagram of the synthesizer's timing circuits;
FIGS. 8a-8f form a composite logic diagram of the synthesizer's ROM/Controller interface logics;
FIGS. 9a-9d form a composite logic diagram of the interpolator logics;
FIGS. 10a-10c form a composite logic diagram of the array multiplier;
FIGS. 11a-11d form a composite logic diagram of the speech synthesizer's lattice filter and excitation generator;
FIGS. 12a and 12b are schematic diagrams of the parameter RAM;
FIGS. 13a-13c are schematic diagrams of the parameter ROM;
FIGS. 14a-14b form a composite diagram of the chirp ROM;
FIGS. 15a-15b form a composite block diagram of a microprocessor which may be utilized as the controller;
FIGS. 16a-16c form a composite logic diagram of the segment decoder of the microprocessor;
FIG. 17 depicts the digit output buffers and digit registers of the microprocessor;
FIG. 18 depicts the KB selector circuit of the microprocessor;
FIG. 19 is a block diagram of a ROM employed as a memory of the talking learning aid;
FIGS. 20a-20f form a composite logic diagram of the control logic for the ROM of FIG. 19;
FIGS. 21a and 21b form a composite logic diagram of the X and Y address decoders and the array of memory cells;
FIG. 22 is a plan view of the synthesizer chip herein described, showing the metal mask or metal pattern, enlarged about fifty times; and
FIGS. 23a-23b depict embodiments of the voice coil connection.

GENERAL DESCRIPTION
FIG. 1 is a front view of a talking learning aid of the type which may embody the present invention. The learning aid includes a case 1 which encloses electronic circuits preferably implemented on integrated circuits (not shown in this figure). These circuits are coupled to a display 2, a keyboard 3 and a speaker 4 or other voice coil means (also not shown in FIG. 1). However, the openings 4a are shown behind which speaker 4 is preferably mounted. The display is preferably of the vacuum fluorescent type in the embodiment to be described; however, it will be appreciated by those skilled in the art that other display means, such as arrays of light emitting diodes, liquid crystal devices, electrochromic devices, gas discharge devices or other display means alternatively may be used if desired. Also, in this embodiment, as a matter of design choice, the display has eight character positions. The keyboard 3 of the learning aid of this embodiment has forty key switch positions, twenty-six of which are used to input the letters of the alphabet into the learning aid. Of the remaining fourteen key switch positions, five are utilized for mode keys (on/spelling mode, learn mode, word guesser game mode, code breaker mode and random letter mode), another five are used to control functions performed by the learning aid in its modes (enter, say again, replay, erase and go) and the remaining four are used for an apostrophe key, a blank space key, a word list select key and an off key. The words spoken by the learning aid, as well as the correct spelling of those words, are stored as digital information in one or more Read-Only-Memories.
The learning aid depicted in FIG. 1 may be battery powered or powered from a source of external electrical power, as desired. The case is preferably made from injection molded plastic and the keyboard switches may be provided by two 5 by 8 arrays of key switches of the type disclosed in U.S. Pat. No. 4,005,293, if desired. Of course, other types of case materials or switches alternatively may be used.
Having described the outward appearance of the learning aid, the modes in which the learning aid may operate will be first described followed by a description of the block diagrams and detailed logic diagrams of the various electronic circuits used to implement the learning aid of FIG. 1.
MODES OF OPERATION
The learning aid of this embodiment has five modes of operation which will be subsequently described. It will be evident to those skilled in the art, however, that these modes of operation may be modified, reduced in number or expanded in capability. As a matter of design choice, the present talking and learning aid is provided with the following modes of operation.
The first mode, the spelling mode, is automatically entered when the "on" key is depressed. In the spelling mode the learning aid randomly selects ten words from a selected word list and at a selected difficulty category within the selected word list. The word list may be changed by depressing the "word list select" key which is coupled to a software implemented flip flop circuit which flips each time the "word list select" key is depressed. The word list select flip flop then determines, as will be seen, which pair of read-only-memories from which the ten words will be randomly selected. Each word list preferably includes words arranged in four levels of difficulty. This embodiment of the learning aid automatically enters the least difficult level of difficulty. The fact that the least difficulty level has been selected is shown by displaying "SPELL A" in display 2. The level difficulty may be increased by depressing the B, C or D keys, and display 2 will show, in response, "SPELL B", "SPELL C" or "SPELL D", respectively. Having selected the word list and level difficulty, the "go" key is depressed upon which the learning aid commences to randomly select ten words and to say the word "spell" followed by the first randomly selected word. A dash, that being segment D in display 2 (FIG. 2), comes up in the left hand most character position. At this time the student may either (1) enter his or her spelling of the word and then depress the "enter" key or (2) depress the "say again" key. The student may also depress the "erase" key if he or she realizes that the spelling being inputted is incorrect before having depressed the "enter" key; the student may then again try to input the correct spelling. The "say again" key causes the word to be spoken by the learning aid again. In some embodiments a subsequent depression of the "say again" key may cause the selected word to be repeated once more, however, then at a slower rate. As the student enters his or her spelling of the word using the alphabet keys at keyboard 3, the inputted spelling appears at display 2 and the character position of the display 2 shifts from left to right as the letters are inputted. Following the depression of the "enter" key, the learning aid compares the student's spelling with a correct spelling, which is stored in one of the Read-Only-Memories, and verbally indicates to the student whether the student spelling was correct or incorrect. The verbal response is also stored as digital information in a Read-Only-Memory. Of course, a visual response may likewise or alternatively be used, if desired. In this embodiment the student is given two opportunities to spell the word correctly and if the student has still failed to correctly spell the word, the learning aid then verbally (via speaker 4) and visually (via display 2) spells the word for the student and goes on to the next word from the group of ten randomly selected words.
At the end of the test of the spelling of the ten randomly selected words, the learning aid then verbally and visually indicates the number of right and wrong answers. Further, in order to give the student additional reinforcement, the learning aid preferably gives a audible response which is a function of the correctness of the spellings. In this embodiment the learning aid plays a tune, the number of notes of which is a function of the correctness of the student's spellings for the group of selected words. The use of the "enter", "say again", "erase", and "go" function keys has just been described with reference to the spelling mode of operation. There is an additional function key, "replay", whose function has not yet been described. The "replay" key causes the learning aid to repeat the group of ten randomly selected words after the group has been completed or causes the learning aid to start over with the first word of the group of ten words if it is depressed during the progression through the group. Alternatively, at the end of a group of ten words, the student may depress the "go" key which initiates the random selection of another group of ten words from the selected word list.
An exemplary set of spell mode problems is shown in Table I; exemplary key depressions, which a student might make during the exemplary set of problems, are listed along with the responses made by the learning aid at display 2 and speaker 4.
The learn mode is entered by depressing the "learn" key. In the learn mode, after the "go" key is depressed the learning aid randomly selects ten words from the selected word list at the selected difficulty level and then proceeds to display the first randomly selected word at display 2 and approximately one second later to speak "say it". Approximately two seconds thereafter the learning aid proceeds to pronounce the word shown in display 2. During this interval the student is given the opportunity to try to pronounce the word spelled at display 2; the learning aid then goes on to demonstrate how the word should be pronounced. After going through the ten randomly selected words the learning automatically returns to the aforementioned spell mode, but the ten words tested during the spell mode are the ten words previously presented during the learn mode. While in the learn mode the "say again", "erase", "repeat" and "enter" keys are invalid. The difficulty level is selected as in the spelling mode, but in the learn mode the learning aid displays the various levels as "SAY IT A", "SAY IT B", etc. Depressing the "go" key causes the learning aid to select another group of ten words in the learn mode. An exemplary set of learn mode problems is set forth in Table II.
The word guesser mode is entered by depressing the "word guesser" mode key. In the word guesser mode the learning aid randomly selects a word from the selected word list and displays dashes in a number of character positions at display 2, the number of character positions corresponding to the number of letters in the randomly selected word. Thus, if the learning aid randomly selects the word "course" for instance, then the dashes will appear in six of the eight character positions in display 2, starting with the left most position and proceeding to the right for six character positions. The dash is shown in the characters of the display by energizing the D segments in those character positions (see FIG. 2). The child may then proceed to enter his or her guesses of the letters in the randomly selected word by depressing the letter keys at keyboard 3. For a correct choice, the learning aid gives an audible response of four tones and shows every place the chosen letter occurs in the randomly selected word. Once letters have been correctly guessed, they remain in the display until the end of the game. For incorrect guesses the learning aid preferably makes no response, but may alternatively say something like "incorrect guess." In this embodiment the child is given six incorrect guesses. Upon the seventh incorrect guess the learning says "I win". On the other hand, if the child correctly guesses all the letters before making seven incorrect guesses the learning aid speaks "you win" and gives an audible response of four tones. Thus in the word guesser mode, the learning aid permits the child to play the traditional spelling game known as "hangman" either by himself or herself or along with other children. Exemplary word guesser problems are set forth in Table III.
The disclosed learning aid has another mode of operation known as "code breaker" which is entered by depressing the "code breaker" mode key. In this mode the child may enter any word of his or her choice and upon depressing the "enter key" the letters in the display are exchanged according to a predetermined code. Thus, in the code breaker mode the learning aid may be used to encode words selected by the child. Further in the code breaker mode the learning aid may be used to decode the encoded words by entering the encoded word and depressing the "enter key".
Another mode with which the learning aid may be provided is the "random letter" mode which is entered by depressing the "random letter" key. In the random letter mode the learning aid automatically displays in response to depression of the "go" key a randomly selected letter of the alphabet in the first character position of display 2. The letters of the alphabet occur in approximate proportion to the frequency of their occurrence in the English language; thus, the more commonly letters are displayed more frequently than uncommonly used letters. If the "go" key is again depressed then another randomly selected letter is displayed in the first character position and the previously selected letter moves right to the second character position and so forth in response to further depressions of the "random letter" key.
Referring now to FIG. 2, there is shown a preferred arrangement of the segments of display 2. Display 2 preferably has eight character positions each of which is provided by a sixteen segment character which has fourteen segments arranged somewhat like a "British flag" with an additional two segments for an apostrophe and a decimal point. In FIG. 2, segments A-N are arranged more or less in the shape of the "British flag" while segment AP provides apostrophe and segment DP provides a decimal point. Segment conductors Sa through Sn, Sdp and Sap are respectively coupled to segments A through N, DP and AP in the eight character positions of display 2. Also, for each character position, there is a common electrode, labeled as D1-D8. When display 2 is provided by a vacuum fluorescent display device, the segment electrodes are provided anodes in the vacuum fluorescent display device while each common electrode is preferably provided by a grid associated with each character position. By appropriately multiplexing signals on the segment conductors (Sa-Sn, Sdp and Sap) with signals on the character common electrodes (D1-D8) the display may be caused to show the various letters of the alphabet, a period, and an apostrophe and various numerals. For instance, by appropriately energizing segment conductors A,B,C, E,F,G and H when character common electrode D1 is appropriately energized the letter A is actuated in the first character position of display 2. Further, by appropriate strobing of segment conductors A,B,C,D,H,I and J when character common electrode D2 is appropriately energized, the letter B is caused to be actuated in the second character position of display 2. It should be evident to those skilled in the art that the other letters of the alphabet as well as the apostrophe, period and numerals may be formed by appropriate energization of appropriate segment conductors and common electrodes. In operation, the character common electrodes D1-D8 are sequentially energized with an appropriate voltage potential as selected segment conductors are energized to their appropriate voltage potential to produce a display of characters at display 2. Of course, the segment electrodes could alternatively be sequentially energized as the digit electrodes are selectively energized in producing a display at display 2.
BLOCK DIAGRAM OF THE LEARNING AID
FIG. 3 is a block diagram of the major components making up the disclosed embodiment of a speaking learning aid. The electronics of the disclosed learning aid may be divided into three major functional groups, one being a controller 11, another being a speech synthesizer 10, and another being a read-only-memory (ROM) 12. In the embodiment disclosed, these major electronic functional groups are each integrated on separate integrated circuit chips except for the ROM functional group which is integrated onto two integrated circuit chips. Thus, the speech synthesizer 10 is preferably implemented on a single integrated circuit denoted by the box labeled 10 in FIG. 3 while the controller is integrated on a separate integrated circuit denoted by a box 11 in FIG. 3. The word list for the learning aid is stored in the ROM functional group 12, which stores both the correct spellings of the words as well as frames of digital coding which are converted by speech synthesizer 10 to an electrical signal which drives speaker or other voice coil means 4. In the embodiment disclosed, ROM functional group 12 is preferably provided with 262,144 bits of storage. As a matter of design choice, the 262,144 bits of data are divided between two separate read-only-memory chips, represented in FIG. 3 at numerals 12A and 12B. The memory capacity of ROM functional group 12 is a design choice; however, using the data compression features which are subsequently discussed with reference to FIG. 6, the 262,144 bits of read-only-memory may be used to store on the order of 250 words of spoken speech and their correct spellings as well as various tones, praise phases and correction phases spoken by the learning aid.
As is discussed with reference to FIG. 1, the "word list select" key causes the learning aid to select words from another word list. In FIG. 3, the basic word list used with the learning aid is stored in ROMs 12A and 12B along with their spellings and appropriate phraseology which the learning aid speaks during its different modes of operation. The second word list, which may be selected by depressing the "word list select" key, is preferably stored in another pair of ROMs 13A and 13B. In FIG. 3 these are depicted by dashed lines because these read-only-memories are preferably plugged into the learning aid by a person using the system (of course, when children use the system it is preferable that an adult change the read-only-memories since children may not have the required manual dexterity) rather than normally packaged with the learning aid. In this manner many different "libraries" of word lists may be made available for use with the learning aid.
Of course, the number of chips on which the learning aid is implemented is a design choice and as large scale integration techniques are improved (using electron beam etching and other techniques), the number of integrated circuit chips may be reduced from four to as few as a single chip.
Synthesizer chip 10 is interconnected with the read-only-memories via data path 15 and is interconnected with controller 11 via data path 16. The controller 11, which may be provided by an appropriately programmed microprocessor type device, preferably actuates display 2 by providing segment information on segment conductors Sa-Sn, Sdp and Sap along with character position information on connectors D1-D8. In the embodiment herein disclosed, controller 11 preferably also provides filament power to display 2 when a vacuum fluorescent device is used therefor. Of course, if a liquid crystal, electrochromic, light emitting diode or gas discharge display were used such filament power would not be required. Controller 11 also scans keyboard 3 for detecting key depressions thereat. Keyboard 3 has forty switch positions which are shown in representative form in FIG. 3, the switch locations occurring where the conductors cross within the dashed line at numeral 3 in FIG. 3. A switch closure causes the conductors shown as crossing in FIG. 3 to be coupled together. At numeral 3' the switch occurring at a crossing of conductors at numeral 3 is shown in detail. In addition to actuating display 2 and sensing key depression at keyboard 3, controller 11 also performs such functions as providing addresses for addressing ROMs 12A and 12B (via synthesizer 10), comparing the correct spellings from ROMs 12A or 12B with spellings input by a student at keyboard 3, and other such functions which will become apparent. Addresses from controller 11 are transmitted to ROMs 12A and 12B by synthesizer 10 because, as will be seen, synthesizer 10 preferably is equipped with buffers capable of addressing a plurality of read-only-memories. Preferably, only one of the pairs of ROMs will output information in response to this addressing because of a chip select signal which is transmitted from synthesizer 10 to all the Read-Only-Memories. Controller 11, in this embodiment, transmits addresses to the ROMs via synthesizer 10 so that only synthesizer 10 output buffers need be sized to transmit addresses to a plurality of ROMs simultaneously. Of course, controller 11 output buffers could also be sized to transmit information to a plurality of read-only-memories simultaneously and thus in certain embodiments it may be desirable to also couple controller 11 directly to the ROMs.
As will be seen, synthesizer chip 10 synthesizes human speech or other sounds according to frames of data stored in ROMs 12A-12B or 13A-13B. The synthesizer 10 employs a digital lattice filter of the type described in U.S. Pat. No. 4,209,844. U.S. Pat. No. 4,209,844 is hereby incorporated herein by reference. As will also be seen, synthesizer 10 also includes a digital to analog (D to A) converter for converting the digital output from the lattice filter to analog signals for driving speaker 4 or other voice coil means with those analog signals. Synthesizer 10 also includes timing, control and data storage and data compression systems which will be subsequently described in detail.
SYNTHESIZER BLOCK DIAGRAM
FIGS. 4a and 4b form a composite block diagram of the synthesizer 10. Synthesizer 10 is shown as having six major functional blocks, all but one of which are shown in greater detail in block diagram form in FIGS. 4a and 4b. The six major functional blocks are timing logic 20; ROM-Controller interface logic 21; parameter loading, storage and decoding logic 22; parameter interpolator 23; filter and excitation generator 24 and D to A and output section 25. Subsequently, these major functional blocks will be described in detail with respect to FIGS. 5, 6, 7a-7d, 8a-8f, 9a-9d, 10a-10c, and 11a-11d.
Rom/Controller Interface Logic
Referring again to FIGS. 4a and 4b, ROM/Controller interface logic 21 couples synthesizer 10 to read-only-memories 12A and 12B and to controller 11. The control 1-8 (CTL1-CTL8), chip select (CS) and processor data clock (PDC) pins are coupled, in this embodiment, to the controller while the address 1-8 (ADD1-ADD8) and instruction 0-1 (I0-I1) pins are connected to ROMs 12A and 12B (as well as ROMs 13A-13B, if used). ROM/Controller interface logic 21 sends address information from controller 11 to the Read-Only-Memories 12A-12B and preferably returns digital information from the ROMs back to the controller 11; logic 21 also brings data back from the ROMs for use by synthesizer 10 and initiates speech. A Chip Select (CS) signal enables tristate buffers, such as buffers 213, and a three bit command latch 210. A Processor Data Clock (PDC) signal sets latch 210 to hold the data appearing at CTL1-CTL4 pins from the controller. Command latch 210 stores a three bit command from controller 11, which is decoded by command decoder 211. Command decoder 211 is responsive to eight commands which are: speak (SPK) or speak slowly (SPKSLW) for causing the synthesizer to access data from the Read-Only-Memory and speak in response thereto either at a normal rate or at a slow rate; a reset (RST) command for resetting the synthesizer to zero; a test talk (TSTTALK) so that the controller can assertain whether or not the synthesizer is still speaking; a load address (LA) where four bits are received from the controller chip at the CTL1-CTL8 pins and transferred to the ROMs as an address digit via the ADD1-ADD8 pins and associated buffers 214; a read and branch (RB) command which causes the Read-Only-Memory to take the contents of the present and subsequent address and use that for a branch address; a read (RE) command which causes the Read-Only-Memory to output one bit of data on ADD1, which data shifts into a four bit data input register 212; and an output command which transfers four bits of data in the data input register 212 to controller 11 via buffers 213 and the CTL1-CTL8 pins. Once the synthesizer 10 has commenced speaking in response to a SPK or SPKSLOW command it continues speaking until ROM interface logic 21 encounters a RST command or an all ones gate 207 (see FIGS. 8a-8f) detects an "energy equal to fifteen" code and resets talk latch 216 in response thereto. As will be seen, an "energy equal to 15" code is used as the last frame of data in a plurality of frames of data for generating words, phases or sentences. The LA, RE and RB commands decoded by decoder 211 are re-encoded via ROM control logic 217 and transmitted to the read-only-memories via the instruction (I0-I1) pins.
The processor Data Clock (PDC) signal serves other purposes than just setting latch 210 with the data on CTL1-CTL4. It signals that an address is being transferred via CTL1-CTL8 after an LA or OUTPUT command has been decoded or that the TSTTALK test is to be performed and outputted on pin CTL8. A pair of latches 218a and 218b (FIGS. 8a-8f) associated with decoder 211 disable decoder 211 when the aforementioned LA, TSTTALK and OUTPUT commands have been decoded and a subsequent PDC occurs so that the data then on pins CTL1-CTL8 is not decoded.
A TALK latch 216 is set in response to a decoded SPK or SPKSLW command and is reset: (1) during a power up clear (PUC) which automatically occurs whenever the synthesizer is energized; (2) by a decoded RST command or (3) by an "energy equals fifteen" code in a frame of speech data. The TALKD output is delayed output to permit all speech parameters to be inputed into the synthesizer before speech is attempted. The slow talk latch 215 is set in response to a decoded SPKSLW command and reset in the same manner as latch 216. The SLOWD output is similarly a delayed output to permit all the parameters to be inputted into the synthesizer before speech is attempted.
Parameter Loading, Storage and Decoding Logic
The parameter loading, storage and decoding logic 22 includes a six bit long parameter input register 205 which receives serial data from the read-only-memory via pin ADD1 in response to a RE command outputted to the selected read-only-memory via the instruction pins. A coded parameter random access memory (RAM) 203 and condition decoders and latches 208 are connected to receive the data inputted into the parameter input register 205. As will be seen, each frame of speech data is inputted in three to six bit portions via parameter input register 205 to RAM 203 in a coded format where the frame is temporarily stored. Each of the coded parameters stored in RAM 203 is converted to a ten bit parameter by parameter ROM 202 and temporarily stored in a parameter output register 201.
As will be discussed with respect to FIG. 6, the frames of data may be either wholly or partially inputted into parameter input register 205, depending upon the length of the particular frame being inputted. Condition decoders and latches 208 are responsive to particular portions of the frame of data for setting repeat, pitch equal zero, energy equal zero, old pitch and old energy latches. The function of these latches will be discussed subsequently with respect to FIGS. 8a-8f. The condition decoders and latches 208 as well as various timing signals are used to control various interpolation control gates 209. Gates 209 generate an inhibit signal when interpolation is to be inhibited, a zero parameter signal when the parameter is to be zeroed and a parameter load enable signal which, among other things, permits data in parameter input register 205 to be loaded into the coded parameter RAM 203.
Parameter Interpolator
The parameters in parameter output register 201 are applied to the parameter interpolator functional block 23. The inputted K1-K10 speech parameters, including speech energy are stored in a K-stack 302 and E10 loop 304, while the pitch parameter is stored in a pitch register 305. The speech parameters and energy are applied via recoding logic 301 to array multiplier 401 in the filter and excitation generator 24. As will be seen, however, when a new parameter is loaded into parameter output register 201 it is not immediately inserted into K-stack 302 or E10 loop 304 or register 305 but rather the corresponding value in K-stack 302, E10 loop 304 or register 305 goes through eight interpolation cycles during which a portion of the difference between the present value in the K-stack, 302 E10 loop 304 or register 305 and the target value of that parameter in parameter output register 201 is added to the present value in K-stack 302, E10 loop 304 or register 305.
Essentially the same logic circuits are used to perform the interpolation of pitch, energy and the K1-K10 speech parameters. The target value from the parameter output register 201 is applied along with the present value of the corresponding parameter to a subtractor 308. A selector 307 selects either the present pitch from pitch logic 306 or present energy or K coefficient data from KE10 transfer register 303, according to which parameter is currently in parameter output register 201, and applies the same to subtractor 308 and a delay circuit 309. As will be seen, delay circuit 309 may provide anywhere between zero delay to three bits of delay. The output of delay circuit 309 as well as the output of subtractor 308 is supplied to an adder 310 whose output is applied to a delay circuit 311. When the delay associated with delay circuit 309 is zero the target value of the particular parameter in parameter output register 201 is effectively inserted into K-stack 302, E10 loop 304 or pitch register 305, as is appropriate. The delay in delay circuit 311 is three to zero bits, being three bits when the delay in the delay circuit 309 is zero bits, whereby the total delay through selector 307, delay circuits 309 and 311, adder 310 and subtractor 308 is constant. By controlling the delays in delay circuits 309 and 311, either all, 1/2, 1/4 or 1/8 of the difference outputted from subtractor 308 (that being the difference between the target value and the present value) is added back into the present value of the parameter. By controlling the delays in the fashion set forth in Table IV, a relatively smooth eight step parameter interpolation is accomplished.
U.S. Pat. No. 4,209,844 discusses with reference to FIG. 7 thereof a speech synthesis filter wherein speech coefficients K1-K9 are stored in the K-stack continuously, until they are updated, while the K10 coefficient and the speech energy (referred to by the letter A in U.S. Pat. No. 4,209,844) are periodically exchanged. In parameter interpolator 23, speech coefficients K1-K9 are likewise stored in stack 302, until they are updated, whereas the energy parameter and the K10 coefficient effectively exchange places in K-stack 302 during a twenty time period cycle of operations in the filter and excitation generator 24. To accomplish this function, E10 loop 304 stores both the energy parameter and the K10 coefficient and alternately inputs the same into the appropriate location in K-stack 302. KE10 transfer register 303 is either loaded with the K10 or energy parameter from E10 loop 304 or the appropriate K1-K9 speech coefficient from K-stack 302 for interpolation by logics 307-311.
As will be seen, recoding logic 301 preferably performs a Booth's algorithm on the data from K-stack 302, before such data is applied to array multiplier 401. Recoding logic 301 thereby permits the size of the array multiplier 401 to be reduced compared to the array multiplier described in U.S. Pat. No. 4,209,844.
Filter and Excitation Generator
The filter excitation generator 24 includes the array multiplier 401 whose output is connected to a summer multiplexer 402. The output of summer multiplexer 402 is coupled to the input of summer 404 whose output is coupled to a delay stack 406 and multiplier multiplexer 415. The output of the delay stack 406 is applied as an input to summer multiplexer 402 and to Y latch 403. The output of Y latch 403 is coupled to an input of multiplier multiplexer 415 and is applied as an input to truncation logic 425. The output of multiplier multiplexer 415 is applied as an input to array multiplier 401. As will be seen filter and excitation generator 24 make use of the lattice filter described in U.S. Pat. No. 4,209,844. Various minor interconnections are not shown in FIG. 4b for sake of clarity, but which will be described with reference to FIGS. 10a-10c and 11a-11d. The arrangement of the foregoing elements generally agrees with the arrangement shown in FIG. 7 of U.S. Pat. No. 4,209,844; thus array multiplier 401 corresponds to element 30', summer multiplexer 402 corresponds to elements 37b', 37c' and 37d', gates 414 (FIGS. 11a-11d) correspond to element 33', delay stack 406 corresponds to elements 34' and 35', Y latch 403 corresponds to element 36' and multiplier multiplexer 415 corresponds to elements 38a', 38b', 38c' and 38d'.
The voice excitation data is supplied from unvoiced/voice gate 408. As will be subsequently described in greater detail, the parameters inserted into parameter input register 205 are supplied in a compressed data format. According to the data compression scheme used, when the coded pitch parameter is equal to zero in input register 205, it is interpreted as an unvoiced condition by condition decoders and latches 208. Gate 408 responds by supplying randomized data from unvoiced generator 407 as the excitation input. When the coded pitch parameter is of some other value, however, it is decoded by parameter ROM 202, loaded into parameter output register 201 and eventually inserted into pitch register 305, either directly or by the interpolation scheme previously described. Based on the period indicated by the number in pitch register 305, voiced excitation is derived from chirp ROM 409. As discussed in U.S. Pat. No. 4,209,844 the voiced excitation signal may be an impulse function or some other repeating function such as a repeating chirp function. In this embodiment, a chirp has been selected as this tends to reduce the "fuzziness" from the speech generated (because it apparently more closely models the action of the vocal cords than does a impulse function) which chirp is repetitively generated by chirp ROM 409. Chirp ROM 409 is addressed by counter latch 410, whose address is incremented in an add one circuit 411. The address in counter latch 410 continues to increment in add on circuit 411, recirculating via reset logic 412 until magnitude comparator 413, which compares the magnitude of the address being outputted from add one circuit 411 and the contents of the pitch register 305, indicates that the value in counter latch 410 then compares with or exceeds the value in pitch register 305, at which time reset logic 412 zeroes the address in counter latch 410. Beginning at address zero and extending through approximately fifty addresses is the chirp function in chirp ROM 409. Counter latch 410 and chirp ROM 409 are set up so that addresses larger than fifty do not cause any portion of the chirp function to be outputted from chirp ROM 409 to UV gate 408. In this manner the chirp function is repetitively generated on a pitch related period during voiced speech.
SYSTEM TIMING
FIG. 5 depicts the timing relationships between the occurrences of the various timing signals generated on synthesizer chip 10. Also depicted are the timing relationships with respect to the time new frames of data are inputted to synthesizer chip 10, the timing relationship with respect to the interpolations performed on the inputted parameters, the timing relations with respect to the foregoing with the time periods of the lattice filter and the relationship of all the foregoing to the basic clock signals.
The synthesizer is preferably implemented using precharged, conditional discharge type logics and therefore FIG. 5 shows clocks .phi.1-.phi.4 which may be appropriately used with such precharge-conditional discharge logic. There are two main clock phases (.phi.1 and .phi.2) and two precharge clock phases (.phi.3 and .phi.4). Phase .phi.3 goes low during the first half of phase .phi.1 and serves as a precharge therefor. Phase .phi.4 goes low during the first half of phase .phi.2 and serves as a precharge therefore. A set of clocks .phi.1-.phi.4 is required to clock one bit of data and thus corresponds to one time period.
The time periods are labeled T1-T20 and each preferably has a time period on the order of five microseconds. Selecting a time period on the order of five microseconds permits, as will be seen, data to be outputted from the digital filter at a ten kilohertz rate (i.e., at a 100 microsecond period) which provides for a frequency response of five kilohertz in the D to A output section 25 (FIG. 4b). It will be appreciated by those skilled in the art, however, that depending on the frequency response which is desired and depending upon the number of Kn speech coefficients used, and also depending upon the type of logics used, that the periods or frequencies of the clocks and clock phases shown in FIG. 5 may be substantially altered, if desired.
As is explained in U.S. Pat. No. 4,209,844, one cycle time of the lattice filter in filter excitation generator 24, preferably comprises twenty time periods, T1-T20. For reasons not important here, the numbering of these time periods differs between this application and U.S. Pat. No. 4,209,844. To facilitate an understanding of the differences in the numbering of the time periods, both numbering schemes are shown at the time period time line 500 in FIG. 5. At time line 500, the time periods, T1-T20 which are not enclosed in parenthesis identify the time periods according to the convention used in this application. On the other hand, the time periods enclosed in parenthesis identify the time periods according to the convention used in U.S. Pat. No. 4,209,844. Thus, time period T17 is equivalent to time period (T9).
At numeral 501 is depicted the parameter count (PC) timing signals. In this embodiment there are thirteen PC signals, PC=0 through PC=12. The first twelve of these, PC=0 through PC=11 correspond to times when the energy, pitch, and K1-K10 parameters, respectively, are available in parameter output register 201. Each of the first twelve PC's comprise two cycles, which are labeled A and B. Each such cycle starts at time period T17 and continues to the following T17. During each PC the target value from the parameter output register 201 is interpolated with the existing value in K-stack 302 in parameter interpolator 23. During the A cycle, the parameter being interpolated is withdrawn from the K-stack 302, E10 loop 304 or pitch register 305, as appropriate, during an appropriate time period. During the B cycle the newly interpolated value is reinserted in the K-stack (or E10 loop or pitch register). The thirteenth PC, PC=12, is provided for timing purposes so that all twelve parameters are interpolated once each during a 2.5 milliseconds interpolation period.
As was discussed with respect to the parameter interpolator 23 of FIG. 4b and Table IV, eight interpolations are performed for each inputting of a new frame of data from ROMs 12A-12B into synthesizer 10. This is seen at numeral 502 of FIG. 5 where timing signals DIV 1, DIV 2, DIV 4 and DIV 8 are shown. These timing signals occur during specific interpolation counts (IC) as shown. There are eight such interpolation counts, IC0-IC7. New data is inputted from the ROMs 12A-b into the synthesizer during IC0. These new target values of the parameters are then used during the next eight interpolation counts, IC1 through IC0; the existing parameters in the pitch register 305 K-stack 302 and E10 loop 304 are interpolated once during each interpolation count. At the last interpolation count, IC0, the present value of the parameters in the pitch register 305, K-stack 302 and E10 loop 304 finally attain the target values previously inputted toward the last IC0 and thus new target values may then again be inputted as a new frame of data. Inasmuch as each interpolation count has a period of 2.5 milliseconds, the period at which new data frames are inputted to the synthesizer chip is 20 microseconds or equivalent to a frequency of 50 hertz. The DIV 8 signal corresponds to those interpolation counts in which one-eighth of the difference produced by subtractor 308 is added to the present values in adder 310 whereas during DIV 4 one-fourth of the difference is added in, and so on. Thus, during DIV 2, 1/2 of the difference from subtractor 308 is added to the present value of the parameter in adder 310 and lastly during DIV 1 the total difference is added in adder 310. As has been previously mentioned, the effect of this interpolation scheme can be seen in Table IV.
PARAMETER DATA COMPRESSION
It has been previously mentioned that new parameters are inputted to the speech synthesizer at a 50 hertz rate. It will be subsequently seen that in parameter interpolator 23 and excitation generator 24 (FIG. 4b) the pitch data, energy data and Kl-Kn parameters are stored and utilized as ten bit digital binary numbers. If each of these twelve parameters were updated with a ten bit binary number at a fifty hertz rate from an external source, such as ROMs 12A and 12B, this would require a 12.times.10.times.50 or 6,000 hertz bit rate. Using the data compression techniques which will be explained, this bit rate required for synthesizer 10 is reduced to on the order of 1,000 to 1,200 bits per second. And more importantly, it has been found that the speech compression schemes herein disclosed do not appreciably degrade the quality of speech generated thereby in comparison to using the data uncompressed.
The data compression scheme used is pictorially shown in FIG. 6. Referring now to FIG. 6, it can be seen that there is pictorially shown four different lengths of frames of data. One, labeled voiced frame, has a length of 49 bits while another entitled unvoiced frame, has a length of 28 bits while still another called "repeat frame" has a length of ten bits and still another which may be alternatively called zero energy frame or energy equals fifteen frame has the length of but four bits. The "voiced frame" supplies four bits of data for a coded energy parameter as well as coded four bits for each of five speech parameters K3 through K7. Five bits of data are reserved for each of three coded parameters, pitch, K1 and K2. Additionally, three bits of data are provided for each of three coded speech parameters K8-K10 and finally another bit is reserved for a repeat bit.
In lieu of inputting ten bits of binary data for each of the parameters, a coded parameter is inputted which is converted to a ten bit parameter by addressing parameter ROM 202 with the coded parameter. Thus, coefficient K1, for example, may have any one of thirty-two different values, according to the five bit code for K1, each one of the thirty-two values being a ten bit numerical coefficient stored in parameter ROM 202. Thus, the actual values of coefficients K1 and K2 may have one of thirty-two different values while the actual values of coefficients K3 through K7 may be one of sixteen different values and the values of coefficients K8 through K10 may be one of eight different values. The coded pitch parameter is five bits long and therefore may have up to thirty-two different values. However, only thirty-one of these reflect actual pitch values, a pitch code of 00000 being used to signify an unvoiced frame of data. The coded energy parameter is four bits long and therefore would normally have sixteen available ten bit values; however, a coded energy parameter equal to 0000 indicates a silent frame such as occur as pauses in and between words, sentences and the like. A coded energy parameter equal to 1111 (energy equals fifteen), on the other hand, is used to signify the end of a segment of spoken speech, thereby indicating that the synthesizer is to stop speaking. Thus, of the sixteen codes available for the coded energy parameter, fourteen are used to signify different ten bit speech energy levels.
Coded coefficients K1 and K2 have more bits than coded coefficients K3-K7 which in turn have more bits than coded coefficients K8 through K10 because coefficient K1 has a greater effect on speech than K2 which has a greater effect on speech than K3 and so forth through the lower order coefficients. Thus given the greater significance of coefficients K1 and K2 than coefficients K8 through K10, for example, more bits are used in coded format to define coefficients K1 and K2 than K3-K7 or K8-K10.
Also it has been found that voiced speech data needs more coefficients to correctly model speech than does unvoiced speech and therefore when unvoiced frames are encountered, coefficients K5 through K10 are not updated, but rather are merely zeroed. The synthesizer realizes when an unvoiced frame is being outputted because the encoded pitch parameter is equal to 00000.
It has also been found that during speech there often occur instances wherein the parameters do not significantly change during a twenty millisecond period; particularly, the K1-K10 coefficients will often remain nearly unchanged. Thus, a repeat frame is used wherein new energy and new pitch are inputted to the synthesizer, however, the K1-K10 coefficients previously inputted remain unchanged. The synthesizer recognizes the ten bit repeat frame because the repeat bit between energy and pitch then comes up whereas it is normally off. As previously mentioned, there occur pauses between speech or at the end of speech which are preferably indicated to the synthesizer; such pauses are indicated by a coded energy frame equal to zero, at which time the synthesizer recognizes that only four bits are to be sampled for that frame. Similarly, only four bits are sampled when an "energy equals fifteen" frame is encountered.
Using coded values for the speech in lieu of actual values, alone would reduce the data rate to 48.times.50 or 2400 bits per second. By additionally using variable frame lengths, as shown in FIG. 6, the data rate my be further reduced to on the order of one thousand to twelve hundred bits per second, depending on the speaker and on the material spoken.
The effect of this data compression scheme can be seen from Table V where the coding for the word "HELP" is shown. Each line represents a new frame of data. As can be seen, the first part of the word "HELP", "HEL", is mainly voiced while the "P" is unvoiced. Also note the pause between "HEL" and "P" and the advantages of using the repeat bit. Table VI sets forth the encoded and decoded speech parameter. The 3, 4 or 5 bit code appears as a hexadecimal number in the left-hand column, while the various decoded parameter values are shown as ten bit, two's complement numbers expressed as hexadecimal numbers in tabular form under the various parameters. The decoded speech parameter is stored in ROM 203. The repeat bit is shown in Table V between the pitch and K parameters for sake of clarity; preferably, according to the embodiment of FIG. 6, the repeat bit occurs just before the most significant bit (MSB) of the pitch parameter.
SYNTHESIZER LOGIC DIAGRAMS
The various portions of the speech synthesizer of FIGS. 4a and 4b will now be described with reference to FIGS. 7a through 14b which, depict, in detail, the logic circuits implemented on a semiconductor chip, for example, to form the synthesizer 10. The following discussion, with reference to the aforementioned drawings, refers to logic signals available at many points in the circuit. It is to be remembered that in P channel MOS devices a logical zero corresponds to a negative voltage, that is, Vdd, while a logical one refers to a zero voltage, that is, Vss. It should be further remembered that P-channel MOS transistors depicted in the aforementioned figures are conductive when a logical zero, that is, a negative voltage, is applied at their respective gates. When a logic signal is referred to which is unbarred, that is, has no bar across the top of it, the logic signal is to be interpreted as "TRUE" logic; that is, a binary one indicates the presence of the signal (Vss) whereas a binary zero indicates the lack of the signal (Vdd). Logic signal names including a bar across the top thereof are "FALSE" logic; that is, a binary zero (Vdd voltage) indicates the presence of the signal whereas a binary one (Vss voltage) indicates that the signal is not present. It should also be understood that a numeral three in clocked gates indicates that phase .phi.3 is used as a precharge whereas a four in a clocked gate indicates that phase .phi.4 is used as a precharge clock. An "S" in the gate indicates that the gate is statically operated.
Timing Logic Diagram
Referring now to FIGS. 7a-7d, they form a composite, detailed logic diagram of the timing logic for synthesizer 10. Counter 510 is a pseudorandom shift counter including a shift register 510a and feed back logic 510b. The counter 510 counts into pseudorandom fashion and the TRUE and FALSE outputs from shift register 510a are supplied to the input section 511 of a timing PLA. The various T time periods decoded by the timing PLA are indicated adjacent to the output lines thereof. Section 511c of the timing PLA is applied to an output timing PLA 512 generating various combinations and sequences of time period signals, such as T odd, T10-T18, and so forth. Sections 511a and 511b of timing PLA 511 will be described subsequently.
The parameter count in which the synthesizer is operating is maintained by a parameter counter 513. Parameter counter 513 includes an add one circuit and circuits which are responsive to SLOW and SLOW D. In SLOW, the parameter counter repeats the A cycle of the parameter count twice (for a total of three A cycles) before entering the B cycle. That is, the period of the parameter count doubles so that the parameters applied to the lattice filter are updated and interpolated at half the normal rate. To assure that the inputted parameters are interpolated only once during each parameter count during SLOW speaking operations each parameter count comprises three A cycles followed by one B cycle. It should be recalled that during the A cycle the interpolation is begun and during the B cycle the interpolated results are reinserted back into either K-stack 302, E10 loop 304 or pitch register 305, as appropriate. Thus, merely repeating the A cycle has no affect other than to recalculate the same value of a speech parameter but since it is only reinserted once back into either K-stack 302, E10 loop 304 or pitch register 305 only the results of the interpolation immediately before the B cycle are retained.
Inasmuch as parameter counter 513 includes an add one circuit, the results outputted therefrom, PC1-PC4, represent in binary form, the particular parameter count in which the synthesizer is operating. Output PC0 indicates in which cycle, A or B, the parameter count is. The parameter counter outputs PC1-PC4 are decoded by timing PLA 514. The particular decimal value of the parameter count is decoded by timing PLA 514 which is shown in adjacent to the timing PLA 514 with nomenclature such as PC=0, PC=1, PC=7 and so forth. The relationship between the particular parameters and the value of PC is set forth in FIG. 6. Output portions 511a and 511b of timing PLA 511 are also interconnected with outputs from timing PLA 514 whereby the Transfer K (TK) signal goes high during T9 of PC=2 or T8 of PC=3 or T7 of PC=4 and so forth through T1 of PC=10. Similarly, a LOAD Parameter (LDP) timing signal goes high during T5 of PC=0 or T1 of PC=1 or T3 of PC=2 and so forth through T7 of PC=11. As will be seen, signal TK is used in controlling the transfer of data from parameter output register 201 to subtractor 308, which transfer occurs at different T times according to the particular parameter count the parameter counter 513 is in to assure that the appropriate parameter is being outputted from KE10 transfer register 303. Signal LDP is, as will be seen, used in combination with the parameter input register to control the number of bits which are inputted therein according to the number of bits associated with the parameter then being loaded according to the number of bits in each coded parameter as defined in FIG. 6.
Interpolation counter 515 includes a shift register and an add one circuit for binary counting the particular interpolation cycle in which the synthesizer 10 is operating. The relationship between the particular interpolation count in which the synthesizer is operating and the DIV1, DIV2, DIV4 and DIV8 timing signals derived therefrom is explained in detail with reference to FIG. 5 and therefore additional discussion here would be superfluous. It will be noted, however, that interpolation counter 515 includes a three bit latch 516 which is loaded at TI. The output of three bit latch 516 is decoded by gates 517 for producing the aforementioned DIV1 through DIV8 timing signals. Interpolation counter 515 is responsive to a signal RESETF from parameter counter 513 for permitting interpolation counter 515 to increment only after PC=12 has occurred.
ROM/Controller Interface Logic Diagram
Turning now to FIGS. 8a-8f, which form a composite diagram, there is shown a detailed logic diagram of ROM/Controller interface logic 21. Parameter input register 205 is coupled, at its input to address pin ADD1. Register 205 is a six bit shift register, most of the stages of which are two bits long. The stages are two bits long in this embodiment inasmuch as ROMs 12a and b output, as will be seen, data at half the rate at which data is normally clocked in synthesizer 10. At the input of parameter input register 205 is a parameter input control gate 220 which is responsive to the state of a latch 221. Latch 221 is set in response to LDP, PC0 and DIV1 all being a logical one. It is reset at T14 and in response to parameter load enable from gate 238 being a logical zero. Thus, latch 221 permits gate 220 to load data only during the A portion (as controlled by PC0) of the appropriate parameter count and at an appropriate T time (as controlled by LDP) of IC0 (as controlled by DIV1) provided parameter load enable is at a logical one. Latch 221 is reset by T14 after the data has been inputted into parameter register 205.
The coded data in parameter input register 205 is applied on lines IN0-IN4 to coded parameter RAM 203, which is addressed by PC1-PC4 to indicate which coded parameter is then being stored. The contents of register 205 is tested by all one's gate 207, all zeroes gate 206 and repeat latch 208a. As can be seen, gate 206 tests for all zeroes in the four least significant bits of register 205 whereas gate 207 tests for all ones in those bits. Gate 207 is also responsive to PC0, DIV1, T16 and PC=0 so that the zero condition is only tested during the time that the coded energy parameter is being loaded into parameter ROM 205. The repeat bit occurs in this embodiment immediately in front of the coded pitch parameter; therefore, it is tested during the A cycle of PC=1. Pitch latch 208b is set in response to all zeroes in the coded pitch parameter and is therefore responsive to not only gate 206 but also the most significant bit of the pitch data on line 222 as well as PC=1. Pitch latch 208b is set whenever the loaded coded pitch parameter is a 00000 indicating that the speech is to be unvoiced.
Energy=0 latch 208c is responsive to the output of gate 206 and PC=0 for testing whether all zeroes have been inputted as the coded energy parameter and is set in response thereto. Old pitch latch 208d stores the output of the pitch=0 latch 208b from the prior frame of speech data while old energy latch 208e stores the output of energy=0 latch 208c from the prior frame of speech data. The contents of old pitch latch 208d and pitch=0 latch 208b are compared in comparison gates 223 for the purpose of generating an INHIBIT signal. As will be seen, the INHIBIT signal inhibits interpolations and this is desirable during changes from voiced to unvoiced or unvoiced to voiced speech so that the new speech parameters are automatically inserted into K-stack 302, E10 loop 304 and pitch register 305 as opposed to being more slowly interpolated into those memory elements. Also, the contents of old energy latch 208e and energy=0 latch 208c is tested by NAND gate 224 for inhibiting interpolation for a transition from a non-speaking frame to a speaking frame of data. The outputs of NAND gate 224 and gates 223 are coupled to a NAND gate 235 whose output is inverted to INHIBIT by an inverter 236. Latches 208a-208c are reset by gate 225 and latches 208d and 208e are reset by gate 226. When the excitation signal is unvoiced, the K5-K10 coefficients are set to zero, as aforementioned. This is accomplished, in part, by the action of gate 237 which generates a ZPAR signal when pitch is equal to zero and when the parameter counter is greater than five, as indicated by PC 5 from PLA 514.
Also shown in FIGS. 8a-8f is a command latch 210 which comprises three latches 210a,b, and c which latch in the data at CTL2,4 and 8 in response to a processor data clock (PDC) signal in conjunction with a chip select (CS) signal. The contents of command latch 210 is decoded by command decoder 211 unless disabled by latches 218a and 218b. As previously mentioned, these latches are responsive to decoded LA, output and TTALK commands for disabling decoder 211 from decoding what ever data happens to be on the CTL2-CTL8 pins when subsequent PDC signals are received in conjunction with the LA, output and TTALK commands. A decoded TTALK command sets TTALK latch 219. The output of TTALK latch 219, which is reset by a Processor Data Clock Leading Edge (PDCLE) signal or by an output from latch 218b, controls along with the output of latch 218a NOR gates 227a and b. The output of NOR gate 227a is a logical one if TTALK latch 219 is set, thereby coupling pins CTL1 to the talk latch via tristate buffer 228 and inverters 229. Tristate latch 228 is shown in detail in FIG. 8d. NOR gate 227b, on the other hand, outputs a logical one if an output code has been detected, setting latch 228a and thereby connecting pins CTL1 to the most significant bit of data input register 212.
Data is shifted into data input register 212 from address pin 8 in response to a decoded read command by logics 230. RE, RB and LA instructions are outputted to ROM via instruction pins I.sub.0 -I.sub.1 from ROM control logic 217 via buffers 214c. The contents of data input register 212 is outputted to CTL1-CTL4 pins via buffers 213 and to the aforementioned CTL1 pin via buffer 228 when NOR gate 227b inputs a logical one. CTL1-CTL4 pins are connected to address pins ADD1-ADD4 via buffers 214a and CTL8 pin is connected to ADD8 pin 8 via a control buffer 214b which is disabled when addresses are being loaded on the ADD1-ADD8 pins by the signal on line 231.
The Talk latch 216 shown in FIG. 8f preferably comprises, three latches 216a, 216b and 216c. Latch 216a is set in response to a decoded SPK command and generates, in response thereto, a speak enable (SPEN) signal. As will be seen, SPEN is also generated in response to a decoded SPKSLOW command by latch 215a. Latch 216b is set in response to speak enable during IC7 as controlled by gate 225. Latches 216a and 216b are reset in response to (1) a decoded reset command, (2) an energy equals fifteen code or (3) on a power-up clear by gate 232. Talk delayed latch 216c is set with the contents of latch 216b at the following IC7 and retains that data through eight interpolation counts. As was previously mentioned, the talk delayed latch permits the speech synthesizer to continue producing speech data for eight interpolation cycles after a coded energy=0 condition has been detected setting latch 208c. Likewise, slow talk latch 215 is implemented with latches 215a, 215b and 215c. Latch 215a enables the speak enable signal while latches 215b and 215c enable the production of the SLOWD signal in much the same manner as latches 216b and 216c enable the production of the TALKD signal.
Considering now, briefly, the timing interactions for inputting data into parameter input register 205, it will be recalled that this is controlled chiefly by a control gate 220 in response to the state of a parameter input latch 221. Of course, the state of the latch is controlled by the LDP signal applied to gate 233. The PC0 and DIV1 signals applied to gate 233 to assure that the parameters are loaded during the A cycle of a particular parameter count during IC0. The particular parameter and the parameter T-Time within the parameter count is controlled by LDP according to the portion 511a of timing PLA 511 (FIGS. 7a-7d). The first parameter inputted (Energy) is four bits long and therefore LDP is initiated during time period T5 (as can be seen in FIGS. 7a and 7b). During parameter count 1, the repeat bit and pitch bits are inputted, this being six bits which are inputted according to LDP which comes up at time period T1. Of course, there four times periods difference between T1 and T5 but only two bits difference in the length of the inputted information. This occurs because it takes two time periods to input each bit into parameter input register 205 (which has two stages per each inputted bit) due to the fact that ROMs 12A-12B are preferably clocked at half the rate at that which synthesizer 10 is clocked. By clocking the ROM chips at half the rate, that the synthesizer 10 chip is clocked simplifies the addressing of the read-only-memories in the aforesaid ROM chips and yet, as can be seen, data is supplied to the synthesizer 10 in plenty of time for performing numerical operations thereon. Thus, in section 511a of timing PLA 511, LDP comes up at T1 when the corresponding parameter count indicates that a six bit parameter is to be inputted, comes up at T3 when the corresponding parameter count indicates that a five bit parameter is to be inputted, comes up at T5 when the corresponding parameter count indicates that a four bit parameter is to be inputted and comes up at time period T7 when the corresponding parameter count (EG parameter counts 9, 10, and 11) which correspond to a three bit coded parameter. ROMs 12A-12B are signaled that the addressed parameter ROM is to output information when signaled via I.sub.0 instruction pin, ROM control logic 217 and line 234 which provides information to ROM control logic 217 from latch 221.
Parameter Interpolator Logic Diagram
Referring now to FIGS. 9a and 9b, which form a composite diagram the parameter interpolator logic 23 is shown in detail. K-stack 302 comprises ten registers each of which store ten bits of information. Each small square represents one bit of storage, according to the convention depicted at numeral 330. The contents of each shift register is arranged to recirculate via recirculation gates 314 under control of a recirculation control gate 315. K-stack 302 stores speech coefficients K1-K9 and temporarily stores coefficient K10 or the energy parameter generally in accordance with the speech synthesis apparatus of FIG. 7 of U.S. Pat. No. 4,209,844. The data outputted from K-stack 302 to recoding logic 301 at various time periods is shown in Table VII. In Table III of U.S. Pat. No. 4,209,844 is shown the data outputted from the K-stack of FIG. 7 thereof. Table VII of this patent differs from Table III of the aforementioned patent because of (1) recoding logic 301 receives the same coefficient on lines 32-1 through 32-4, on lines 32-5 and 32-6, on lines 32-7 and 32-8 and on lines 32-9 and 32-10 because, as will be seen, recoding logic 301 responds to two bits of information for each bit which was responded to by the array multiplier of the aforementioned U.S. Patent; (2) because of the difference in time period nomenclature as was previously explained with reference to FIG. 5; and (3) because of the time delay associated with the recoding logic 301.
Recoding logic 301 couples K-stack 302 to array multiplier 401 (FIGS. 10a-10c). Recoding logic 301 includes four identical recoding stages 312a-312d, only one of which, 312a, is shown in detail. The first stage of the recoding logic, 313, differs from stages 312a-312d basically because there is, of course, no carry, such as occurs on input A in stages 312a-312d, from a lower order stage. Recoding logic outputs +2, -2, +1 and -1 to each stage of a five stage array multiplier 401, except for stage zero which receives only -2, +1 and -1 outputs. Effectively recoding logic 301 permits array multiplier to process, in each stage thereof, two bits in lieu of one bit of information, using Booth's algorithm. Booth's algorithm is explained in "Theory and Application of Digital Signal Processing", published by Prentice-Hall 1975, at pp. 517-18.
The K10 coefficient and energy are stored in E10 loop 304. E10 loop preferably comprises a twenty stage serial shift register; ten stages 304a of E10 loop 304 are preferably coupled in series and another ten stages 304b are also coupled in series but also have parallel outputs and inputs to K-stack 302. The appropriate parameter, either energy or the K10 coefficient, is transferred from E10 loop 304 to K-stack 302 via gates 315 which are responsive to a NOR gate 316 for transferring the energy parameter from E10 loop 304 to K-stack 302 at time period T10 and transferring coefficient K10 from E10 loop 304 to K-stack 302 at time period T20. NOR gate 316 also controls recirculation control gate 315 for inhibiting recirculation in K-stack 302 when data is being transferred.
KE10 transfer register 303 facilitates the transferring of energy or the K1-K10 speech coefficients which are stored in E10 loop 304 or K-stack 302 to subtractor 308 and delay circuit 309 via selector 307. Register 303 has nine stages provided by paired inverters and a tenth stage being effectively provided by selector 307 and gate 317 for facilitating the transfer of ten bits of information either from E10 loop 304 or K-stack 302. Data is transferred from K-stack 302 to register 303 via transfer gates 318 which are controlled by a Transfer K (TK) signal generated by decoder portion 511b of timing PLA 511 (FIGS. 7a-7d). Since the particular parameter to be interpolated and thus shifted into register 303 depends upon the particular parameter count in which the synthesizer is operating and since the particular parameter available to be outputted from K-stack 302 is a function of particular time period the synthesizer is operating in, the TK signal comes up at T9 for the pitch parameter, T8 for the K1 parameter, T7 for the K2 parameter and so forth, as is shown in FIGS. 7a-7d. The energy parameter or the K10 coefficient is clocked out of E10 loop 304 into register 303 via gates 319 in response to a TE10 signal generated by a timing PLA 511. After each interpolation, that is during the B cycle, data is transferred from register 303 into (1) K-stack 302 via gates 318 under control of signal TK, at which time recirculation gates 314 are turned off by gate 315, or (2) E10 loop 304 via gates 319.
A ten bit pitch parameter is stored in a pitch register 305 which includes a nine stage shift register as well as recirculation elements 305a which provide another bit of storage. The pitch parameter normally recirculates in register 305 via gate 305a except when a newly interpolated pitch parameter is being provided on line 320, as controlled by pitch interpolation control logics 306. The output of pitch 305 (PT0) or the output from register 303 is applied by selector 307 to gate 317. Selector 307 is also controlled by logics 306 for normally coupling the output of register 303 to gate 317 except when the pitch is to be interpolated. Logics 306 are responsive for outputting pitch to subtractor 308 and delay 309 during the A cycle of PC=1 and for returning the interpolated pitch value on line 320 on the B cycle of PC=1 to register 305. Gate 317 is responsive to a latch 321 for only providing pitch, energy or coefficient information to subtractor 308 and delay circuit 309 during the interpolation. Since the data is serially clocked, the information may be started to be clocked during an A portion and PC0 may switch to a logical one sometime during the transferring of the information from register 303 or 305 to subtractor 308 or delay circuit 309, and therefore, gate 317 is controlled by an A cycle latch 321, which latch is set with PC0 at the time a transfer coefficient (TK) transfer E10 (TE10) or transfer pitch (TP) signal is generated by timing PLA 511.
The output of gate 317 is applied to subtractor 308 and delay circuit 309. The delay in delay circuit 309 depends on the state of DIV1-DIV8 signals generated by interpolation counter 515 (FIG. 7a). Since the data exits gate 317 with the least significant bit first, by delaying the data in delay circuit 309 a selective amount, and applying the output to adder 310 along with the output of subtractor 308, the more delay there is in circuit 309, the smaller the effective magnitude of the difference from subtractor 308 which is subsequently added back in by adder 310. Delay circuit 311 couples adder 310 back into registers 303 and 305. Both delay circuits 309 and 311 can insert up to three bits of delay and when delay circuit 309 is at its maximum, delay circuit 311 is at its minimum delay and vice-versa. A NAND gate 322 couples the output of subtractor 308 to the input of adder 310. Gate 322 is responsive to the output of an OR gate 323 which is in turn responsive to INHIBIT from inverter 236 (FIGS. 8a and 9b). Gates 322 and 323 act to zero the output from subtractor 308 when the INHIBIT signal comes up unless the interpolation counter is at IC0 in which case the present values in K-stack 302, E10 loop 304 and pitch register 305 are fully interpolated to their new target values in a one step interpolation. When an unvoiced frame (FIG. 6) is supplied to the speech synthesis chip, coefficients K5-K10 are set to zero by the action of gate 324 which couples delay circuit 311 to shift register 325 whose output is then coupled to gates 305a and 303'. Gate 324 is responsive to the zero parameter (ZPAR) signal generated by gate 237 (FIGS. 8a and 9b).
Gate 326 disables shifting in the 304b portion of E10 loop 304 when a newly interpolated value of energy or K10 is being inputted into portion 304b from register 303. Gate 327 controls the transfer gates coupling the stages of register 303, which stages are inhibited from serially shifting data therebetween when TK or TE10 goes high during the A cycle, that is, when register 303 is to be receiving data from either K-stack 302 or E10 loop 304 as controlled by transfer gates 318 or 319, respectively. The output of gates 327 is also connected to various stages of shift register 325 and to a gate coupling 303' with register 303. Whereby up top the three bits which may trail the ten most significant bits after an interpolation operation may be zeroed.
Array Multiplier Logic Diagram
FIGS. 10a-10c form a composite logic diagram of array multiplier 401. Array multipliers are sometimes referred to as Pipeline Multipliers. For example, see "Pipeline Multiplier" by Granville E. Ott, published by the University of Missouri.
Array multiplier 401 has five stages, stage 0 through stage 4, and a delay stage. The delay stage is used in array multiplier 401 to give it the same equivalent delay as the array multiplier shown in U.S. Pat. No. 4,209,844. The input to array multiplier 401 is provided by signals MR.sub.0 -MR.sub.13, from multiplier multiplexer 415. MR.sub.13 is the most significant bit while MR.sub.0 is the least significant bit. Another input to array multiplier are the aforementioned +2, -2, +1 and -1 outputs from recoding logic 301 (FIG. 9d). The output from array multiplier 401, P.sub.13 -P.sub.0, is applied to summer multiplexer 402. The least significant bit thereof, P0, is in this embodiment always made a logical one because doing so establishes the mean of the truncation error as zero instead of -1/2 LSB which value would result from a simple truncation of a two's complement number.
Array multiplier 401 is shown by a plurality of box elements labeled A-1, A-2, B-1, B-2, B-3 or B-C. The specific logic elements making up these box elements are shown in FIG. 10c in lieu of repetitively showing these elements and making up a logic diagram of array multiplier 401, for simplicity sake. The A-1 and A-2 block elements make up stage zero of the array multiplier and thus are each responsive to the -2, +1 and -1 signals outputted from decoder 313 and are further responsive to MR2-MR13. When multiplies occur in array multiplier 401, the most significant bit is always maintained in the left most column elements while the partial sums are continuously shifted toward the right. Inasmuch as each stage of array multiplier 401 operates on two binary bits, the partial sums, labeled .SIGMA.n, are shifted to the right two places. Thus no A type blocks are provided for the MR0 and MR1 data inputs to the first stage. Also, since each block in array multiplier 401 is responsive to two bits of information from K-stack 302 received via recording logic 301, each block is also responsive to two bits from multiplier multiplexer 415, which bits are inverted by inverters 430, which bits are also supplied in true logic to the B type blocks.
Filter and Excitation Generator Logic Diagram
FIGS. 11a-11d form a composite, detailed logic diagram of lattice filter and excitation generator 24 (other than array multiplier 401) and output section 25. In filter and excitation generator 24 is a summer 404 which is connected to receive at one input thereof either the true or inverted output of array multiplier 401 (see FIGS. 10a-10c) on lines P0-P13 via summer multiplexer 402. The other input of adder 404 is connected via summer multiplexer 402 to receive either the output of adder 404 (atT10-T18), the output of delay stack 406 on lines 440-453 at T20-T7 and T9), the output of Y-latch 403 (at T8) or a logical zero from .phi.3 precharge gate 420 (at T19 when no conditional discharge is applied to this input). The reasons these signals are applied at these times can be seen from FIG. 8 of the aforementioned U.S. Pat. No. 4,209,844; it is to be remembered of course, that the time period designations differ as discussed with reference to FIG. 5 hereof.
The output of adder 404 is applied to delay stack 406, multiplier, multiplexer 415, one period delay gates 414 and summer multiplexer 402. Multiplier multiplexer 415 includes one period delay gates 414 which are generally equivalent to one period delay 34' of FIG. 7 in U.S. Pat. No. 4,209,844. Y-latch 403 is connected to receive the output of delay stack 406. Multiplier multiplexer 415 selectively applies the output from Y-latch 403, one period delay gates 414, or the excitation signal on bus 415' to the input MR0-MR13 of array multiplier 401. The inputs D0-D13 to delay stack 406 are derived from the outputs of adder 404. The logics for summer multiplexer 402, adder 404, Y-latch 403, multiplier multiplexer 415 and one period delay circuit 414 are only shown in detail for the least significant bit as enclosed by dotted line reference A. The thirteen most significant bits in the lattice filter also are provided by logics such as those enclosed by the reference line A, which logics are denoted by long rectangular phantom line boxes labeled "A". The logics for each parallel bit being processed in the lattice filter are not shown in detail for sake of clarity. The portions of the lattice filter handling bits more significant than the least significant bit differ from the logic shown for elements 402, 403, 404, 415, and 414 only with respect to the interconnections made with truncation logics 425 and bus 415' which connects to UV gate 408 and chirp ROM 409. In this respect, the output from UV gate 408 and chirp ROM 409 is only applied to inputs I13-I6 and therefore the input labeled I.sub.x within the reference A phantom line is not needed for the six least significant bits in the lattice filter. Similarly, the output from the Y-latch 403 is only applied for the ten most significant bits, YL.sub.13 through YL.sub.4, and therefore the connection labeled YLx within the reference line A is not required for the four least significant bits in the lattice filter.
Delay stack 406 comprises 14 nine bit long shift registers, each stage of which comprise inverters clocked on .phi.4 and .phi.3 clocks. As is discussed is U.S. Pat. No. 4,209,844, the delay stack 406 which generally corresponds to shift register 35' of FIG. 7 of the aforementioned patent, is only shifted on certain time periods. This is accomplished by logics 416 whereby .phi.1B-.phi.4B clocks are generated from T10-T18 timing signal from PLA 512 (FIGS. 7a-7d). The clock buffers 417 in circuit 416 are also shown in detail in FIG. 11c.
Delay stack 406 is nine bits long whereas shift register 35' in FIG. 7 of U.S. Pat. No. 4,209,844 was eight bits long; this difference occurs because the input to delay stack 406 is shown as being connected from the output of adder 404 as opposed to the output of one period delay circuit 414. Of course, the input to delay stack 406 could be connected from the outputs of one period delay circuit 414 and the timing associated therewith modified to correspond with that shown in U.S. Pat. No. 4,209,844.
The data handled in delay stack 406, array multiplier 401, adder 404, summer multiplexer 402, Y-latch 403, and multiplier multiplexer 415 is preferably handled in two's complement notation.
Unvoiced generator 407 is a random noise generator comprising a shift register 418 with a feedback term supplied by feedback logics 419 for generating pseudorandom terms in shift register 418. An output is taken therefrom and is applied to UV gate 408 which is also responsive to OLDP from latch 208d (FIG. 8c). Old pitch latch 208d controls gate 408 because pitch=0 latch 208b changes state immediately when the new speech parameters are inputted to register 205. However, since this occurs during interpolation count IC0 and since, during an unvoiced condition the new values are not interpolated into K-stack 302, E10 loop 304 and pitch register 305 until the following ICO, the speech excitation value cannot change from a periodic excitation from chirp ROM 409 to a random excitation from unvoiced generator 407 until eight interpolation cycles have occurred. Gate 420 nors the output of gate 408 into the most significant bit of the excitation signal, I.sub.13, thereby effectively causing the sign bit to randomly change during unvoiced speech. Gate 421 effectively forces the most significant bit of the excitation signal, I.sub.12, to a logical one during unvoiced speech conditions. Thus the combined effect of gates 408, 420 and 421 is to cause a randomly changing sign to be associated with a steady decimal equivalent value of 0.5 to be applied to the lattice filter and Filtering Excitation Generator 24.
During voiced speech, chirp ROM 409 provides an eight bit output on lines I.sub.6 -I.sub.13 to the lattice filter. This output comprises forty-one successively changing values which, when graphed, represent a chirp function. The contents of ROM 409 are listed in Table VIII; ROM 409 is set up to invert its outputs and thus the data is stored therein in complemented format. The chirp function value and the complemented value stored in the chirp ROM are expressed in two's complement hexadecimal notation. ROM 409 is addressed by an eight bit register 410 whose contents are normally updated during each cycle through the lattice filter by add one circuit 411. The output of register 410 is compared with the contents of pitch register 305 in a magnitude comparator 403 for zeroing the contents of 410 when the contents of register 410 become equal to or greater than the contents of register 305. ROM 409, which is shown in greater detail in FIGS. 14a-b, is arranged so that addresses greater than 110010 cause all zeroes to be outputted on lines I.sub.13 -I.sub.6 to multiplier multiplexer 415. Zeros are also stored in address locations 41-51. Thus, the chirp may be expanded to occupy up to address location fifty, if desired.
Random Access Memory Logic Diagram
Referring now to FIGS. 12a-12b, there is shown a composite detailed logic diagram of RAM 203. RAM 203 is addressed by address on PC1-PC4, which address is decoded in a PLA 203a and defines which coded parameter is to be inputted into RAM 203. RAM 203 stores the twelve decoded parameters, the parameters having bit lengths varing between three bits and five bits according to the decoding scheme described with reference to FIG. 6. Each cell, reference B, of RAM 203 is shown in greater detail in FIG. 12b. Read/Write control logic 203b is responsive to T1, DIV1, PC0 and parameter load enable for writing into the RAM 203 during the A cycle of each parameter count during interpolation count zero when enabled by parameter load enable from logics 238 (FIG. 8c). Data is inputted to RAM 203 on lines IN0-IN4 from register 205 as shown in FIGS. 8c and 8f and data is outputted on lines C0-C4 to ROM 202 as is shown in FIGS. 8f and 8e.
Parameter Read-Only-Memory Logic Diagram
In FIGS. 13a-13c, there is shown a logic diagram of ROM 202. ROM 202 is preferably a virtual ground ROM of the type disclosed in U.S. Pat. No. 3,934,233. Address information from ROM 202 and from parameter counter 513 are applied to address buffers 202b which are shown in detail at reference A. The NOR gates 202a used in address buffers 202b are shown in detail at reference B. The outputs of the address buffers 202b are applied to an X-decoder 202c or to a Y-decoder 202d. The ROM is divided into ten sections labeled reference C, one of which is shown in greater detail. The outline for output line from each of the sections is applied to register 201 via inverters as shown in FIGS. 8e and 8f. X-decoder selects one of fifty-four X-decode lines while Y-decoder 202d tests for the presence or nonpresence of a transistor cell between an adjacent pair of diffusion lines, as is explained in greater detail in the aforementioned U.S. Pat. No. 3,934,233. The data preferably stored in ROM 202 of this embodiment is listed in Table VI.
Chirp Read-Only-Memory Logic Diagram
FIGS. 14a-14b form a composite diagram of chirp ROM 409. ROM 409 is addressed via address lines A.sub.0 -A.sub.8 from register 410 (FIG. 11c) and output information on lines I.sub.6 -I.sub.11 to multiplier multiplexer 415 and lines I.sub.m1 and I.sub.m2 to gates 421 and 420, all which are shown in FIGS. 11a-11d. As was previously discussed with reference to FIGS. 11a-11d, chirp ROM outputs all zeros after a predetermined count is reached in register 410, which, in this case is the count equivalent to a decimal 51. ROM 409 includes a Y-decoder 409a which is responsive to the address on lines A.sub.0 and A.sub.1 (and A.sub.0 and A.sub.1) and an X-decoder 409b which is responsive to the address on lines A.sub.2 through A.sub.5 (and A.sub.2 -A.sub.5).
ROM 409 also includes a latch 409c which is set when decimal 51 is detected on lines A.sub.0 -A.sub.5 according to line 409c from a decoder 409e. Decoder 409e also decodes a logical zero on lines A.sub.0 -A.sub.8 for resetting latch 409c. ROM 409 includes timing logics 409f which permit data to be clocked in via gates 409g at time period T12. At this time decoder 409e checks to determine whether either a decimal 0 or decimal 51 is occurring on address lines A.sub.0 -A.sub.8. If either condition occurs, latch 409c, which is a static latch, is caused to flip.
An address latch 409h is set at time period T13 and reset at time period T11. Latch 409h permits latch 409c to force a decimal 51 onto lines A.sub.0 -A.sub.5 when latch 409c is set. Thus, for addresses greater than 51 address register 410, the address is first sampled at time period T12 to determine whether it has been reset to zero by reset logic 412 (FIG. 11c) for the purpose of resetting latch 409c and if the address has not been reset to zero then whatever address has been inputted on lines A.sub.0 -A.sub.8 is written over by logics 409j at T13. Of course, at location 51 in ROM 409 will be stored all zeros on the output lines I6-I11, IM1 and IM2. Thus by the means of logics 409c, 409h and 409j addresses of a preselected value, in this case a decimal 51, are merely tested to determine whether a reset has occurred but are not permitted to address the array of ROM cells via decoders 409a and 409b. Addresses between a decimal 0 and 50 address the ROM normally via decoders 409a and 409b. The ROM matrix is preferably of the virtual ground type described in U.S. Pat. No. 3,934,233. As aforementioned, the contents of ROM 409 are listed in Table VIII. The chirp function is located at addresses 00-40 while zeros are located at addresses 41-51.
Truncation Logic and Digital-To-Analog Converter
Turning again to FIGS. 11a-11d, the truncation logic 425 and Digital-to-Analog (D/A) converter are shown in detail. Truncation logic 425 includes circuitry for converting the two's complement data on YL.sub.13 -YL.sub.14 to sign magnitude data. Logics 425a test the MSB from Y-latch 403 on line YL.sub.13 for the purpose of generating a sign bit and for controlling the two's complement to sign magnitude conversion accomplished by logics 425c. The sign bit is supplied in true and false logic on lines D/Asn and D/Asn to D/A converter 426.
Logics 425c convert the two's complement data from Y-latches 403 in lines YL.sub.10 -YL.sub.4 to simple magnitude notation on lines D/A.sub.6 -D/A.sub.0. Only the logics 425c associated with YL10 are shown in detail for sake of simplicity.
Logics 425b sample the YL.sub.12 and YL.sub.11 bits from the Y-latches 403 and perform a magnitude truncation function thereon by forcing outputs D/A.sub.6 through D/A.sub.0 to a logical zero (i.e., a value of one if the outputs were in true logic) wherever either YL.sub.12 or YL.sub.11 is a logical one and YL.sub.13 is a logical zero, indicating that the value is positive or either YL.sub.12 or YL.sub.11 is a logical zero and YL.sub.13 is a logical one, indicating that the value is negative (and complemented, of course). Whenever one of these conditions occurs, a logical zero appears on line 427 and Vss is thereby coupled to the output buffer 428 in each of logics 425c. The magnitude function effectively truncates the more significant bits on YL.sub.11 and YL.sub.12. It is realized that this is comewhat unorthodox truncation, since normally the less significant bits are truncated in most other circuits where truncation occurs. However, in this circuit, large positive or negative values are effectively clipped. More important digital speech information, which has smaller magnitudes, is effectively amplified by a factor of four by this truncation scheme.
The outputs D/A.sub.6 -D/A.sub.0, along with D/Asn and D/Asn, are coupled to D/A converter 426. D/A converter 426 preferably has seven MOS devices 429 coupled to the seven lines D/A.sub.6 through D/A.sub.0 from truncation logics 425. Each device 429 preferably includes a MOS transistor whose gates is coupled to one of the lines D/A.sub.6 -D/A.sub.0 and a series connected implanted load transistor 429b. Devices 429 are arranged, by controlling their length to width ratios, to act as current sources, the device 429 coupled to D/A.sub.6 sourcing twice as much current (when on) as the device 429 coupled to D/A.sub.5. Likewise the devices 429 coupled to D/A.sub.5 is capable of sourcing twice as much current as the device 429 coupled to D/A.sub.4. This two to one current sourcing capability similarly applies to the remaining devices 429 coupled to the remaining lines D/A.sub.3 -D/A.sub.0. Thus, device 429 coupled to D/A.sub.1, is likewise capable of sourcing twice as much current as the device 429 coupled to D/A.sub.0, but only one-half of that source by the device 429 coupled to D/A.sub.2. All devices 429 are connected in parallel, one side of which are preferably coupled to Vss and the other side is preferably coupled to either side of the speaker 4 via transistors 430 and 431. Transistor 430 is controlled by D/Asn which is applied to its gates; transistor 431 is turned off and on in response to D/Asn. Thus, either transistor 430 or 431 is on depending on the state of the sign bit, D/Asn. The voice coil of speaker 4 preferably has a 100 ohm impedance and has a center tap connected to Vgg, as shown in FIG. 23a. Thus, the signals on lines D/A.sub.6 -D/A.sub.0 control the magnitude of current flow through the voice coil while the signals on lines D/Asn and D/Asn control the direction of that flow.
Alternatively to using a center-topped 100 ohm voice coil, a more conventional eight ohm speaker may be used along with a transformer having a 100 ohm center topped primary (connected to Vgg and transistors 430 and 431) and an eight ohm secondary (connected to the speaker's terminals), as shown in FIG. 23b;
It should now be appreciated by those skilled in the art that D/A converter 426 not only converts digital sign magnitude information on lines D/A.sub.6 -D/A.sub.0 and D/Asn-D/Asn to an analog signal, but has effectively amplified this analog signal to sufficient levels to permit a speaker to be driven directly from the MOS synthesis chip 10 (or via the aforementioned transformer, if desired). Of course, those skilled in the art will appreciate that simple D/A converters, such as that disclosed here, will find use in other applications in addition to speech synthesis circuits.
THE SPEECH SYNTHESIZER CHIP
In FIG. 22 a greatly enlarged plan view of a semiconductor chip which contains the entire system of FIGS. 4a and 4b is illustrated. The chip is only about two hundred fifteen mils (about 0.215 inches) on a side. In the example shown, the chip is manufactured by the P-channel metal gate process using the following design rules: metal line width 0.25 mil; metal line spacing 0.25 mil; diffusion line width 0.15 mil; and diffusion line spacing 0.30 mil. Of course, as design rules are tightened with the advent of electron beam mask production or slice writing, and other techniques, it will be possible to further reduce the size of the synthesizer chip. The size of the synthesizer chip can, of course also be reduced by not taking advantage of some of the features preferably used on the synthesizer chip.
The total active area of speech synthesizer chip 10 is approximately 45,000 square mils.
It will also be appreciated by those skilled in the art, that other MOS manufacturing techniques, such as N-channel, complementary MOS (CMOS) or silicon gate processes may alternatively be used.
The various parts of the system are labeled with the same reference numerals previously used in this description.
CONTROLLER LOGIC DIAGRAMS
The controller used in the learning aid is preferably a microprocessor of the type described in U.S. Pat. No. 4,074,355, with modifications which are subsequently described. U.S. Pat. No. 4,074,355 is hereby incorporated herein by reference. It is to be understood, of course, that other microprocessors, as well as future microprocessors, may well find use in applications such as the speaking learning aid described herein.
The microprocessor of U.S. Pat. No. 4,074,355 is an improved version of an earlier microprocessor described in U.S. Pat. No. 3,991,305. One of the improvements concerned the elimination of digit driver devices so that arrays of light emitting diodes (LED's) forming a display could be driven directly from the microprocessor. As a matter of design choice, the display used with this learning aid is preferably a vacuum fluorescent (VF) display device. Those skilled in the art will appreciate that when LED's are directly driven, the display segments are preferably sequentially actuated while the display's common character position electrodes are selectively actuated according to information in a display register or memory. When VF displays are utilized, on the other hand, the common character position electrodes are preferably sequentially actuated while the segments are selectively actuated according to information in the display register or memory. Thus, the microprocessor of U.S. Pat. No. 4,074,355 is preferably altered to utilize digit scan similar to that used in U.S. Pat. No. 3,991,305.
The microprocessor of U.S. Pat. No. 4,074,355 is a four bit processor and to process alphanumeric information, additional bits are required. By using six bits, which can represent 2.sup.6 or 64 unique codes, the twenty-six characters of the alphabet, ten numerals as well as several special characters can be handled with ease. In lieu of converting the microprocessor of U.S. Pat. No. 4,074,355 directly to a six bit processor, it was accomplished indirectly by software pairing the four bit words into eight bit bytes and transmitting six of those bits to the display decoder.
Referring now to FIGS. 15a-15b, which form a composite block diagram of the microprocessor preferably used in the learning aid, it should be appreciated that this block diagram generally corresponds with the block diagram of FIGS. 7a and 7b of U.S. Pat. No. 4,074,355; several modifications to provide the aforementioned features of six bit operation and VF display compatability are also shown. The numbering shown in FIGS. 15a and 15b generally agrees with that of U.S. Pat. No. 4,074,355. The modifications will now be described in detail.
Referring now to the composite diagram formed by FIGS. 16a-16c, which replace FIG. 13 of U.S. Pat. No. 4,074,355, there can be seen the segment decoder and RAM address decoder 33-1 which decodes RAMY for addressing RAM 31 or ACC1-ACC8 for decoding segment information. Decoder 33-1 generally corresponds to decoder 33 in the aforementioned U.S. patent. The segment information is re-encoded into particular segment line information in output section 32-2 and outputted on bus 90 to segment drivers 91. Six bits of data from the processor's four bit accumulator 77 are decoded in decoder 33-1 as is now described. First, four bits on bus 86 are latched into accumulator latches 87-1 through 87-8 on a TDO (Transfer Data Out) instruction when status is a logical one. Then, two bits on bus 86 (from lines 86-1 and 86-2) are latched into accumulator latches 87-16 and 86-32, respectively, on another TD0 instruction when status is a logical zero. Then the six bits in latches 87-1 through 87-32 are decoded in decoder 33-1. Segment drivers 91 may preferably be of one of three types, 91A, 91B or 91C as shown in FIGS. 16 a-16c. The 91A type driver permits the data on ACC1-ACC8 to be communicated externally via pins SEG G, SEG B, SEG C and SEG D. The 91B type driver coupled to pin SEG E permits the contents of digit register 94-10 to be communicated externally when digit register 94-12 is set. The 91C type driver coupled to pin SEG A permits the contents of the program counter to be outputted during test operations.
The digit buffers registers and TD0 latches of FIG. 14 of U.S. Pat. No. 4,074,355 are also preferably replaced with the digit buffers registers of FIG. 17 herein inasmuch as (1) the DDIG signal is no longer used and (2) the digit latches (elements 97 in U.S. Pat. No. 4,074,355) are no longer used. For simplicity's sake, only one of the digit output buffer registers 94 is shown in detail. Further, since in this embodiment of the learning aid, display 2 preferably has eight character positions, eight output buffers 98-0 through 98-7 connect D.sub.0 -D.sub.7 to the common electrodes of display 2 via registers 94-0 through 94-7 as shown in FIG. 17. An additional output buffer 98-8 communicates the contents of register 94-12, which is the chip select signal, to synthesizer 10.
To facilitate bi-directional communication with synthesizer 10, the microprocessor of U.S. Pat. No. 4,074,355 is preferably modified to permit bi-directional communication on pins SEG G, SEG B, SEG C and SEG D. Thus, in FIG. 18, these SEG pins are coupled to the normal K lines, 112-1 through 112-8, via an input selector 111a for inputting information when digit register 94-12 (R12) is set. Further, these pins are also coupled to ACC1-ACC8 via segment drivers 91A when digit registers 94-12 (R12) and 94-11 (R11) are set for outputting information in accumulator 77.
Thus, when digit latch 94-12 (which communicates the chip select signal externally) is set, SEG E is coupled to R10 (digit register 94-10) for communicating the PDC signal to synthesizer 10. Also, ACC1-ACC8 is outputted on SEG G and SEG B-SEG D, during the time R12 and R11 are set. When R11 is a logical 0, i.e., is reset, segment drivers 91A are turned off and data may be read into CKB circuit 113 for receiving data from ROMs 12A-12B via synthesizer 10, for instance. FIG. 18 replaces the keyboard circuit 111 shown in FIG. 22 of U.S. Pat. No. 4,064,554.
Preferably, pins SEG G and SEG B-SEG D are coupled to CTL1-CTL8 pins of synthesizer 10, while pin SEG E is coupled to the PDC pin of synthesizer 10.
In Table IX (which comprises Tables 0 through IX-15) is listed the set of instructions which may be stored in the main Read-Only-Memory 30 of FIGS. 15a-15b to provide controller 11. Referring now to Table IX, there are several columns of data which are, reading from left to right: PC (Program Counter), INST (Instruction), BRLN (Branch Line), Line and Source Statement (which includes Name, Title and Comments). In U.S. Pat. No. 4,074,355, it can be seen that main Read-Only-Memory 30 is addressed with a seven bit address in program counter 47 and a four bit address in a buffer 60. The address in buffer 60 is referred to as a page address in the main Read-Only-Memory. The instructions listed on Table IX-0 correspond to page zero in the microprocessor while the instructions listed in Table IX-1 are those on page one and so forth through to the instructions in Table IX-15 which are stored on page fifteen in the microprocessor.
The program counter 47 of the aforementioned microprocessor is comprised of a feedback shift register and therefore counts in a pseudorandom fashion, thus the addresses in the left-hand column of Table IX, which are expressed as a hexadecimal number, exhibit such pseudorandomness. If the instruction starting at page zero were read out sequentially from the starting position in the program counter (00) then the instructions would be read out in the order shown in Table IX. In the "Line" column is listed a sequentially increasing decimal number associated with each source statement and its instruction and program counter address as well as those lines in which only comments appear. The line number starts at line 55 merely for reasons of convenience not important here. When an instruction requiring either a branch or call is to be performed, the address to which the program counter will jump and the page number to which the buffer will jump, if required, is reflected by the binary code comprising the instruction or instructions performing the branch or call. For sake of convenience, however, the branch line column indicates the line number in Table IX to which the branch or call will be made. For example, the instruction on line 59 (page 0, Program Counter Address 0F) is a branch instruction, with a branch address of 1010111 (57 in hexadecimal). To facilitate finding the 57 address in the program counter, the branch line column directs the reader to line 80, where the 57 address is located.
READ-ONLY-MEMORY LOGIC DIAGRAMS
Any one of Read-Only-Memories 12A and 12B or 13A and 13B is shown in FIGS. 19, 20a-20f, 21a and 21b. FIG. 19 is a block diagram of any one of these ROMs. FIGS. 20a-20f form a composite logic diagram of the control logic for the ROMs while FIGS. 21a and 21b form a composite logic diagram of the X and Y address decoders and pictorially show the array of memory cells.
Referring now to FIG. 19, the ROM array 601 is arranged with eight output lines, one output line from each section of 16,384 bits. The eight output lines from ROM array 601 are connected via an output latch 602 to an eight bit output register 603. The output register 603 is interconnected with pins ADD1-ADD8 and arranged either to communicate the four high or low order bits from output register 603 via the four pins ADD1-ADD8 or alternatively to communicate the bit serially from output register 603 via pin ADD1. The particular alternative used may be selective according to mask programmable gates.
ROM array 601 is addressed via a 14 bit address counter 604. The address counter 604 has associated therewith a four bit chip select counter 605. Addresses in address counter 604 and chip select counter 605 are loaded four bits at a time from pins ADD1-ADD8 in response to a decoded Load Address (LA) command. The first LA command loads the four least significant bits in address counter 604 (bits A.sub.0 -A.sub.3), and subsequent LA commands load the higher order bits, (A.sub.4 -A.sub.7, A.sub.8 -A.sub.11 and A.sub.12 -A.sub.13). During the fourth LA cycle the A.sub.12 and A.sub.13 bits are loaded at the same time the CS0 and CS1 bits in chip select counter 605 are loaded. Upon the fifth LA command the two most significant bits in chip select counter 605 are loaded from ADD1 and ADD2. A counter 606 counts consecutively received LA commands for indicating where the four bits on ADD1-ADD8 are to be inputted into counters 604 and/or 605.
Commands are sent to the ROM chip via I.sub.0 and I.sub.1 pins to a decoder 607 which outputs the LA command a TB (transfer bit) and a RB (read and branch) command.
Address register 604 and chip select register 605 have an add-one circuit 608 associated therewith for incrementing the address contained therein. When a carry occurs outside the fourteen bit number stored in address register 604 the carry is carried into chip select register 605 which may enable the chip select function if not previously enabled or disable the chip select function if previously enabled, for example. Alternatively, the eight bit contents of output register 603 may be loaded into address register 604 by means of selector 609 in response to an RB command. During an RB command, the first byte read out of array 601 is used as the lower order eight bits while the next successive byte is used for the higher order six bits in counter 604.
The output of chip select register 605 is applied via programmable connectors 610 to gate 611 for comparing the contents of chip select counter 605 with a preselected code entered by the programming of connectors 610. Gate 611 is also responsive to a chip select signal on the chip select pin for permitting the chip select feature to be based on either the contents of the four bit chip select register 605 and/or the state of the chip select bit on the CS pin. The output of gate 611 is applied to two delay circuits 612, the output of which controls the output buffers associated with outputting information from output register 603 to pins ADD1-ADD8. The delay imposed by delay circuits 612 effect the two byte delay in this embodiment, because the address information inputted on pins ADD1-ADD8 leads the data outputted in response thereto by the time to require to access ROM array 601. The CS pin is preferably used in the embodiment of the learning aid disclosed herein.
A timing PLA 600 is used for timing the control signals outputted to ROM array 601 as well as the timing of other control signals.
Referring now to the composite drawing formed by FIGS. 20a-20f, output register 603 is formed by eight "A" bit latches, an exemplary one of which is shown at 617. The output of register 603 is connected in parallel via a four bit path controlled on LOW or HIGH signals to output buffers 616 for ADD1-ADD4 and 616a for ADD8.
Gates 615 which control the transferring of the parallel outputs from register 603 via in response to LOW and HIGH are preferably mask level programmable gates which are preferably not programmed when this chip is used with the learning aid described herein. Rather the data in register 603 is communicated serially via programmable gate 614 to buffer 616a and pin ADD8. The bits outputted to ADD1-ADD8 in response to a HIGH signal are driven from the third through sixth bits in register 603 rather that the fourth through seventh bits inasmuch as a serial shift will normally be accomplished between a LOW and HIGH signal.
Address register 604 comprises fourteen of the bit latches shown at 617. The address in address 604 on lines A.sub.0 -A.sub.13 is communicated to the ROM X and Y address buffers. Register 604 is divided into four sections 604a-604d, the 604d section loading four bits from ADD1-ADD8 in response an LA0 signal, the 604c section loading four bits from ADD1-ADD8 in response to an LA1 signal and likewise for section 604b in response to an LA2 signal. Section 604a is two bits in length and loads the ADD1 and ADD2 bits in response to an LA3 signal. The chip select register 605 comprise four B type bit latches of the type shown at 618. The low order bits, CS0 and CS1 are loaded from ADD4 and ADD8 in response to an LA3 signal while the high order bits CS2 and CS3 are loaded from ADD1 and ADD2 on an LA4 signal. The LA0-LA4 signals are generated by counter 606. Counter 606 includes a four bit register 619 comprised of four A bit latches 617. The output of the four bit counter 619 is applied to a PLA 620 for decoding the LA1-LA4 signals. The LA0 signal is generated by a NAND gate 621. As can be seen, the LA0 signal comes up in response to an LA signal being decoded immediately after a TB signal. The gate 621 looks for a logical one on the LA signal and a logical one on an LTBD (latched transfer bit delay) signal from latch 622. Decoder 607 decodes the I.sub.0 and I.sub.1 signals applied to pins I.sub.0 and I.sub.1 for decoding the TB, LA and RB control signals. The signals on the I.sub.0 and I.sub.1 pins are set out in Table X. Latch circuit 622 is responsive to LA, RB and TB for indicating whether the previously received instruction was either an LA or a TB or RB command.
In addition to counting successive LA commands, four bit counter 619 and PLA 620 are used to count successive TB commands. This is done because in this embodiment each TB command transfers one bit from register 603 on pin ADD8 to the synthesizer chip 10 and output register 603 is loaded once each eight successive TB commands. Thus, PLA 620 also generates a TB8 command for initiating a ROM array addressing sequence. The timing sequence of counter 619 and PLA 620 are set forth in Table XI. Of course, the LA1-LA4 signal is only generated responsive to successive LA commands while the TB8 signals only generate in response to successive TB commands.
Add-one circuit 608 increments the number in program counter 604 in response to a TB command or an RB command. Since two successive bytes are used as a new address during an RB cycle, the card address and the present address incremented by one must be used to generate these two bytes. The output of add-one circuit 608 is applied via selector 609 for communicating the results of the incrementation back to the input of counter 604. Selector 609 permits the bits in output register 603 to be communicated to program counter 604 during an RB cycle as controlled by signal BR from array 600. Add-one circuit 608 is also coupled via COUNT to chip select counter 605 for incrementing the number stored therein whenever a CARRY would occur outside the fourteen bits stored in program counter 604. The output of chip select counter 605 is applied via programmable gate 610 to gate 611. The signal on the CS pin may also be applied to gate 611 or compared with the contents of CS3. Thus, gate 611 can test for either (1) the state of the CS signal, (2) a specific count in counter 605 or (3) a comparison between the state on the chip select and the state of CS3 or (4) some combination of the foregoing, as may be controlled by those knowledgeable in the art according to how programmable links 610 are programmed during chip manufacture. The output of gate 611 is applied via two bit latches of the C type, which are shown at 622. Timing array 600 controls the timing of ROM sequencing during RB and TB sequences. Array 600 includes PLA sections 600a and 600b and counters 623 and 624. Counter 623 is a two bit counter comprising two A type bit latches shown at 617. Counter 623 counts the number of times a ROM access is required to carry out a particular instruction. For instance, a TB command requires one ROM access while an RB command requires three ROM accesses. Counter 624, which comprises four "A" type bit latches of the type shown at 617, counts through the ROM timing sequence for generating various control signals used in accessing ROM array 601. The timing sequence for a TB command is shown in Table XII which depicts the states in counters 623 and 624 and the signals generated in response thereto. A similar timing sequence for an RB command is shown in Table XIII. The various signals generated by PLA 600a and 600b will now be briefly described. The BR signal controls the transfer of two serial bits from the output register 603 to the program counter 604. The TF signal controls the transfer of eight bits from the sense amp output latch 602 (FIG. 19) to output register 603 on lines SA0-SA7. INC controls the serial incrementing of the program counter, two bits for each INC signal generated. PC is the precharge signal for the ROM array and normally exists for approximately ten microseconds. The DC signal discharges the ROM 601 array and preferably lasts for approximately ten microseconds for each DC signal. This particular ROM array uses approximately seventy microseconds to discharge and thus seven DC signals are preferably generated during each addressing sequence. SAM gates the data outputted from the ROM into the sense amp output latch 602 while SAD sets the address lines by gating the address from the program counter into the ROM address buffers.
ALTERNATIVE EMBODIMENTS
Although the invention has been described with reference to a specific embodiment, this description is not meant to be construed in a limiting sense. Various modifications of the disclosed embodiment as well as alternative embodiments of the invention will become apparent to persons skilled in the art upon reference to the description of the invention. It is therefore contemplated that the appended claims will cover any such modifications or embodiments that fall within the true scope of the invention.
TABLE I______________________________________THE FOLLOWING SEQUENCE IS AN EXAMPLE OF THELEARNING AID IN THE SPELLING MODE.KEY DISPLAY SPEAKER______________________________________COMPUSPELL 4 RANDOM TONES SPELL AB SPELL B BC SPELL C CD SPELL D DP SPELL D PA SPELL A AGO -- SPELL DO AS IN DO NOTD D- DO DO- OENTER DO THAT IS CORRECT, NOW SPELL -- WASW W- WU WU- US WUS- SERASE --W W- WA WA- AS WAS- SENTER WAS THAT IS RIGHT, NEXT SPELL -- ANYA A- AN AN- NI ANI- IENTER ANI TRY AGAIN, -- ANY --REPEAT -- ANYREPEAT -- ANY (1/2 SPEED)E E- EN EN- NY ENY- YENTER ENY THAT IS INCORRECT, THE CORRECT SPELLING OF ANY IS A A AN N ANY Y ANY ANY NOW TRY FULLF F- FU FU- UL FUL- LL FULL- L FULL THAT IS CORRECT, TRY SHOE MEANING FOOTWEAR --S S- SH SH- HO SHO- OE SHOE- EENTER SHOE YOUR ARE CORRECT, SPELL COMBC C- CO CO- OM COM- ME COME- EENTER COME TRY AGAIN, -- COMBC C-O CO-M COM-B COMB-ENTER COMB YOU ARE CORRECT, NOW SPELL FOUR AS IN -- THE NUMBERF F- FO FO- OU FOU- UR FOUR- RENTER FOUR THAT IS CORRECT, -- NEXT SPELL WHOW W- WH WH- HO WHO- OENTER WHO YOU ARE RIGHT, -- NOW TRY SOUPS S- SO SO- OU SOU- UP SOUP- PENTER SOUP THAT IS RIGHT, -- TRY MOSTM M- MO MO- OS MOS- ST MOST- TENTER MOST YOU ARE CORRECT +8 -2 4 TONES +8 -2 4 TONES +8 -2 HERE IS YOUR SCORE, EIGHT CORRECT, TWO DID NOT COMPUTE.______________________________________
TABLE II______________________________________LEARN MODEKEY DISPLAY SPEAKER______________________________________ BUSY (1 SECOND PAUSE) SAY IT (2 SECOND PAUSE) BUSY MANY (1 SECOND PAUSE) SAY IT (2 SECOND PAUSE) MANY CARRY (1 SECOND PAUSE) SAY IT (2 SECOND PAUSE) CARRY YOUR (1 SECOND PAUSE) SAY IT (2 SECOND PAUSE) YOUR WILD (1 SECOND PAUSE) SAY IT (2 SECOND PAUSE) WILD LOVE (1 SECOND PAUSE) SAY IT (2 SECOND PAUSE) LOVE BUSH (1 SECOND PAUSE)REPEAT SAY ITREPEAT IG- (2 SECOND PAUSE)REPEAT NORED BUSHREPEAT EARN (1 SECOND PAUSE) SAY IT (2 SECOND PAUSE) EARN -- SPELL MANYM M- MA MA- AN MAN- NY MANY- YENTER MANY YOU ARE CORRECT, -- NOW SPELL EARN______________________________________ THE LEARNING AID CONTINUES THROUGH THE REMAINING 9 WORDS AS IN THE SPELLING MODE.
TABLE III______________________________________IN THE WORD GUESSER MODE THE LEARNING AIDRANDOMLY SELECTS A WORD FROM LEVEL C OR DAND DISPLAYS DASHES TO REPRESENT THE NUMBEROF LETTERS IN THE CHOSEN WORD. THE USER TRIESTO GUESS THE WORD. THE USER MUST COMPLETETHE WORD BEFORE MAKING SEVEN INCORRECTGUESSES. THE FOLLOWING IS AN EXAMPLE OF THEFUNCTION OF THE LEARNING AIDIN THE SPELLING MODE.KEY DISPLAY SPEAKER______________________________________HANGMAN 4 TONES A E E-E----E 4 TONES I E-E----E O E-E--O-E 4 TONES U E-E--O-E B E-E--O-E C E-E--O-E D E-E--O-E F E-E--O-E EVERYONE 4 TONES, I WIN A E E 4 TONES I E O O---E 4 TONES U OU--E 4 TONES B OU--E C COU--E 4 TONES R COUR-E 4 TONES S COURSE 4 TONES COURSE 4 TONES, YOU WIN______________________________________
TABLE IV______________________________________The synthesizer 10 includes interpolation logics to accomplish anearly linear interpolation of all twelve speech parameters ateight points within each frame, that is, once each 2.5 msec. Theparameters are interpolated one at a time as selected by theparameter counter. The interpolation logics calculate a new valueof a parameter from its present value (i.e. the value currentlystored in the K-stack, pitch register or E-10 loop) and the targetvalue stored in encoded form in RAM 203 (and decoded by ROM202). The value computed by each interpolation is listed below.Where P.sub.i is the present value of the parameter, P.sub.i+l is the new parameter value P.sub.t is the target value N.sub.i is an integer determined by the interpolation counter ##STR1## INTERPOLATION COUNT N.sub.i ##STR2##______________________________________1 8 0.1252 8 0.2343 8 0.3304 4 0.4985 4 0.6236 2 0.7177 2 0.8590 1 1.000______________________________________
TABLE V______________________________________" HELP" ##STR3## ##STR4##______________________________________
TABLE VI__________________________________________________________________________DECODED PARAMETERSCODE E P K1 K2 K3 K4 K5 K6 K7 K8 K9 K10__________________________________________________________________________00 000 000 208 2A3 273 28F 201 2DE 20D 326 31F 34D01 000 029 20B 2BA 293 282 2B2 304 300 37B 363 38602 001 02B 213 2CF 289 2DH 306 32F 32A 3DA 3AF 3C303 001 02D 218 2BA 2E6 30H 32D 35D 352 038 3FD 00104 002 02F 220 304 31B 341 35B 38E 380 098 04C 03F05 003 031 229 321 356 37D 386 3C2 3B0 03B 097 07B06 005 033 234 340 398 3BD 386 3F7 3B1 131 0DC 08307 007 035 242 362 3DC 3FF 3E7 02C 013 169 118 0F708 00A 037 255 384 023 040 01A 061 04509 00F 03A 268 3AB 068 080 099 093 0750A 015 03C 286 3CD 049 0BC 079 0C2 0A30B 01F 03F 2AB 3F2 0F4 0F3 0A7 0EF 0CF0C 02B 042 2DF 017 119 123 0D2 116 0F60D 03D 046 2FD 03C 146 14C 0F9 139 1180E 056 049 332 061 16C 16F 11D 158 13C0F 000 04C 36C 085 18C 18D 13E 173 15910 04F 344 04711 053 3FB 0C712 057 02D 0E613 05A 06E 10314 05E 04B 11F15 063 0F3 13616 067 115 14D17 06B 140 16218 070 165 17419 076 184 1851A 07B 190 1941B 081 182 1411C 086 103 1401D 08C 100 1871E 094 1D4 1011F 099 1E2 1FA__________________________________________________________________________
TABLE VII__________________________________________________________________________DATA OUTPUTTED FROM K-STACK 302 TO RECODING LOGIC301 BY TIME PERIODSK-STACKOUTPUT TIME PERIODS__________________________________________________________________________BIT LINE T8 T9 T10 T11 T12 T13 T14 T15 T16 T17__________________________________________________________________________LSB 32-1 K.sub.2 K.sub.1 A K.sub.9 K.sub.8 K.sub.7 K.sub.6 K.sub.5 K.sub.4 K.sub.3 32-2 K.sub.2 K.sub.1 A K.sub.9 K.sub.8 K.sub.7 K.sub.6 K.sub.5 K.sub.4 K.sub.3 32-3 K.sub.2 K.sub.1 A K.sub.9 K.sub.8 K.sub.7 K.sub.6 K.sub.5 K.sub.4 K.sub.3 32-4 K.sub.2 K.sub.1 A K.sub.9 K.sub.8 K.sub.7 K.sub.6 K.sub.5 K.sub.4 K.sub.3 32-5 K.sub.3 K.sub.2 K.sub.1 A K.sub.9 K.sub.8 K.sub.7 K.sub.6 K.sub.5 K.sub.4 32-6 K.sub.3 K.sub.2 K.sub.1 A K.sub.9 K.sub.8 K.sub.7 K.sub.6 K.sub.5 K.sub.4 32-7 K.sub.4 K.sub.3 K.sub.2 K.sub.1 A K.sub.9 K.sub.8 K.sub.7 K.sub.6 K.sub.5 32-8 K.sub.4 K.sub.3 K.sub.2 K.sub.1 A K.sub.9 K.sub.8 K.sub.7 K.sub.6 K.sub.5 32-9 K.sub.5 K.sub.4 K.sub.3 K.sub.2 K.sub.1 A K.sub.9 K.sub.8 K.sub.7 K.sub.6MSB 32-10 K.sub.5 K.sub.4 K.sub.3 K.sub.2 K.sub.1 A K.sub.9 K.sub.8 K.sub.7 K.sub.6__________________________________________________________________________BIT LINE T18 T19 T20 T21 T22 T23 T24 T25 T26 T27__________________________________________________________________________LSB 32-1 K.sub.2 K.sub.1 K.sub.10 K.sub.9 K.sub.8 K.sub.7 K.sub.6 K.sub.5 K.sub.4 K.sub.3 32-2 K.sub.2 K.sub.1 K.sub.10 K.sub.9 K.sub.8 K.sub.7 K.sub.6 K.sub.5 K.sub.4 K.sub.3 32-3 K.sub.2 K.sub.1 K.sub.10 K.sub.9 K.sub.8 K.sub.7 K.sub.6 K.sub.5 K.sub.4 K.sub.3 32-4 K.sub.2 K.sub.1 K.sub.10 K.sub.9 K.sub.8 K.sub.7 K.sub.6 K.sub.5 K.sub.4 K.sub.3 32-5 K.sub.3 K.sub.2 K.sub.1 K.sub.10 K.sub.9 K.sub.8 K.sub.7 K.sub.6 K.sub.5 K.sub.4 32-6 K.sub.3 K.sub.2 K.sub.1 K.sub.10 K.sub.9 K.sub.8 K.sub.7 K.sub.6 K.sub.5 K.sub.4 32-7 K.sub.4 K.sub.3 K.sub.2 K.sub.1 K.sub.10 K.sub.9 K.sub.8 K.sub.7 K.sub.6 K.sub.5 32-8 K.sub.4 K.sub.3 K.sub.2 K.sub.1 K.sub.10 K.sub.9 K.sub.8 K.sub.7 K.sub.6 K.sub.5 32-9 K.sub.5 K.sub.4 K.sub.3 K.sub.2 K.sub.1 K.sub.10 K.sub.9 K.sub.8 K.sub.7 K.sub.6MSB 32-10 K.sub.5 K.sub.4 K.sub.3 K.sub.2 K.sub.1 K.sub.10 K.sub.9 K.sub.8 K.sub.7 K.sub.6__________________________________________________________________________
TABLE VIII______________________________________CHIRP ROM CONTENTS CHIRP FUNCTION STORED VALUEADDRESS VALUE (COMPLEMENTED)______________________________________00 00 FF01 2A D502 D4 2B03 32 CD04 B2 4D05 12 ED06 25 DA07 14 EB08 02 FD09 E1 IE10 C5 3A11 02 FD12 5F A013 5A A514 05 FA15 0F F016 26 D917 FC 0318 A5 5A19 A5 5A20 D6 2921 DD 2222 DC 2323 FC 0324 25 DA25 2B D426 22 DD27 21 DE28 0F F029 FF 0030 F8 0731 EE 1132 ED 1233 EF 1034 F7 0835 F6 0936 FA 0537 00 FF38 03 FC39 02 FD40 01 FE______________________________________
TABLE IX-0__________________________________________________________________________LEARNING AID INSTRUCTION SETAdd- Branchress Instruction Line Line Name Title Comments__________________________________________________________________________0000 000101110 0055 HD3 TAMZA ADD 5 TO KEY0001 001111010 0056 ACACC 5 CODE EACH TIME0003 001000111 0057 TCY 14 N-LINE POINTER IS DECREMENTED0007 111011000 0112 0058 CALI ADDCARRY0008 101010111 3089 0059 BRANCH WD20016 001100000 0060 KEYDOWN TCHIY 0 RESET DEBOUNCE COUNTEN0045 010011000 0061 LOX 10075 001000111 0062 TCY 140078 000001010 0063 TKM0078 000110011 0064 MNFZ DOUBLE CHECK KEY DOWN0074 101011111 0068 0065 BRANCH KD10077 010010000 0066 LDX 00066 100110110 0154 0067 BRANCH CARS KEY DOT DOWN0056 010011000 0068 KD1 LDX 00036 001100000 0069 TCMIY 00070 001100000 0070 TCMIY 00079 001001011 0071 TCY 130074 000101010 0072 IMY0087 000110110 0073 RSTR RESET PRESENT N-LINE0088 001001011 0071 TCY 130016 000000110 0078 CIA0036 001110110 0076 ACACO 6 PUT 6 IN ACC0074 000001110 0077 KMEZ SEE IF KEY IS ON VSS0075 101010111 9680 0178 BRANCH K02 VSS0068 000101001 4877 IM40057 000101111 0086 KD2 IAM *STORE 6 IF K=VSS0025 001001011 0081 TCY 140056 000000111 0082 DMAQ0033 100000000 0055 0083 BRANCH KD30079 010011000 0080 SUMMIT TDX DNF *HUMP ROUTINE TO CALCUL. VALUE OF KP0081 001000111 0085 TCY VALUE **0083 000101001 0086 TMA **0006 011100100 0087 ALFC 20068 101010111 0046 0068 BRANCH ANNI+50018 001111111 0089 ACACC 150057 011101100 9690 ALFC 30068 101010011 0096 0081 BRANCH ANND+50059 001111011 0083 ACACC 130054 011100011 0093 ALFC 40075 101010011 0090 0094 BRANCH ANND+50069 001110101 0095 ACACC 100053 001111111 0096 ANND+5 ACACC MINOS+1 **0028 010010000 0097 IDX ZERO **0040 001000111 0098 TCY VALUE **0018 111011000 0112 0099 CALL ADDCARRY0081 010001111 0100 EVL+OUT BL REVBEAL0062 100001100 2242 0101 0102 *THIS ROUTINE USES ,CARRY, 10 INCREMENT THE RANDOM NUMBER/TIMEOUT COUNTER0089 001000011 0103 TIME UP TCY 120084 000001110 0104 KNFZ0015 100011101 0128 0105 BRANCH CAR20028 010011100 0108 TIMEUP: FOX 30058 001000001 0197 TCY 80020 100000010 0116 0108 BRANCH CARRYON 0109 * 0110 *CARRY: FOR ADDITION IN NOM ADDR SECTION OF RAM 0111 *0056 000010101 0112 ADDCARRY ANAAC0036 101000001 0115 0113 BRANCH CARRY0080 100000011 0110 0014 BRANCH NOCARRY0081 000101001 0115 CARRY TAKIVC CARRY0002 000110000 0116 CARRYON IMAC INCREMENT MEN IF CARRY0005 101000001 0015 0017 BRANCH CARRY0008 000100111 0018 NOCARRY TAH0017 010111111 0119 RETR0026 001000011 0120 TCY 120058 000101001 0121 IMA0030 011101100 0122 ALFO 3 CHECK TIMEOUT COUNTER0078 101000111 0126 0123 BRANCH CAR10073 001000011 0128 OFF TCY 130068 000110110 0129 RSIK TURNS OFF CALCULATOR0087 010010000 0126 CAR1 FOX 00001 100110110 144 128 BRANCH CARS0010 000101001 0128 CAR2 1280048 001000101 0129 CAR2 ICY 100076 001000011 0140 THTT 3 TEST DEBOUNCE COUNTER0069 101011001 0135 0131 BRANCH CARS ACCEPT KEY IF COUNTER>70058 001100000 0142 TCMIY 0 RESET DEBOUNCE COUNTER0036 010001111 0143 CARS 11 DISP/KR10060 100110010 2245 01440059 011100011 0145 CARS 41FC 13 *TEST TO SEE IF SPEECH IS0042 100010110 0134 0136 BRANCH CARS *FINISHED (TEST TALK COUNTER=14)0081 100011111 0080 0137 BRANCH KEYDOWN 0134 * 0139 * 0140 * 0141 *0049 010010001 0142 GAME#3 RDX H0012 001001110 0143 TCY 70025 000101001 0144 TMA0044 011100110 0145 ALFC 60014 101010010 0148 0146 BRANCH FIRST0029 100100001 0152 0147 BRANCH GM340052 001101110 0148 FIRST TCMTY 70024 010100010 0149 SHTT 10048 010001000 0150 CALL1 CLEAR0010 110111010 0236 01510021 110001010 0152 GM3A CALL1 CURLEVL0042 111101111 0700 01530044 001100000 0154 TCMTY D0049 001100001 0155 TCMTY A *TO 008C: 008C-008D 0156 * *CONTAIN ADDRESS FOR 0157 * *RANDOM LETTER TABLE0013 000000101 0158 CALLL HEMADOR ADDRESS 03500027 111011000 1501 01590048 000001110 0180 CALLL ADDRESS *LOAD DATA FROM 0350 INTO0010 111000010 1121 0151 *RDM ADDRESS LOCATION 0162 *0039 010011100 0163 TDX 30072 001001001 0164 TCY 90065 010100111 0165 RBTT 30048 000101001 0166 TMA0018 010011000 0167 EDX 1 *ADD0029 001001101 0168 TCY 11 *TO0054 111011000 0112 0169 CALL ADDCARRY *ROM ADDRESS0039 010011100 0170 EDX 3 GET LSD OF RANDOM NUMBER0064 001000001 0171 TCY A GET MSD OF RANDOM NUMBER0051 001000001 0172 TMA0022 010011000 0173 TDX 10044 001000101 0174 TCY 100004 111011000 0112 0175 CALL ADDCARRY *ADD TO ROM ADDRESS0011 010000101 0176 CALLL REMADDR LOAD ADDRESS TO 03500023 111011100 1501 01770046 010001110 0178 CALLL DUTADDR2 GET LSD OF RANDOM LETTER0004 111000001 1083 01790039 010010000 0180 CDX 00034 001000111 0181 TCY 140060 000100110 0182 TAM0090 010001110 0183 CALLL DDTADDR2 GET 180 OF RANDOM LETTER0014 111000001 1084 01840035 010010000 0185 LDX 0 *STORE0064 001001111 0186 TCY 15 *LIKE A0055 000101111 0187 TAM *KEYPRESS0024 010010100 0188 LDX 20054 001100000 0189 TCMIY 00028 010001011 0190 BL TRANSFER **SAYS LETTER AND0059 101011111 1875 0191 **PUTS IT IS DISPLAY 0192 *__________________________________________________________________________
TABLE IX-1__________________________________________________________________________ 0195 OHGPG 10000 000101101 0194 NOTFULL IAMIYC0001 001101000 0195 TCMTV 10003 001000111 0196 TCY 140007 000101001 0197 TMA0005 001001101 0198 TCY 110015 000101010 0199 TDY0035 010011000 0200 TDX 10075 000101101 0201 LABIYC0076 001100011 0202 ICOIY 120070 010010000 0203 LDX 00078 001000101 0204 TCY NXTXDSP **0077 000110010 0205 IMAC **0068 000101111 0206 IAM **0056 010000010 0207 ML NHSTMANS **0059 100101100 6880 0208 0209 * 0214 *60 MODTICK.fwdarw. OFFICES WHICH MODE YOUR IN AND BRANCHES 0211 *IN THAT MODE, ELSE GOES TO DISP/KR. 0212 *0071 010001010 0213 GO BL RANDOM0079 100000000 0753 02140073 010010001 0215 HANBTN EDX 8 PAM0067 001000110 0216 TCY 60045 010100110 0217 S8TT 10018 001000001 0218 TCY 8 SET GO MODE FLAG0030 010100010 0219 SHTT 1 *0074 001001110 0220 TCY 7 TEST WHICH MODE0075 000101001 0221 TPA0026 010011010 0222 LDX 50057 001001011 0223 TCY 150026 001100000 0224 TCMIY 00050 010001101 0025 CALLL CORNSSPL0038 110000000 1582 02260070 010000100 0227 10P 20061 011101000 0228 ALEC 1 SPELL?0043 100000000 0342 0229 BRANCH UNSPELL *0000 010000001 0230 LDP 4 *0006 011101100 0231 ALEC 3 LEARN?0010 100110001 1209 0232 BRANCH DLRN+10037 010001101 0233 LDP 110056 011101010 0234 ALPC 5 GAME#10050 101111110 1590 0235 BRANCH CORR+10034 001000000 0236 CLEAR TCY 00074 010010000 0237 HERE LDX 00069 001101000 0238 TCMTV 10053 000000100 0239 DYN0020 010011000 0240 TDV 10040 001101101 0241 TCMIY 110018 001010001 0242 YFRC 80031 101110100 0237 0243 BRANCH HERE0062 001000000 0244 ICY 00085 001100011 0245 ICMIY 120008 010010000 0248 LDX 00015 001001101 0247 ICY 110025 001100000 0208 TCMIV 00056 010111111 0249 hH140029 101110011 0214 0256 REPLAY BRANCH MARRTH 0251 * 0252 *AFTER- MOOIIF TO PROCESS ENTER KEY IMPRESS 0254 *0052 010010001 0254 ENTER FOX M DAM0054 001001110 0255 TCY 7 FLAG0059 000110011 0256 HDF2 SPELL MODE?0041 100000101 0259 0257 BRANCH ISTUAS NO0002 101100011 0273 0258 BRANCH SPACE=30005 000101010 0259 TST4A3 TMY0006 001011100 0260 YDFC 3 SPELL IT MODE?0017 101011110 0265 0261 BRANCH IST4A6 NO0026 101100011 0273 0262 BRANCH SPACE=30056 001010110 0263 TST4A6 YNFC 0 GAME 2 MODE?0036 101100011 0273 0264 BRANCH SPACE=30078 010000110 0265 ML CRYPTO0071 100000000 0894 0266 0267 * 0268 *TEST FOR CURSER POSITION 0269 RETURNRST POSITION? 0270 *ELSE, REPLACE CURSER WITH SPACE 0271 * 0272 *TEST FOR POSITION OF CURSER AND REPLACE WITH SPACE0064 001001110 0273 SPACE=3 TCY 7 LAST CHAN0007 010011000 0274 LDX 10006 000000110 0275 SPACE=2 LLA ACC=H0018 001111101 0276 ACACC 11 1H=SPACE0036 000001001 0277 M&FA MEM=110076 101011001 0283 0278 BRANCH CHAROHa- NO0060 010010000 0279 LDX 6 YES0056 000110011 0286 RNF7 BLANK?0036 100100001 0240 0261 BRANCH SPACE=1 YES, GO TO SPACE=10060 100100100 0293 0282 BRANCH CHAN ELSE, CHAN0058 010011000 0283 CHAROR LDX 10032 001111000 0284 ACACC 1 ACC=12 FOR CURSER0059 000001101 0285 NDFA0094 100100100 0244 0286 BRANCH CHAN CHAR0012 010010000 0877 LDX 0 TEST DSR0025 000110001 0288 CGFZ CURSER0034 100101001 0291 0289 BRANCH CDR=1 YES0014 100100100 0243 0240 BRANCH CHAR NO, THEN CHAR0021 010011000 0291 CDR=1 LDX 1 LSW0052 001101101 0242 TCMTY 110029 010111111 0294 CHAR METM0098 010000100 0294 M1 SPLENTER GO TO SPELL ROUTINE0010 101010111 0373 02950021 000000100 0296 SPACE=1 DYA SEARCH FOR CURSER0042 010011000 0297 LDX 1 *0001 100001110 0275 0298 BRANCH SPACE=2 * 0299 * 0300 * 0301 *NOPHRASE LOADS RUN ADDR WITH SECOND WRONG RESPONSE 0302 *THEN CONTINUES TO NEXT WORD 0303 *0069 010011100 0304 NOPHRASE LDX 3 FLAG0027 001001011 0305 TCY 13 *0046 001101100 0306 TCMIY 30045 010001010 0307 CALL1 CURSER0010 111101111 0769 03080039 001100100 0309 TCMIY 20072 001100110 0310 TCMIY 60065 010000101 0311 SPK4 CALL1 REMADDR0048 111011000 1501 03120016 010001110 0313 CALL1 LOADRESS0020 111000010 1121 03140054 010000101 0315 CALL1 REMADDR0034 111011000 1501 03160066 010000011 0317 ML LNRSFT ALWAYS BRANCH0051 100111000 1751 03180022 010010100 0319 F-SCOWF LDX 2 RETNRCH FLAG0044 001000101 0320 TCY 140000 000000000 0321 TCMIY 10011 001100000 0322 TCMIY 1 *0023 010001110 0323 CALL1 CURIEVL ZEPO ROM ADDR0040 111101111 0769 03240080 010000110 0325 RDM 60019 011101001 0326 ALEC 9 10 CORRECT?????0033 100101111 0255 0327 BRANCH F2 NO,0060 010010000 0328 LDX 00040 001000100 0329 TLY 20014 001100100 0330 TCNIY 20035 010011000 0331 LDX 1 RICE-0063 001001000 0332 ICY 10055 001101000 0333 ICALY 10021 001100000 0334 TCALY 00054 010010100 0335 LDX 20024 001000111 0336 ICY 140050 000110010 0337 IMAC0029 010001101 0338 BL 10NE220044 101100011 1656 0339__________________________________________________________________________
TABLE IX-2__________________________________________________________________________ 0340 DMCPG 2 0341 *0000 010110010 0342 USPELL COMX8 ADDRESS DAM0001 001000010 0343 TCY 40006 001100000 0344 TCMIY 00007 010001000 0345 USPELL+ 1 CALLL CLEAR * BLANK DISPLAY - INPUT CURSER0008 110111010 0236 0346 0347 * LOAD PHRASE INTO ROM ADDRESS REG0016 010001010 0348 DISSPELL CALLL CURLEVL0038 111101111 0769 03490076 001100010 0350 TCMIY 40076 001100110 0351 TCMIY 60078 010110010 0352 ADDCTR COMXA ADDRESS DAM0074 001000010 0353 TCY 4 PHRASE COUNTER.fwdarw.ACC0077 000101001 0354 TMA *0066 010011000 0355 LDX 10056 001000101 0356 TCY 100036 010111111 0357 RETN0070 010000000 0358 CALLL ADDCARRY0079 111011000 0112 0359 0360 * SET UP WORD ADDRESS IN LNK/EDT0073 010010100 0361 LDX 20067 001001111 0362 TCY 150046 001101001 0363 TCMIY 90016 010000101 0364 CALLL MEMADDR0039 111011000 1501 03650074 010001110 0366 CALLL LOADRESS0075 111000000 1121 03670063 101011011 0123 0368 BRANCH NBIT3 0369 * 0370 * SPLENTER- BEGINS BY COMPARING CORRECT SPELLING BUFFER 0371 * TO DISPLAY BUFFER 0372 *0057 001000000 0373 SPLENTER TCY 0 FIRST LETTER--LSW0026 010011100 0374 SPLNTR+1 LDX 3 *0050 000101001 0375 TDM0038 010011000 0376 LDX 1 DISPLAY BUFFER0070 000001001 0377 MNBA SAME?0061 101101100 0425 0378 BRANCH N1SS10045 010010100 0379 LDX 2 YES, TEST MSW0005 000000110 0380 CLA0000 000100000 0381 TBIT 00018 101101110 0384 0382 BRANCH CONXT10037 101011101 0385 0383 BRANCH CONXT20066 001111000 0384 CONXT1 ACACC 10050 010010000 0385 CONXT2 LDX 00034 000000001 0386 NBEA SAME?0074 101101100 0425 0387 BRANCH N1SS10069 000000110 0388 CLA0058 110111111 0389 RETN0026 000000101 0390 IVC NEXT LETTER0040 001110001 0391 YNEC 80018 100101110 0374 0392 BRANCH SPLNTR+1 NO 0393 * SPELLING IS CORRECT0081 010110010 0394 COMX8 ADDRESS DAM0062 001000110 0395 TCY 6 FLAG0045 000100000 0396 TBIT 0 BIT 0.fwdarw.0-FIRST TRY0004 100101011 0400 0397 BRANCH NMII * 1.fwdarw.MORE IN ONE0015 010100000 0398 SBIT 0 0399 * BEGIN LOADING PRAISE PHRASE0028 010011100 0400 TBIT LDX 30054 001001011 0401 TCY 13 FLAG0020 001101000 0402 TCMIY 10064 010110010 0403 COMX80030 001001000 0404 TCY 10060 001100000 0405 TCMIY 00041 010010100 0406 LDX 20002 001001111 0407 TCY 150005 001101100 0408 TCMIY 30008 110001000 0409 CALLL CURLEVL0017 111101111 0769 04100028 001100001 0411 TCMIY 80056 001100010 0412 TCMIY 50030 111111101 0352 0413 CALL ADDCIR0078 011100110 0414 ALEC 60071 101110110 0121 0415 BRANCH TBIT20064 010110010 0416 COMX80097 001000010 0417 TCY 40008 001100000 0418 TCMIY 00010 000000010 0419 CLA0038 010000010 0420 COMX80076 010000000 0421 TBIT2 LDP 00068 111011000 0118 0422 CALL ADDCARRY0090 010000010 0423 TBIT3 BL ADDCIR60086 101011001 0700 04240060 000000110 0425 M1SS1 CLA0059 001110011 0426 ACACC 120032 010010000 0427 LDX 00064 010111111 0428 RETN0049 010000101 0429 BL MISSPELL0012 100111001 1546 04300025 010001000 0431 F3 CALLL CLEAR CLEAR DISPLAY004A 110111010 0236 04320014 010010001 0433 LDX 80029 001000001 0434 TCY 80052 010100001 0435 SBIT 20024 010100110 0436 RBIT 10048 001001000 0437 TCY 10010 010010000 0438 LDX 00021 001100100 0439 TCMIY 20042 001001110 0440 TCY 70004 001100100 0441 TCMIY 20009 010011000 0442 LDX 10013 001000000 0443 TCY 00027 001101011 0444 TCMIY 130048 001000110 0445 TCY 60010 001100111 0446 TCMIY 140039 010011010 0447 LDX 50072 001001011 0448 TCY 130065 000101001 0449 TMA0048 010011000 0450 LDX 10016 001001110 0451 TCY 7002D 000101111 0452 TAM005A 010001110 0453 CALLL FL20034 110001100 1145 04540068 010011000 0455 LDX 10051 001001000 0456 TCY 10022 000101111 0457 TAM0044 010001000 0458 BL F-SCORE0008 100100010 0319 0459 0460 * LEARN MODE BEGINS HERE 0461 *0011 010010001 0462 SPELL LDX 80023 001001110 0463 TCY 70046 001100000 0464 TCMIY 0000C 101001101 0469 0465 BRANCH SPELL90019 010010001 0466 LEARN LDX 80033 001001110 0467 TCY 70066 001100100 0468 TCMIY 20040 010001111 0469 SPELL9 BL DSP7001A 101110000 2188 04700035 001111100 0471 MISS3 ACACC 3006A 000101111 0472 TAM0055 010000010 0473 LDP 4002A 011100110 0474 ALEC 60054 100101100 0680 0475 BRANCH NOSTRANS0028 010001100 0476 BL TWIN0050 100101100 0541 0477__________________________________________________________________________
TABLE IX-3__________________________________________________________________________ 0478 ORGPG 30000 010010100 0479 GAME#1 LDX 20001 000000110 0480 CLA0003 001001011 0481 TCY 130007 000101111 0482 TAM CLEAR GUESS COUNTER000F 010011100 0483 LDX 3001F 001100111 0484 TCMIY 14 HANGMAN FLAG003F 001000101 0485 TCY 10007F 000100000 0486 TBIT 0 * TEST RANDOM COUNTER007E 101111011 0489 0487 BRANCH HANG2 * BIT AND PUT 2 OR 3007D 001111000 0488 ACACC 1 * IN ACC007B 001110100 0489 HANG2 ACACC 2 *0077 010011000 0490 LDX 1006F 001001111 0491 TCY 15 * STORE 2 OR 3 IN LEVEL005F 000101111 0492 TAM * OF DIFFICULTY003B 010010001 0493 LDX 8 DAM007C 001001110 0494 TCY 70079 001101010 0495 TCMIY 5 SET HANGMAN MODE0073 010001010 0496 BL CURLEVL0067 101101111 0769 0497 0498 * `RANDOM` GENERATES A RANDOM WORD, 0499 * PUTS IT IN THE CORRECT SPELLING 0500 * BUFFER AND RETURNS TO `HANG`004F 010001000 0501 HANG CALLL CLEAR PUT BLANKS IN DISPLAY001E 110111010 0236 0502003D 001000001 0503 TCY 8007A 000000100 0504 HANG3 DYN0075 010000100 0505 CALLL SPLNTR+1 * COMPARE DISPLAY DIGIT TO006B 110101110 0374 05060057 011100000 0507 ALEC 0 * DIGIT IN CORRECT002E 101111010 0504 0508 BRANCH HANG3 * SPELLING BUFFER 0509 * FINDS THE FIRST DIGIT THAT IS NOT A 0510 * BLANK, STARTING FROM THE RIGHT SIDE; 0511 * THE ROUTINE BELOW THEN PUTS CURSORS IN 0512 * THE DIGITS CORRESPONDING TO LETTERS005C 010011000 0513 LDX 10038 000101100 0514 HANG4 TAMDYN0070 100111000 0514 0515 BRANCH HANG40061 010001101 0516 SONG BL TONES0043 101000111 1657 0517 0518 * IF THE HANGMAN FLAGS ARE SET UP, LETTER 0519 * KEYS GO TO `HANG1` AFTER SPEAKING THE LETTER 0520 ** THIS ROUTINE COMPARES LETTER ENTERED TO CORRECT SPELLING0006 001001011 0521 HANG1 TCY 130000 010010000 0522 LDX 0 * BIT 1= WORD NOT COMPLETE0018 001100000 0523 TCMIY 0 * BIT 0=CORRECT LETTER0037 001000001 0524 TCY 8006E 010100011 0525 HANG5 SBIT 3 BIT IS SET AFTER EACH DIGIT IS COMPARED005D 000000100 0526 DYN003A 101011011 0562 0527 BRANCH HANG60074 001000001 0528 TCY 8 COMPARISONS ARE COMPLETE0069 010100111 0529 HANG10 RBIT 3 RESET BIT 3 IN EACH DIGIT0053 000000100 0530 DYN0026 101101001 0529 0531 BRANCH HANG10004C 001001011 0532 TCY 130018 000100000 0533 IBIT 0 WAS THE LETTER CORRECT?0031 101100011 0555 0534 BRANCH HANG110062 010010100 0535 LDX 2 NO0045 000110010 0536 IMAC * ADD 1 TO INCORRECT000A 000101111 0537 IAM * GUESS COUNTER0015 010001111 0538 LDP 150028 011100110 0539 ALEC 60056 100101100 2219 0540 BRANCH DISP/RB002C 010011000 0541 IWIN LDX 10058 001000101 0542 TCY 100030 001100000 0543 TCMIY 00060 001101110 0544 TCMIY 70041 001100000 0545 IWIN1 TCMIY 00002 001100000 0546 TCMIY 00005 001001111 0547 TCY 150008 010010100 0548 LDX 20017 001100000 0549 TCMIY 0002F 010010001 0550 LDX 8 CLEAR HANGMAN005E 001000001 0551 TCY 8003C 010100110 0552 RBIT 10078 010000101 0553 BL LOADDISP0071 101111001 1456 05540063 000100010 0555 HANG11 TBIT 10047 101100001 0516 0556 BRANCH SONG000E 001000101 0557 YOUWIN TCY 10 YES001D 010011000 0558 LDX 1003A 001100100 0559 TCMIY 20076 001101110 0560 TCMIY 7 * `YOU WIN`006D 101000001 0545 0561 BRANCH IWIN1005B 010000100 0562 HANG6 CALLL SPLNTR+1 *CHECK IF CORRECT0036 110101110 0374 0563006C 011100000 0564 ALEC 0 *LETTER HAS ALREADY0059 101101110 0525 0565 BRANCH HANG5 *BEEN ENTERED IN EACH DIGIT0032 001001111 0566 TCY 15 NO0064 000101001 0567 FINDIT TMA PUT LETTER CODE IN ACC0049 001000001 0568 TCY 8 * FIND THE FIRST LETTER0012 000000100 0569 HANG7 DYN * THAT HASN'T YET0025 000100011 0570 TBIT 3 * BEEN ENTERED004A 100010010 0569 0571 BRANCH HANG7 * CORRECTLY0014 010111111 0572 REIN *0029 000101111 0573 TAM STORE LETTER CODE0052 001000111 0574 TCY 14 *GET OTHER HALF OF0024 010001100 0575 CALLL FINDIT *LETTER CODE AND STORE IT0048 111100100 0567 05760010 010011000 0577 LDX 1 *0021 000101111 0578 TAM *0042 010000100 0579 CALLL SPLNTR+1 CHECK TO SEE IF0004 110101110 0374 05800009 011100000 0581 ALEC 0 NEW LETTER MATCHES0013 100101101 0591 0582 BRANCH HANG80027 010011000 0583 LDX 1 * DOES NOT MATCH004E 000101011 0584 TYA * PUT BLANK BACK001C 001100011 0585 TCMIY 12 * IN DISPLAY0039 010010000 0586 LDX 00072 001001011 0587 TCY 130065 010100010 0588 SBIT 1 SET FLAG FOR WORD NOT COMPLETE004B 000101000 0589 TAY0016 100110100 0593 0590 BRANCH HANG9 BET002D 000101011 0591 HANG8 TYA CORRECT LETTER GUESS005A 001001011 0592 TCY 13 *0034 010100000 0593 HANG9 SBIT 0 * CORRECT LETTER FLAG IF Y=130068 000101000 0594 TAY0051 101101110 0525 0595 BRANCH HANG5 0596 * 0597 * NXTWORD--RESETS FLAGS, INCREMENTS COUNTERS AND POINTERS 0598 *0022 010110010 0599 NXTWORD COMX8 *0044 001000010 0600 TCY 4 INCREMENT PHRASE COUNTER0008 000101001 0601 TMA0011 001110100 0602 ACACC 20023 011100001 0603 ALEC 80046 100011001 0606 0604 BRANCH NXT2000C 000000110 0605 CLA0019 000101111 0606 NXT2 TAM0033 001000110 0607 TCY 6 RESET BITS FLAG60066 010100100 0608 RBIT 0004D 010100110 0609 RBIT 1001A 001000000 0610 TCY 0 INCREMENT RWE POINTER0035 000110010 0611 IMAC *006A 000101111 0612 TAM *0055 000101010 0613 TMY *002A 010000100 0614 LDP 20054 001010101 0615 YNEC 10 *0028 100000111 0345 0616 BRANCH DSPELL+10050 010000100 0617 BL F30020 100100101 0431 0618__________________________________________________________________________
TABLE IX-4__________________________________________________________________________ 0619 ORGPG 40000 010001000 0620 GAME#2 CALLL CLEAR PUTS BLANKS AND CURSOR IN DISPLAY0001 110111010 0234 06210003 010010001 0622 LDX 8 DAM0007 001001110 0623 TCY 7000F 001100110 0624 TCMIY 6 SET MODE FOR CODE BREAKER001F 010100010 0625 SBIT 1 SET GO FLAG003F 010001101 0626 BL TONES007F 101000111 1657 0627 0628 *007E 010010001 0629 DIFFSLV LDX 8007D 001001110 0630 TCY SEVEN **007B 000101001 0631 TMA0077 010010000 0632 LDX 0006F 001000000 0633 TCY 0005F 001101000 0634 BLANKM TCMIY 1003E 001010001 0635 YNEC 8007C 101011111 0634 0636 BRANCH BLANKM0079 001001000 0637 TCY 10073 011100000 0638 ALEC 00067 101000011 0656 0639 BRANCH LZEROS 0640 *004F 001100000 0641 TCMIY 0 A001E 001000010 0642 TCY 4003D 001100000 0643 TCMIY 0 I 0644 *007A 010011000 0645 LDX ONE **0075 001000000 0646 TCY DISPLAY **0068 001100100 0647 TCMIY 2 S0057 001100000 0648 TCMIY 0 A002E 001100001 0649 TCMIY 8 Y005C 001101101 0650 TCMIY 110038 001100001 0651 TCMIY 8 I0070 001101100 0652 TCMIY 3 T0061 101110100 0665 0653 BRANCH BLANK 0654 * 0655 *0043 001100000 0656 LZEROS TCMIY 0 PUT ,SPELL, IN DISPLAY0006 001011010 0657 YNEC 5000D 101000011 0656 0658 BRANCH LZEROS 0659 *001B 010011000 0660 LDX ONE **0037 001000000 0661 TCY DISPLAY **006E 001100100 0662 TCMIY LSW$S **005D 001101111 0663 TCMIY LSW$P **003A 001100010 0664 TCMIY LSW$E **0074 001101101 0665 BLANK TCMIY 110069 001010001 0666 YNEC 80053 101110100 0665 0667 BRANCH BLANK0026 001001111 0668 PUT$LVL TCY LEVEL * PUT LEVEL IN DISPLAY004C 000101001 0669 TMA **0018 001001110 0670 TCY 70031 000101111 0671 TAM ** 0672 *0062 010010000 0673 LDX ZERO **0045 001100000 0674 TCMIY 0 0675 *000A 010110010 0676 COMX8 * CLEAR GO FLAG0015 001000001 0677 TCY FLAG2 **0028 001100000 0678 TCMIY 00056 010111111 0679 RETN **002C 010010000 0680 NO$TRANS LDX 0 CALCULATE LETTER ADDRESS0058 001001111 0681 TCY 150030 000101001 0682 TMA0060 010011000 0683 LDX 10041 001000011 0684 TCY 120002 001100000 0685 TCMIY 00005 001100000 0686 TCMIY 00008 001001101 0687 TCY 110017 000101111 0688 TAM002F 010000000 0689 CALLL ADDCARRY005F 111011000 0112 0690003C 010010000 0691 LDX 00078 001000111 0692 TCY 140071 000101001 0693 TMA0063 010011000 0694 LDX 10047 001000101 0695 TCY 10000E 000101111 0696 TAM001D 010000000 0697 CALLL ADDCARRY003B 111011000 0112 06980076 000000110 0699 CLA006D 001110011 0700 ACACC 120058 001000101 0701 TCY 100036 010000000 0702 CALLL ADDCARRY006C 111011000 0112 07030059 010000101 0704 ADDCTR6 CALLL MEMADDW0032 111011000 1501 07050064 010001110 0706 CALLL LOADRESS0049 111000010 1121 07070012 010000111 0708 BL ADDWDS20025 100001010 2057 0709004A 010010100 0710 RETNSBCH LDX 2 RETNSBCH FLAG-ACC0014 001001111 0711 TCY 15 *0029 000101001 0712 TMA0052 010001111 0713 LDP 150024 011101000 0714 ALEC 1 SPELL?0048 100101100 2219 0715 BRANCH DISP/KB0010 010001101 0716 LDP 110021 011100100 0717 ALEC 20042 101000010 1680 0718 BRANCH NXTTONE0004 010001100 0719 LDP 30009 011101100 0720 ALEC 3 NXTWORD?0013 100100010 0599 0721 BRANCH NXTWORD0027 010000101 0722 LDP 10004E 011100010 0723 ALEC 4 NEG?001C 100001001 1540 0724 BRANCH MSPEL30039 010000001 0725 LDP 80072 011101010 0726 ALEC 5 SAY IT?0065 101100011 1232 0727 BRANCH DISLP-50048 010001001 0728 LDP 90016 011100110 0729 ALEC 6 SPEAK LETTER?002D 101110110 1372 0730 BRANCH LET+4005A 010001100 0731 LDP 30034 011101110 0732 ALEC 70068 100000110 0521 0733 BRANCH HANG10051 011100001 0734 ALEC 80022 100000000 0479 0735 BRANCH GAME#10044 010000101 0736 LDP 100008 011101001 0737 ALEC 90011 101101010 1570 0738 BRANCH ADDCTR20023 010000001 0739 LDP 80046 011100101 0740 ALEC 10000C 101100011 1232 0741 BRANCH DISPL-5 0742 * TSTBIT2-->USED IN LOADING LNK/EDT TO TEST FOR 3 WORDS OF ZERO 0743 * 1 WORD OF 0001 0744 *0019 010110010 0745 TSTBIT2 COMXM DAM REG0033 001000100 0746 TCY 20066 010100110 0747 RBIT 1004D 010100101 0748 RBIT 2001A 010110010 0749 COMX80035 010111111 0750 RETN__________________________________________________________________________
TABLE IX-5__________________________________________________________________________ 0751 ORGPG 5 ** 0752 * STORE SEED NUMBER0000 010010010 0753 RANDOM LDX 40001 001000101 0754 TCY 100003 000000110 0755 CLA0007 010001111 0756 CALLL FILSLOOP000F 110101110 2183 0757001F 001001110 0758 TCY 7003F 010010001 0759 LDX 8007F 010001110 0760 LDP 7007E 000100000 0761 TBIT 0007D 101110011 1039 0762 BRANCH LDPREV007B 010100000 0763 SBIT 00077 010001010 0764 LDP 5 0765 * CURLEVL.fwdarw. 0766 * STORES NUMBER OF ENTRIES IN CURRENT LEVEL 0767 * INTO RAM 0768 *006F 001000101 0769 CURLEVL TCY 10005F 010011000 0770 LDX 1 0771 * ZERO OUT ROM ADDR003E 001100000 0772 TCMIY 0007C 001100000 0773 TCMIY 00079 001100000 0774 TCMIY 00073 001100000 0775 TCMIY 00067 001000101 0776 TCY 10004F 010111111 0777 RETN 0778 * FIND DIFFICULTY LEVEL001E 001001111 0779 TCY 15003D 000101001 0780 TMA007A 001000101 0781 TCY 100075 000101111 0782 TAM0068 010000111 0783 CALLL ADD80057 110001100 2139 0784002E 010000101 0785 CALLL MEMADDR005C 111011000 1501 0786 0787 * OUTPUT # OF ENTRIES IN THIS LEVEL0038 010001110 0788 CALLL OUTADDR20070 111000001 1083 07890061 001001111 0790 TCY 150043 010011010 0791 LDX 50006 000101111 0792 TAM000D 010001110 0793 CALLL OUTADDR20018 111000001 1083 07940037 001001111 0795 TCY 15006E 010010010 0796 LDR 4005D 000101111 0797 TAM003A 010011010 0798 LDX 50074 000000111 0799 DMAN0069 100011000 0804 0800 BRANCH DECMEM0053 000101111 0801 TAM0026 010010010 0802 LDX 4004C 000000111 0803 DMAN0018 000101111 0804 DECMEM TAM0031 010011100 0805 LDX 30062 001000001 0806 TCY 80045 000101001 0807 TMA000A 010011010 0808 LDX 50015 001000000 0809 TCY 00028 000101111 0810 TAM0056 010011100 0811 LDX 3002C 001001001 0812 TCY 90058 000101001 0813 TMA0030 010010010 0814 LDX 40060 001000000 0815 TCY 00041 000101111 0816 TAM 0817 * DETERMINE IF SEED IS '>' NUMBER OF ENTRIES0002 001001111 0818 DECLOOP TCY 150005 000000001 0819 ALEM0008 101111000 0825 0820 BRANCH RANOK0017 001000000 0821 TCY 0002F 001111100 0822 ACACC 3005E 000101111 0823 TAM003C 100000010 0818 0824 BRANCH DECLOOP0078 000001001 0825 RANOK MNEA0071 101011001 0837 0826 BRANCH RANOK20063 001000000 0827 TCY 00047 010011010 0828 LDX 5000E 000101001 0829 TMA001D 001001111 0830 DECLOOP3 TCY 15003B 000000001 0831 ALEM0076 101011001 0837 0832 BRANCH RANOK20060 001000000 0833 TCY 00058 001111100 0834 ACACC 30036 000101111 0835 TAM006C 100011101 0830 0836 BRANCH DECLOOP30059 010110010 0837 RANOK2 COMX8 0838 * ZERO RWE POINTER0032 001000000 0839 TCY 00064 001100000 0840 TCMIY 00049 010011010 0841 RPLOOP LDX 50012 010001101 0842 CALLL RCOMX80025 111001100 1631 0843004A 000101001 0844 TMA0014 000000101 0845 IYC0029 001111000 0846 ACACC 10052 110101000 0888 0847 CALL INCARRY0024 000101100 0848 TAMDYN0048 010010010 0849 LDX 40010 000101001 0850 TMA0021 000000101 0851 IYC0042 000010101 0852 AMAAC0004 000101111 0853 TAM0009 010001101 0854 RANARND CALLL RCOMX80013 111001100 1631 08550027 000101001 0856 TMA004E 001001111 0857 TCY 15001C 000000001 0858 ALEM0039 101100101 0861 0859 BRANCH RANCNT0072 101000100 0870 0860 BRANCH ZRORAND0065 000001001 0861 RANCNT MNEA0048 101100110 0878 0862 BRANCH RANCOMP0016 010011010 0863 LDX 5002D 010001101 0864 CALLL RCOMX8005A 111001100 1631 08650034 000101001 0866 TMA0068 001001111 0867 TCY 150051 000000001 0868 ALEM0022 101100110 0878 0869 BRANCH RANCOMP0044 010001101 0870 ZRORAND CALLL RCOMX80008 111001100 1631 08710011 001100000 0872 TCMIY 00023 000000100 1873 DYN0046 010010010 0874 LDX 4000C 001100000 0875 TCMIY 00019 001100000 0876 TCMIY 00033 101001001 0841 0877 BRANCH RPLOOP0066 001000000 0878 RANCOMP TCY 0 0879 * COMPARE RANDOM # TO # OF ENTRIES004D 010110010 0880 COMX80014 000110010 0881 IMAC0035 000101111 0882 TAM006A 011101001 0883 ALEC 90055 101001001 0841 0084 BRANCH RPLOOP002A 010001110 0885 BL RANSTOP0054 100000000 1021 0886 0887 *0028 000101111 0888 INCARRY TAM0050 010010010 0889 LDX 40020 000110010 0890 IMAC0040 010111111 0891 RETN__________________________________________________________________________
TABLE IX-6__________________________________________________________________________ 0892 ORGPG 6 ** 0893 **** CODE BREAKER ******0000 010001000 0894 CRYPTO CALLL SPACE-3 ELIMINATE CURSOR FROM DISPLAY0001 111100011 0273 08950003 001000000 0896 TCY 00007 010010000 0897 CRY1 LDX 0000F 000110011 0898 MNEZ TEST MSB OF DISPLAY CHARACTER001F 100111101 0915 0899 BRANCH CRY2 BRANCH IF MSR=1003F 010011000 0900 COMPL LDX 1007F 000110010 0901 IMAC * COMPLEMENT THE LSD OF007E 000110001 0902 CPAIZ * THE DISPLAYED LETTER007D 010111111 0903 REIN007B 011101001 0904 ALEC 9 * IF A CHARACTER CODE0077 100111110 0908 0905 BRANCH CRY3 * PAST 'Z' HAS BEEN006F 001110110 0906 ACACC 6 * CREATED, ADD 6 TO GET A LETTER005F 101010111 0919 0907 BRANCH CRY6 RET003E 000101111 0908 CRY3 TAM STORE COMPLEMENT OF LSD007C 010010000 0909 CRY5 LDX 00079 001101000 0910 TCMIY 1 SET MSB TO 10073 001010001 0911 CRY4 YNEC 8 ARE ALL LETTERS FINISHED?0067 100000111 0897 0912 BRANCH CRY1 NO, CONTINUE004F 010001101 0913 CRY12 BL TONES001E 101000111 1657 09140030 010000110 0915 CRY2 CALLL COMPL007A 110111111 0900 09160075 011101010 0917 ALEC 5 * TEST FOR CODES OTHER006B 101111100 0909 0918 BRANCH CRY5 * THAN LETTERS AND SKIP THEM0057 000101111 0919 CRY6 TAM002E 010010000 0920 LDX 0005C 001100000 0921 TCMIY 0 SET MSB TO ZERO0038 101110011 0911 0922 BRANCH CRY4 BET0070 010011100 0923 CLUE LDX 30061 001000001 0924 TCY 80043 000101001 0925 TMA GET HEX RANDOM NUMBER0006 011101110 0926 ALEC 7 * IF NUMBER IS GREATER0000 100110111 0929 0927 BRANCH CLUE1 * THAN 7, ADD 80018 001110001 0928 ACACC 8 *0037 000101000 0929 CLUE1 TAY SET Y RANDOMLY 0- 7006E 000000100 0930 CLUE2 DYN * LOOK FOR FIRST005D 101110100 0933 0931 BRANCH YOK003A 001001110 0932 TCY 70074 010000100 0933 YOK CALLL SPLNTR+1 * LETTER THAT HASN'T0069 110101110 0374 09340053 011100000 0935 ALEC 0 * BEEN CORRECTLY ENTERED0026 101101110 0930 0936 BRANCH CLUE2004C 010010100 0937 LDX 20018 000100000 0938 TBIT 0 MSB IS A ONE?0031 100000101 0952 0939 BRANCH CLUE3 YES0062 010011100 0940 GFTIT LDX 3 NO0045 000101001 0941 TMA * GET LSD OF LETTER000A 010010000 0942 LDX 0 * FROM CORRECT SPELLING0015 001000111 0943 TCY 14 * BUFFER AND PUT IT IN0028 000101101 0944 TAMIYC * KEY CODE0056 010111111 0945 RETN002C 001100000 0946 TCMIY 0 SET MSB=00058 001001011 0947 CLUE4 TCY 130030 010010100 0948 LDX 20060 000101001 0949 TMA0001 010000100 0950 ML MISS30002 100110101 0471 09510005 111100010 0940 0952 CLUE3 CALL GETIT0008 001101000 0953 TCMIY 1 SET MSB=10017 101011000 0947 0954 BRANCH CLUE4 SET002F 000101000 0955 F2 TAY005E 001010000 0956 YNEC 0003C 101001111 0913 0957 BRANCH CRY120078 010010000 0958 LDX 0 100071 001001010 0959 TCY 50063 001101000 0960 TCMIY 10047 001100100 0961 TCMIY 2000E 001100100 0962 TCMIY 20010 010011000 0963 LDX 10038 001001010 0964 TCY 50076 001100111 0965 TCMIY 140060 001101000 0966 TCMIY 10058 001100000 0967 TCMIY 00036 101001111 0913 0968 BRANCH CRY12006C 010011100 0969 F5 LDX 30059 001001011 0970 TCY 13 LNK/EDT VALUE0032 001100000 0971 TCMIY 00064 010011000 0972 F2LOOP LDX 10049 001000101 0973 TCY 100012 001100100 0974 TCMIY 20025 001100010 0975 TCMIY 4004A 001100000 0976 TCMIY 00014 001100000 0977 TCMIY 00029 010011010 0978 LDX 50052 001001011 0979 TCY 13 # OF CORRECT SCORES0024 000101001 0980 TMA0048 000010101 0981 AMAAC CORRY?0010 101001101 1012 0982 BRANCH NOF20021 010011000 0983 LDX 10042 001000101 0984 TCY 100004 000010101 0985 AMAAC0009 101101010 1015 0986 BRANCH NOF30013 000101111 0987 TAM0027 010111111 0988 FINL2 RETN004E 010000101 0989 CALL MEMADDR001C 111011000 1501 09900039 010001110 0991 CALLL LOADRESS LOAD ADDRESS0072 111000010 1121 09920065 010011000 0993 LDX 1004B 010000011 0994 CALLL TRANS-1 STORE N DAM0016 110100011 1836 09950020 010001001 0996 BL F4005A 101001101 1422 09970034 001000101 0998 FINL3 TCY 100068 010011000 0999 FINL6 LDX 10051 000101001 1000 TMA0022 010010010 1001 LDX 40044 000101101 1002 TAMIYC0008 001010111 1003 YNEC 140011 101101000 0999 1004 BRANCH FINL60023 010001010 1005 CALLL CURLEVL0046 111101111 0769 1006000C 001100010 1007 TCMIY 40019 001101110 1008 TCMIY 70033 010001000 1009 BL SPR40066 101100101 0311 1010 1011 *0040 010011000 1012 NOF2 LDX 10014 001000101 1013 TCY 100035 000010101 1014 AMAAC006A 000101101 1015 NOF3 TAMIYC0055 000110010 1016 IMAC002A 000101111 1017 TAM0054 100100111 0988 BRANCH FINL2__________________________________________________________________________
TABLE IX-7__________________________________________________________________________ 1019 ORGPG 7 ** 1020 * LOADED 10 VALUES -STORE LAST VALUE0000 001100000 1021 RANSTOP TCMIY 00001 001000101 1022 TCY 100003 010011010 1023 LDX 50007 000101001 1024 TMA000F 001000111 1025 TCY 14001F 000101111 1026 TAM003F 010010010 1027 LDX 4007F 001000101 1028 TCY 10007E 000101001 1029 TMA0070 001000111 1030 TCY 140078 000101111 1031 TAM0077 010011010 1032 RSCRAM2 LDX 5006F 111110000 1052 1033 CALL RSCRAM005F 010010010 1034 LDX 4003E 111110000 1052 1035 CALL RSCRAM007C 010001000 1036 BL RANRTN0079 101110011 0215 1037 1038 * LDPREV.fwdarw. LOADS NEXT VALUE NTO RWE0076 001000111 1039 LDPREV TCY 140067 010010010 1040 LDX 4004F 000101001 1041 TMA001E 001000000 1042 TCY 0003D 000101111 1043 TAM007A 001000111 1044 TCY 140075 010011010 1045 LDX 5006R 000101001 1046 TMA0057 001000000 1047 TCY 0002E 000101111 1048 TAM005C 010001010 1049 LDP 50038 101011001 0837 1050 BRANCH RANOK2 1051 * SCRAMBLES RWE WORDS0070 001000000 1052 RSCRAM TCY 00061 000101001 1053 TMA0043 001000110 1054 TCY 60006 000000011 1055 XMA000D 001000000 1056 TCY 00018 000101101 1057 TAMIYC0037 000101001 1058 TMA006E 001001110 1059 TCY 70050 000000011 1060 XMA003A 001001000 1061 TCY 10074 000101101 1062 TAMIYC0069 000101001 1063 TMA0053 001001010 1064 TCY 50026 000000011 1065 XMA004C 001000100 1066 TCY 20018 000101101 1067 TAMIYC0031 000101001 1068 TMA0062 001000001 1069 TCY 80045 000000011 1070 XMA000A 001001100 1071 TCY 30015 000101101 1072 TAMIYC002B 000101001 1073 TMA0056 001001001 1074 TCY 9002C 000000011 1075 XMA005A 001000010 1076 TCY 40030 000000011 1077 XMA0060 010111111 1078 RETN 1079 * 1080 * OUTADDR2: 1081 * LOADS 4 BITS INTO K-LINES USING PDC AND OUTPUT 4 BITS 1082 *0041 001000011 1083 OUTADDR2 TCY 12 ** CHIP SELECT0002 000001101 1084 SETR **0005 001001101 1085 TCY 11 L/R = 0000B 000001101 1086 SETR0017 001000101 1087 TCY 10002F 000000110 1088 CLA ACC=OUTPUT 4 BITS COMMAND005E 001110001 1089 ACACC EIGHT **003C 000001101 1090 SETR **0076 000110110 1091 RSTR **0071 000001101 1092 SETR **0063 000110110 1093 RSTR **0047 000001101 1094 SETR **000E 000110110 1095 RSTR **001D 000001101 1096 SETR **0038 000110110 1097 RSTR **0076 000000110 1098 CLA **006D 001110010 1099 ACACC FOUR **0058 000001101 1100 SETR 1ST PDC LOADS COMMAND0036 000110110 1101 RSTR *006C 001001101 1102 TCY 110059 000110110 1103 RSTR0032 001000101 1104 TCY 100064 000001101 1105 SETR 2ND PDC APPLIES SR TO K-LINES0049 000110110 1106 RSTR *0012 001110000 1107 ACACC 00025 000001000 1108 TKA LOAD INTO ACC004A 000001101 1109 SETR 3RD PDC DISCONNECTS SR0014 000110110 1110 RSTR *0029 001001101 1111 TCY 110052 000001101 1112 SETR0024 010010100 1113 LDX 20048 000100011 1114 TBIT 30010 101001011 1131 1115 BRANCH LSHIFT-10021 010111111 1116 RETN 1117 * 1118 * END OF OUTADDR2 SUBROUTINE 1119 * 1120 *0042 001001101 1121 LOADRESS TCY 110004 010010100 1122 LDX 20009 010100011 1123 SBIT 3 *0013 001000101 1124 TCY 100027 000000110 1125 CLA004E 001111100 1126 ACACC 3001C 010010100 1127 LDX 2 MEMORY FOR LOOP0039 000101110 1128 LOADR+1 TAMZA0072 010011000 1129 LDX 10065 101000001 1083 1130 BRANCH OUTADDR20048 001001011 1131 LSHIFT-1 TCY 130016 010011000 1132 LDX 1002D 000000011 1133 LSHIFT XMA SHIFT ROUTINE005A 000000100 1134 DYN *0034 001011001 1135 YNEC 9 *0068 100101101 1133 1136 BRANCH LSHIFT *0051 001000101 1137 TCY 10 TEST LOOP COUNT0022 010010100 1138 LDX 2 *0044 000000111 1139 DMAN *0008 100111001 1128 1140 BRANCH LOADR+1 *0011 001001101 1141 TCY 110023 010100111 1142 RBIT 30046 010111111 1143 RETN 1144 *000C 010011010 1145 FL2 LDX 50019 001001011 1146 TCY 130033 000000110 1147 CLA0066 001110101 1148 ACACC 100040 000000011 1149 XMA001A 000110000 1150 SAMAN0035 000101111 1151 TAM006A 010111111 1152 RETN0055 001000110 1153 ROM TCY 6002A 010010001 1154 LDX 80054 000101001 1155 TMA0028 001110001 1156 ACACC 80050 000101111 1157 TAM0020 010001111 1158 BL DISP/KB0040 100101100 2219 1159__________________________________________________________________________
TABLE IX-8__________________________________________________________________________ 1160 ORGPG 8 1161 * 1162 * CALADDR--> STICKS ADDRESS WANTED INTO LNK/EDT 1163 *0000 001000111 1164 CALADDR TCY 140001 001100101 1165 TCMIY 100003 001001001 1166 TCY 90007 010011000 1167 LDX 1000F 000101001 1168 TMA001F 001111111 1169 ACACC 15003F 010110010 1170 CDMX8 ADDRESS DAM007F 000101111 1171 TAM007E 001000101 1172 TCY 10007D 000101001 1173 TMAA TMA0078 010011000 1174 LDX 10077 000101101 1175 TAMIYC006F 010110010 1176 COMX8 ADDRESS DAM005F 001010111 1177 YNEC 14003E 101111101 1173 1178 BRANCH TMAA007C 111001111 1183 1179 CALL+2 CALL CAL+10079 010011110 1180 LDX 70073 000101111 1181 TAM STORE WORD0067 010110010 1182 COMX8 ADDRESS DAM004F 001000111 1183 CAL+1 TCY 14 GET Y POINTER001E 000110010 1184 IMAC *003D 000101111 1185 TAM *007A 000101010 1186 TMY *0075 000000100 1187 DYN0068 000101001 1188 TMA0057 001001001 1189 OUT$RTN TCY 9 GET LNK/EDT POINTER002E 000101010 1190 TMY *005C 010110010 1191 COMX8 EXIT DAM0038 010111111 1192 RETN0070 010010110 1193 LDX 6 STORE WORD0061 000101111 1194 TAM *0043 010110010 1195 COMX8 ADDRESS DAM0006 001001001 1196 TCY 9000D 000110010 1197 IMAC0018 000101111 1198 TAM0037 001000111 1199 TCY 14006E 000101010 1200 TMY005D 001010111 1201 YNEC 14 Y-14? IF YES,003A 101111100 1179 1202 BRANCH CALL+2 LOAD 2 MSW0074 001000100 1203 TCY 20069 010100101 1204 RBIT 20053 010011000 1205 LDX 10026 001001001 1206 TCY 9004C 010000011 1207 BL LNKCNT20018 101101100 1798 12080031 010011100 1209 ULRN+1 LDX 30062 001001011 1210 TCY 130045 001101010 1211 TCMIY 5000A 010001101 1212 ULRN+2 BL CORR+10015 101111110 1590 1213 1214 * * CALCULATES ADDRESS 1215 * * LOADS CSB0028 001100000 1216 DISLP-1 TCMIY 00056 010000101 1217 BL LOADDISP002C 101111001 1456 12180058 010000111 1219 DISLP7 CALLL SPEAK+10030 110000001 2010 12200060 010000011 1221 CALLL TRANS-10041 110100011 1836 12220002 010010100 1223 DISLP+2 LDX 20005 001001111 1224 TCY 15 *0008 001101010 1225 TCMIY 50017 010001010 1226 CALLL CURLEVL002F 111101111 0769 1227005E 001100111 1228 TCMIY 14003C 001100110 1229 TCMIY 60078 010000010 1230 BL ADDCTR60071 101011001 0704 12310063 001001111 1232 DISLP-5 TCY 150047 010110010 1233 CUMX8 ADDRESS DAM000E 001101111 1234 TCMIY 15001D 010110010 1235 DISPLOOP COMX8 EXIT DAM0038 001000111 1236 TCY 140076 010011100 1237 LDX 3006D 010100000 1238 SBIT 00058 010001111 1239 BL DISP/KB0036 100101100 2219 1240006C 010110010 1241 DISLP+1 COMX8 ADDRESS DAM0059 001001111 1242 TCY 15 LOOP0032 000000111 1243 DMAN *0064 000101111 1244 TAM *0049 000110011 1245 MNEZ *0012 100011101 1235 1246 BRANCH DISPLOOP * ELSE0025 001000111 1247 TCY 14004A 010011100 1248 LDX 30014 010100100 1249 RBIT 00029 010010001 1250 LDX 80052 010001001 1251 LDP 90024 001000100 1252 TCY 20048 000100011 1253 TBIT 30010 101010011 1341 1254 BRANCH LET40021 000100001 1255 TBIT 20042 101001010 1385 1256 BRANCH RESTO20004 010000001 1257 LDP 80009 010010100 1258 LDX 20013 001001111 1259 TCY 150027 000101001 1260 TMA004E 011101001 1261 ALEC 9001C 101110010 1264 1262 BRANCH DISP80039 101101000 1271 1263 BRANCH DISP50072 001100101 1264 DISP8 TCMIY 100065 010011000 1265 LDX 10048 010110010 1266 COMX8 ADDRESS DAM0016 010000011 1267 DISP9 CALLL TRANS-1002D 110100011 1836 1268005A 010000111 1269 BL ADDWDS20034 100001010 2057 12700068 010001001 1271 DISP5 CALLL DELAY20051 110100111 1398 12720022 010110010 1273 COMX80044 001000000 1274 TCY 0 INCREMENT RWE POINTER0008 000110010 1275 IMAC *0011 000101101 1276 TAMIYC0023 001100000 1277 TCMIY 00046 011101001 1278 ALEC 9000C 101010000 1291 1279 BRANCH DISP60019 001000000 1280 TCY 00033 001100000 1281 TCMIY 00066 001100000 1282 TCMIY 0004D 010011010 1283 LDX 5001A 010001110 1284 CALLL RSCRAM0035 111110000 1052 1285006A 010010010 1286 LDX 40055 010001110 1287 CALLL RSCRAM0024 111110000 1052 12880054 010000100 1289 BL DSPELL+10028 100000111 0345 12900050 010001001 1291 DISP6 CALLL DELAY20020 110100111 1398 12920040 100110001 1209 1293 BRANCH ULRN+1__________________________________________________________________________
TABLE IX-9__________________________________________________________________________ 1294 ORGPG 9 1295 * 1296 * LETTER-->TRANSFERS LETTERS TO BE SPOKEN, FROM THE CSB 1297 * INTO THE LINK/EDIT AND THEN CALCULATES THE ADDRESS FOR L/E. 1298 *0000 001001111 1299 LETTER TCY 150001 000000110 1300 CLA0003 010000111 1301 CALLL RETURN40007 110000100 2113 1302000F 010001000 1303 CALLL CLEAR001F 110111010 0236 1304003F 001001000 1305 TCY 1007F 010110010 1306 COMX8 *007E 001100000 1307 TCMIY 0 *007D 001001111 1308 TCY 150078 001101000 1309 TCMIY 10077 010011100 1310 LETTER+1 LDX 3 LOAD LSW -->ACC006F 001001000 1311 TCY 1 *005F 010001101 1312 CALLL COMX8 *003E 110011000 1632 1313007C 000101001 1314 TMA *0079 010011110 1315 LDX 7 STORE IN LNK/EDT0073 001000000 1316 TCY 0 *0067 000101111 1317 TAM *004F 010010100 1318 LDX 2 MSW001E 001001000 1319 TCY 1 GET Y POINTER003D 010001101 1320 CALLL COMX8 *007A 110011000 1632 13210075 000101001 1322 TMA LOAD MSW0068 010000101 1323 LDP 100057 000100001 1324 TBIT 2 LAST LETTER?002E 111010011 1485 1325 CALL SETBIT2 YES, SETBIT2005C 010001111 1326 LDP 150038 000100011 1327 TBIT 3 SYLLABLE?0070 111010101 2291 1328 CALL SETBIT3 SET SYLLABLE FLAG0061 001000000 1329 TCY 0 *0043 010010110 1330 LDX 6 *0006 000101111 1331 TAM *000D 010100101 1332 RBIT 20018 010100111 1333 RBIT 3 1334 * CALCULATE ADDRESS OF LETTER0037 001000100 1335 TCY 2 FLAG WORD006E 010010001 1336 LDX 8005D 010000001 1337 LDP 8003A 000100011 1338 TBIT 3 SYLLABLE?0074 100011101 1235 1339 BRANCH DISPLOOP0069 010001001 1340 LDP 90053 001000000 1341 LET4 TCY 00026 010010110 1342 LDX 6004C 000101001 1343 TMA0018 000010101 1344 AMAAC MULTIPLY BY 20031 000101111 1345 TAM0062 010011110 1346 LDX 7 *0045 000101001 1347 TMA000A 000010101 1348 AMAAC0015 111000010 1394 1349 CALL TLETTER CARRY, GO TO TLETTER0028 000101111 1350 TAM0056 010011110 1351 LDX 7002C 000101001 1352 TMA0058 001110011 1353 ACACC 120030 111000000 1394 1354 CALL TLETTER0060 000101111 1355 TAM 1356 * LOADS LETTER ADDRESS INTO FOM ADDR AREA (RAM)0041 010000111 1357 CALLL SPEAK+10002 110000001 2010 13580005 010011100 1359 LDX 3 FLAG0008 001001011 1360 TCY 13 *0017 001100011 1361 TCMIY 12002F 010010100 1362 LDX 2 FLAG005E 001001111 1363 TCY 15 *003C 001100110 1364 TCMIY 60078 001001000 1365 TCY 10071 010001101 1366 CALLL COMX80063 110011000 1632 13670047 010000101 1368 CALLL DPLOAD000E 111110011 1457 1369001D 010000010 1370 BL ADDCTR60038 101011001 0704 13710076 001000100 1372 LET+4 TCY 2 1373 * SPEAKS LETTER006D 010110010 1374 COMX8 *0058 010100111 1375 RBIT 30036 000100001 1376 TBIT 2 *006C 100010010 1383 1377 BRANCH WESTO0059 001001000 1378 TCY 10032 000110010 1379 IMAC BUMP POINTER FOR CSB0064 000101111 1380 TAM *0049 101110111 1310 1381 BRANCH LETTER+1 GET NEXT LETTER--ALWAYS B. 1382 * RESTORE LNK/EDT POINTER AND RETURN TO CONTINUE SPEAKING0012 010000001 1383 REST0 BL DISLP-50025 101100011 1232 1384004A 010100101 1385 REST02 RBIT 20014 010010100 1386 LDX 20029 001001111 1387 TCY 150052 001101100 1388 TCMIY 30024 001001000 1389 TCY 10048 010110010 1390 COMX80010 010000101 1391 BL REPT20021 100000011 1439 1392 1393 * INCREMENT WHEN OVERFLOW OCCURS0042 000101111 1394 TLETTER TAM0004 010010110 1395 LDX 60009 000110010 1396 IMAC0013 010111111 1397 RETN0027 000000110 1398 DELAY2 CLA004E 010010100 1399 LDX 2 DELAY BUFFER--RAM001C 001000001 1400 TCY 8 *0039 001100000 1401 TCMIY 0 CLEAR0072 001100000 1402 TCMIY 0 *0065 001100000 1403 TCMIY 00048 001000001 1404 TCY 80016 000101111 1405 DELAY2+1 TAM002D 000110010 1406 IMAC005A 101101000 1409 1407 BRANCH PLUSONE0034 100010110 1405 1408 BRANCH DELAY2+10068 000101101 1409 PLUSONE TAMIYC0051 000110010 1410 IMAC0022 100010001 1414 1411 BRANCH WORD30044 000101100 1412 TAMDYN0008 100010110 1405 1413 BRANCH DELAY2+10011 000101101 1414 WORD3 TAMIYC0023 000110010 1415 IMAC0046 101100110 1420 1416 BRANCH QUIT000C 000101100 1417 TAMDYN0019 000000100 1418 DYN0033 100010110 1405 1419 BRANCH DELAY2+10066 010111111 1420 QUIT RETN 1421 *004D 010001110 1422 F4 CALLL FL2 STORE * OF WRONG RESPONSES001A 110001100 1145 14230035 010000110 1424 CALLL F2LOOP006A 111100100 0972 14250055 010000101 1426 CALLL MEMADDR002A 111011000 1501 14270054 010001110 1428 CALLL LOADRESS0028 111000010 1121 14290050 010000110 1430 BL FINL30020 100110100 0998 1431__________________________________________________________________________
TABLE IX-10__________________________________________________________________________ 1432 ORGPG 10 1433 * 1434 * REPEAT ROUTINE.fwdarw.REPEATS PHRASE PREVIOUSLY SPOKEN 1435 * TWO REPEATS OR MORE CAUSES PHRASE TO BE SPOKEN SLOWER 1436 *0000 010010100 1437 REPEAT LDX 20001 001001111 1438 TCY 150003 001100000 1439 REPT2 TCMIY 00007 010011000 1440 LDX 1000F 001000101 1441 TCY 10001F 010110010 1442 RPT+1 COMX8 DAM REG003F 000101001 1443 TMA STORE WORD.fwdarw.ACC007F 010110010 1444 COMX8 EXIT DAM007E 000101101 1445 TAMIYC007D 001010111 1446 YNEC 14 *007B 100011111 1442 1447 BRANCH RPT+1 *0077 010110010 1448 COMX8006F 001001000 1449 TCY 1005F 001100000 1450 TCMIY 0003E 010000111 1451 BL ADDWDS2007C 100001010 2057 1452 1453 * LOADDISP.fwdarw. 1454 * SUBROUTINE TO DISPLAY WORD BEING USED IN LEARN MODE 1455 *0079 001000000 1456 LOADDISP TCY 0 INITIALIZE Y/POINTER0073 010011100 1457 DPLOAD LDX 3 TRANSFER LSW'S0067 000101001 1458 TMA *004F 010011000 1459 LDX 1 *001E 000101111 1460 TAM *0030 010010100 1461 LDX 2 TRANSFER MSW'S007A 000101001 1462 TMA *0075 010010000 1463 LDX 0 *006A 000101111 1464 TAM0057 010111111 1465 RETN002E 000100000 1466 TBIT 0005C 101100001 1470 1467 BRANCH LDONE0038 001100000 1468 TCMIY 00070 101000011 1471 1469 BRANCH LDONE+10061 001101000 1470 LDONE TCMIY 10043 001010001 1471 LDONE+1 YNEC 80006 101110011 1457 1472 BRANCH DPLOAD NO, LOOP--ELSE,000D 010010001 1473 LDX 80018 001001110 1474 TCY 70037 000101010 1475 TMY006E 010000001 1476 LDP 80050 001011010 1477 YNEC 5003A 101011000 1219 1478 BRANCH DISLP70074 010000010 1479 BL ADDCTR60069 101011001 0704 1480 1481 * 1482 * 1483 * SETBIT2 - SUBROUTINE TO USE DAM REG FOR FLAG PURPOSES 1484 *0053 010110010 1485 SETBIT2 COMX8 DAM REG0026 001000100 1486 TCY 2004C 010100001 1487 SBIT 2 TEST BIT 20018 001001000 1488 TCY 10031 000101010 1489 TMY0062 010110010 1490 COMX8 EXIT DAM0045 010111111 1491 RETN 1492 *000A 010110010 1493 SETBIT1 COMX80015 001000100 1494 TCY 20028 010100010 1495 SBIT 10056 010110010 1496 COMX8002C 010111111 1497 RETN 1498 * 1499 * MEMLOOP- LOADS ADDRESS INTO RUN ADDRESS, 4 BITS AT A TIME 1500 *0058 001000011 1501 MEMADDR TCY 12 CHIP SELECT0030 000001101 1502 SETR0060 001001101 1503 TCY 11 L/R = 1 (INPUT)0041 000001101 1504 SETR R11 = 10002 001000101 1505 TCY 100005 000000110 1506 CLA0008 001111100 1507 ACACC 3 FOR LOOP COUNT, ACC = 30017 010010100 1508 LDX 2 MEMORY FOR LOOP (SAVE ADDR)002F 000101110 1509 MEMLOOP TAMZA005E 010011000 1510 LDX 1003C 001110100 1511 ACACC TWO0078 000001101 1512 SETR LOADS COMMAND0071 000110110 1513 RSTR *0063 000101001 1514 TMA 4 BITS OF ADDR.fwdarw.ACC0047 001110000 1515 ACACC 0000E 000001101 1516 SETR LOADS DATA001D 000110110 1517 RSTR *003B 001001011 1518 TCY 130076 000000011 1519 SHIFTUP XMA SHIFT ROUTINE *006D 000000100 1520 DYN * SHIFT UP IN *0058 001011001 1521 YNEC 9 * SAME REGISTER *0036 101110110 1519 1522 BRANCH SHIFTUP * * * * * * * * * * * *006C 001000101 1523 TCY 10 ORIGINAL WORD0059 010010100 1524 LDX 2 REG-60032 000000111 1525 DMAN MEM-1,.fwdarw. ACC LOOP0064 100101111 1509 1526 BRANCH MEMLOOP0049 000101111 1527 TAM0012 001111100 1528 ACACC 30025 000001101 1529 SETR004A 000110110 1530 RSTR0014 000000110 1531 CLA0029 000001101 1532 SETR0052 000110110 1533 RSTR0024 010011000 1534 MEMDRED LDX ONE * DUMMY READ TO SETUP MEMORY ADDRESS0048 001000101 1535 TCY TEN **0010 001110001 1536 ACACC EIGHT **0021 000001101 1537 SETR **0042 000110110 1538 RSTR **0004 010111111 1539 RETN0009 010001000 1540 MSPEL3 CALLL CLEAR0013 110111010 0236 15410027 010001001 1542 CALLL DELAY2004E 110100111 1398 1543001C 100000000 1437 1544 BRANCH REPEAT 1545 * SPELLING IS INCORRECT0039 010111111 1546 MISSPELL RETN0072 010110010 1547 COMX80065 001000110 1548 TCY 6 FLAG0048 010001000 1549 LDP 10016 000100010 1550 TBIT 1 BIT 1.fwdarw.0-FIRST TRY0020 100001001 0304 1551 BRANCH NOPHRASE BIT 1.fwdarw.1-SECOND TRY005A 010100010 1552 SBIT 1 * 1553 * LOAD NEGATIVE RESPONSE INTO L/E0034 010011010 1554 SCORE LDX 50068 001001011 1555 TCY 130051 000110010 1556 TMAC0022 000101111 1557 TAM0044 010011100 1558 LDX 30008 001001011 1559 TCY 13 FLAG0011 001100100 1560 TCMIY 20023 010001010 1561 CALLL CURLEVL0046 111101111 0769 1562000C 000000101 1563 TCY0019 001100110 1564 TCMIY 60033 010010100 1565 LDX 2 FLAG0066 001001111 1566 TCY 15 *004D 001100010 1567 TCMIY 4001A 010001000 1568 BL SPK40035 101100101 0311 1569006A 001100000 1570 ADDCTR2 TCMIY 0 FOR RETNSBCH0055 010011100 1571 LDX 3002A 001001011 1572 TCY 130054 001100010 1573 TCMIY 40028 010001101 1574 BL CORR+10050 101111110 1590 1575 1576 *__________________________________________________________________________
TABLE IX-11__________________________________________________________________________ 1577 ORGPG 11 1578 * 1579 * POINTERS DAM-WORD 0.fwdarw. RANDOM WORD ENTRY POINTER 1580 * POINTER DAM-WORD 1.fwdarw. CORRECR SPELLING BUFFER POINTER 1581 *0000 010110010 1582 CORRSSPL COMX8 DAM REG-POINTER0001 001000000 1583 TCY 00003 001100000 1584 TCMIY 0 ZEROS OUT POINTER0007 001100000 1585 TCMIY 0000F 001100000 1586 TCMIY 0001F 001100000 1587 TCMIY 0003F 010110010 1588 COMX8 OUT OF DAM REG007F 010111111 1589 RETN007E 010001010 1590 CORR+1 CALLL CURLEVL007D 111101111 0769 1591007B 001001111 1592 TCY 150077 000101001 1593 TMA006F 000010101 1594 AMAAC005F 001110010 1595 ACACC 4003E 001000101 1596 TCY 10007C 000101111 1597 TAM0079 010000111 1598 CALLL ADD80073 110001100 2139 15990067 010000101 1600 CALLL MEMADDR004F 111011000 1501 1601001E 010001110 1602 CALLL LOADRESS003D 111000010 1121 1603 1604 * 1605 * RESIDENT: 1606 * LOOP TO TRANSFER ADDRESS FROM RESIDENT (RAM) TO ADDRESS 1607 * REGION (RAM) 1608 *007A 001001110 1609 RESIDENT TCY 7 OLD BLKCSB ROUTINE0075 000000110 1610 CSB2 CLA006B 001111000 1611 ACACC 10057 010010100 1612 LDX 2002E 000101111 1613 TAM005C 010011100 1614 LDX 30038 001110101 1615 ACACC 100070 000101100 1616 TAMDYN0061 101110101 1610 1617 BRANCH CSB20043 010011000 1618 LDX 10006 001000001 1619 TCY 8000D 001100100 1620 TCMIY 20018 010011010 1621 ADRSCALC LDX 5 LSW0037 111001100 1631 1622 CALL BCOMX8006E 000101001 1623 ADD2ROM TMA READY FOR ADDITION0050 010011000 1624 LDX 1 LSW OF ROM ADDR REGION003A 001000101 1625 TCY 100074 010000000 1626 CALLL ADDCARRY0069 111011000 0112 16270053 010010010 1628 LDX 40026 001000000 1629 TCY 0 * 1630 *004C 001000000 1631 RCOMX8 TCY 00018 010110010 1632 COMX8 COMX80031 000101010 1633 TMY0062 010110010 1634 COMX80045 010111111 1635 RETN000A 000101001 1636 TMA0015 010011000 1637 LDX 1 ROM ADDR REGION0028 001001101 1638 TCY 11 *0056 010000000 1639 CALLL ADDCARRY002C 111011000 0112 16400058 001000001 1641 TCY 8 *0030 000000111 1642 DMAN ADD2ROM TO BE EXECUTED TWICE0060 000101111 1643 TAM *0041 000110011 1644 MNEZ0002 100011011 1621 1645 BRANCH ADRSCALC0005 010000101 1646 CALLL MEMADDR0008 111011000 1501 16470017 010001110 1648 CALLL LOADRESS002F 111000010 1121 1649005E 010000101 1650 CALLL MEMADDR003E 111011000 1501 1651 1652 *0078 010000011 1653 BL OUTADDR0071 100000000 1723 1654 1655 *0063 000101111 1656 TONE22 TAM0047 010001010 1657 TONES CALLL CURLEVL000E 111101111 0769 1658001D 001100001 1659 TCMIY 80038 001101110 1660 TCMIY 7 *0076 010011100 1661 LDX 30060 001000001 1662 TCY 80058 010100100 1663 RBIT 00036 010100111 1664 RBIT 3006C 000101001 1665 TMA0059 010011000 1666 LDX 10032 001000101 1667 TCY 100064 000010101 1668 AMAAC0049 100100100 1676 1669 BRANCH TONCARRY0012 000101111 1670 TONE3 TAM0025 010010100 1671 LDX 2004A 001001111 1672 TCY 150014 001100100 1673 TCMIY 20029 010000010 1674 BL ADDCTR60052 101011001 0704 16750024 000101101 1676 TONCARRY TAMIYC0048 000110010 1677 IMAC0010 000101111 1678 TAM0021 100010010 1670 1679 BRANCH TONE30042 001001110 1680 NXTTONE TCY 70004 010010001 1681 LDX 80009 000101010 1682 TMY0013 001011010 1683 YNEC 50027 101100101 1669 1684 BRANCH CRY24004E 010010100 1685 LDX 2001C 001001111 1686 TCY 150039 001101110 1687 TCMIY 70072 101001011 1692 1688 BRANCH TONESCON0065 001100000 1689 CRY24 TCMIY 0 1690 * RETURN TO ROUTINE 1691 *0048 010010001 1692 TONESCOR LDX 80016 001000001 1693 TCY 80020 000100001 1694 TBIT 2005A 101010001 1698 1695 BRANCH TON120034 010001111 1696 BL DISP/KB0068 100101100 2219 16970051 010010100 1698 TON12 LDX 20022 001000111 1699 TCY 140040 000000111 1700 DMAN0008 101100011 1656 1701 BRANCH TONE220011 010010001 1702 LDX 80023 001000001 1703 TCY 80046 010100101 1704 RBIT 2000C 010011010 1705 LDX 50019 001001011 1706 TCY 130033 000101001 1707 TMA0066 010011000 1708 LDX 10040 010000110 1709 LDP 6001A 011101001 1710 ALEC 90035 101101100 0969 1711 BRANCH F5006A 010001010 1712 CALLL CURLEVL0055 111101111 0769 1713002A 001100110 1714 TCMIY 60054 001101110 1715 TCMIY 70028 010000010 1716 BL ADDCTR60050 101011001 0704 1717__________________________________________________________________________
TABLE IX-12__________________________________________________________________________ 1718 ORGPG 12 1719 * 1720 * OUTADDR- 1721 * LOADS CORRECT SPELLING BUFFER WITH ACTUAL SPELLING CODE 1722 *0000 010001110 1723 OUTADDR CALLL OUTADDR20001 111000001 1083 17240003 010011100 1725 LDX 30007 001001000 1726 TCY 1 *000F 010001101 1727 CALLL COMX8001F 110011000 1632 1728003F 000101111 1729 TAM007F 010001110 1730 CALLL OUTADDR2 PDC FOR OUTPUT COMMAND007E 111000001 1083 1731007D 010010100 1732 LDX 2007B 001001000 1733 TCY 10077 010001101 1734 CALLL COMX8006F 110011000 1632 1735005F 010000101 1736 LDP 10003F 000101111 1737 TAM007C 000100001 1738 TBIT 2 END OF SPELLING?0079 110001010 1493 1739 CALL SETBIT10073 010000011 1740 LDP 120067 010110010 1741 COMX8004F 001001000 1742 TCY 1001E 000110010 1743 IMAC INCREMENT COR SPEL POINTER003D 000101111 1744 TAM007A 001000100 1745 TCY 20075 000100010 1746 TBIT 1 TEST FLAG006B 100111000 1751 1747 BRANCH LNKSET0057 100101110 1749 1748 BRANCH EXDAM2002B 010110010 1749 EXDAM2 COMX8005C 100000000 1723 1750 BRANCH OUTADDR ADDR.fwdarw. ALWAYS BRANCH0038 000000110 1751 LNKSET CLA0070 001001001 1752 TCY 90061 010011000 1753 LDX 10043 000101111 1754 LNKSET+1 TAM0006 010001110 1755 CALLL OUTADDR2 PDC FOR OUTPUT 4 BITS0000 111000001 1083 17560018 010000101 1757 LDP 100037 011100000 1758 ALEC 0006E 111010011 1485 1759 CALL SETBIT20050 010000011 1760 LDP 12003A 011100000 1761 ALEC 00074 101001100 1766 1762 BRANCH LNKON0069 010000101 1763 LDP 100053 011101000 1764 ALEC 10026 110001010 1493 1765 CALL SETBIT1004C 010000011 1766 LNKON CALLL LNKPTR20018 111011110 1765 17670031 010001110 1768 CALLL OUTADDR2 PDC0062 111000001 1083 17690045 010000010 1770 LDP 4000A 001111111 1771 ACACC 150015 110011001 0745 1772 CALL TSTBIT2002B 001111000 1773 ACACC 10056 010000111 1774 CALLL LNKPTR002C 111101000 2130 17750058 000110010 1776 IMAC0030 000101111 1777 TAM *0060 010001110 1778 CALLL OUTADDR2 PDC'S0041 111000001 1083 17790002 010000010 1780 LDP 40005 001111111 1781 ACACC 150008 110011001 0745 1782 CALL TSTBIT20017 010000011 1783 LDP 12002F 001111000 1784 ACACC 1005B 010011000 1785 LNKPTR2 LDX 10030 001001001 1786 TCY 9 *0078 000101010 1787 TMY *0071 010011110 1788 LDX 70063 000101111 1789 TAM STORE WORD0047 001000101 1790 TCY 10 R10000B 010111111 1791 RETN0010 010001110 1792 CALLL OUTADDR2003B 111000001 1083 17930076 011100000 1794 ALEC 00060 101100100 1801 1795 BRANCH LNKEND0058 010000111 1796 LNKCNT CALLL LNKPTR0036 111101000 2130 1797006C 000110010 1798 LNKCNT2 IMAC0059 101000010 1813 1799 BRANCH ENDSPEL GO TO ENDSPEL0032 101000011 1754 1800 BRANCH LNKSET+1 ELSE0064 010110010 1801 LNKEND COMX80049 001000100 1802 TCY 20021 000100010 1803 TBIT 10025 100000100 1814 1804 BRANCH ENDSPEL1004A 000100001 1805 TBIT 20014 101010010 1808 1806 BRANCH LNK40029 101011011 1796 1807 BRANCH LNKCNT0052 000100000 1808 LNK4 TBIT 00024 100010001 1833 1809 BRANCH F90048 010100000 1810 SBIT 00010 010000001 1811 BL CALADDR0021 100000000 1164 18120042 010110010 1813 ENDSPEL COMX8 ADDRESS DAM0004 001000100 1814 ENDSPEL1 TCY 20009 001100000 1815 TCMIY 00013 010011100 1816 LDX 30027 001001011 1817 TCY 13004E 000101001 1818 TMA001C 010000111 1819 LDP 140039 011101100 1820 ALEC 30072 100000000 2009 1821 BRANCH SPEAK0065 010000011 1822 LDP 12004B 011100010 1823 ALEC 4 'SPELL'0016 100101010 1847 1824 BRANCH USPELL30020 010000001 1825 LDP 80054 011101010 1826 ALEC 5 'SAY IT'0034 100101011 1216 1827 BRANCH DISLP-10068 010001100 1828 LDP 30051 011100111 1829 ALEC 140022 101001111 0501 1830 BRANCH HANG0044 010001111 1831 BL DISP/KB0008 100101100 2219 18320011 010010010 1833 F9 LDX 4 1834 * TRANS.fwdarw.STORES CALCULATED ADDRESS IN DAM FOR USE IN LINK/EDIT 1835 *0023 001000101 1836 TRANS-1 TCY 100046 000101001 1837 TRANS TMA LOAD ACC000C 010110010 1838 COM8X0019 000101101 1839 TAMIYC0033 010110010 1840 COMX80066 001010111 1841 YNEC 140040 101000110 1837 1842 BRANCH TRANS001A 010111111 1843 RETN0035 010110010 1844 COMX8006A 010000001 1845 BL CALADDR0055 100000000 1164 1846002A 010000111 1847 USPELL3 CALLL SPEAK+10054 110000001 2010 18480028 010000011 1849 CALLL TRANS-10050 110100011 1836 18500020 010000111 1851 BL SPEAK0040 100000000 2009 1852__________________________________________________________________________
TABLE IX-13__________________________________________________________________________ 1853 ORGPG 13 1854 * 1855 * 1856 * 1857 * THE FOLLOWING ROUTINE DIRECTS THE PROGRAM FLOW 1858 * ACCORDING TO THE KEY PRESSED. 1859 *0000 000100010 1860 KEY00 TBIT 10001 100111011 1933 1861 BRANCH KEY20003 010010001 1862 KEY0 LDX 8 * LETTER KEYS0007 001000001 1863 TCY 8000F 000100010 1864 TBIT 1 TEST GO FLAG001F 101011111 1875 1865 BRANCH TRANSFER003F 001001110 1866 TCY 7007F 000100001 1867 TBIT 2 TEST FOR MODE OTHER THAN SPELL 1868 * * OR LEARN007E 101011111 1875 1869 BRANCH TRANSFER007D 011101100 1870 ALEC 3 A,B,C,D?007B 101100001 1892 1871 BRANCH REV120077 010000010 1872 KEY13 BL DIFFSLV CHANGE LEVL IN DISPLAY006F 101111110 0629 1873 1874 *005F 001001110 1875 TRANSFER TCY 7003B 010010001 1876 LDX 8007C 000101010 1877 TMY0079 001011010 1876 YNEC 50073 100011110 1882 1879 BRANCH TRAN830067 010000010 1880 BL NOSTRANS004F 100101100 0680 1881001B 001001111 1882 TRANS3 TCY 15003D 010010000 1883 LDX 0007A 000101001 1884 TMA0075 001001101 1885 TCY 110068 000101010 1886 TMY0057 010001000 1887 LDP 1002E 001010001 1888 YNEC 8005C 100000000 0194 1889 BRANCH NOTFULL0038 010001011 1890 LDP 130070 100010100 1946 1891 BRANCH NOP0061 001001111 1892 KEY12 TCY 15 * STORE0043 010011000 1893 LDX 1 * NEW0006 000101111 1894 TAM * DIFFICULTY LEVEL0000 101110111 1872 1895 BRANCH KEY130018 011100101 1896 KEY1 ALEC 10 * MSD=10037 101000111 1930 1897 BRANCH KEY15006E 011100111 1898 ALEC 140050 101101001 1902 1899 BRANCH KEY70034 010000010 1900 BL GAME#2 KEY=1F * CODEBREAKER0074 100000000 0620 19010069 011101011 1902 KEY7 ALEC 130053 100011000 1906 1903 BRANCH KEY80026 010001100 1904 BL GAME#1 KEY=1E * HANGMAN004C 100000000 0479 19050018 010010001 1906 KEY8 LDX 80031 001001110 1907 TCY 70062 000101010 1908 TMY PUT MODE # IN Y0045 011101101 1909 ALEC 11000A 101000001 1918 1910 BRANCH KEY140015 001011010 1911 YNEC 5 * CHECK MODE --002B 100101100 1914 1912 BRANCH K10A * IGNORE ERASE AND0056 100010100 1946 1913 BRANCH NOP002C 001000001 1914 K10A TCY 80058 000100010 1915 TBIT 1 TEST GO FLAG0030 100000101 1921 1916 BRANCH KEY100060 100010100 1946 1917 BRANCH NOP0041 010001110 1918 KEY14 BL ROM0002 101010101 1153 1919 1920 * * HANGMAN MODE0005 011100011 1921 KEY10 ALEC 12000B 100010001 1974 1922 BRANCH ERASE KEY=1C * ERASE0017 001001110 1923 TCY 7002F 000101010 1924 TMY005B 001011110 1925 YNEC 7 * IGNORE ENTER003C 101110001 1928 1926 BRANCH KEY9 * IN RANDOM LETTER0078 100010100 1946 1927 BRANCH NOP * MODE0071 010001000 1928 KEY9 BL ENTER KEY=1D * ENTER0063 101011000 0254 19290047 000101011 1930 KEY15 TYA PUT 15 IN ACC000E 010001011 1931 BL KEY0 * LETTERS Q-Z001D 100000011 1862 19320038 010010001 1933 KEY2 LDX 8 MSD=20076 001001110 1934 TCY 7006D 011101100 1935 ALEC 3005B 101010010 1949 1936 BRANCH KEY30036 011100110 1937 ALEC 6006C 101110010 1962 1938 BRANCH KEY60059 000101010 1939 TMY PUT MODE IN Y0032 001011010 1940 YNEC 5 * IGNORE CLUE0064 100010100 1946 1941 BRANCH NOP * KEY UNLESS0049 010000110 1942 LDP 60012 001000001 1943 TCY 8 * IN HANGMAN MODE0025 000100010 1944 TBIT 1 * AND GO FLAG004A 101110000 0923 1945 BRANCH CLUE0014 010001111 1946 NOP BL DISP/KB * ENTER KEYS IN0029 100101100 2219 1947 1948 * KEY=27 * CLUE0052 011100100 1949 KEY3 ALEC 20024 100100001 1953 1950 BRANCH KEY40048 010000000 1951 BL OFF KEY=23 * OFF0010 101110001 0124 19520021 011101000 1953 KEY4 ALEC 10042 100010011 1957 1954 BRANCH KEY50004 010000100 1955 BL SPELL0009 100010001 0462 19560013 010000000 1957 KEY5 LDP 00027 011100000 1958 ALEC 0004E 101001001 0142 1959 BRANCH GAME#3 KEY=20 * RANDOM LETTER001C 010000100 1960 BL LEARN KEY=21 * LEARN0039 100011001 0466 19610072 000100001 1962 KEY6 TBIT 2 * TEST FOR MODES OTHER0065 100010100 1946 1963 BRANCH NOP * THAN SPELL OR LEARN004B 011100010 1964 K16 ALEC 40016 101000100 1972 1965 BRANCH K170020 001000001 1966 TCY 80054 000100010 1967 TBIT 1 GO FLAG0034 100001100 1977 1968 BRANCH K190068 011101010 1969 ALEC 5 REPLAY?0051 101001101 1981 1970 BRANCH K230022 100010100 1946 1971 BRANCH NOP0044 010001000 1972 K17 BL GO KEY=24 * GO0008 101111100 0213 19730011 010001000 1974 ERASE CALLL CLEAR0023 110111010 0236 19750046 100010100 1946 1976 BRANCH NOP000C 011101010 1977 K19 ALEC 50019 100100000 1990 1978 BRANCH K210033 010000101 1979 BL REPEAT0066 100000000 1437 1980004D 010010000 1981 K23 LDX 0001A 001000000 1982 TCY 00035 000110011 1983 MNEZ006A 100101010 1986 1984 BRANCH K200055 100010100 1946 1985 BRANCH NOP002A 010011000 1986 K20 LDX 10054 001110001 1987 ACACC 8 ACC=13 AFTER THIS INSTRUCTION0028 000001001 1988 MNEA0050 100010100 1946 1989 BRANCH NOP0020 010001000 1990 K21 BL REPLAY0040 100101100 0250 1991__________________________________________________________________________
TABLE IX-14__________________________________________________________________________ 1992 ORGPG 14 1993 1994 SPEAK 1995 ROUTINE TO CONTROL SPEECH TO AND FROM SYNTHESIZER 1996 1997 IF SS==SET, SPEAK WAS CALLED 1998 IF SS==RESET, MEMADDR WAS CALLED 1999 2000 IF SS=1, ADDRESSES ARE TRANSFERED FROM FILES 6 AND 7 TO FILE 2001 1, WORDS 10-13, ELSE IF SS=0, ADDRESS IS IN FILE 1 PRIOR TO CALL 2002 2003 2 POINTERS USED 2004 (1) LINK/EDIT POINTER FOR WORDS IN FILES 6 AND 7 2005 (2) ROM ADDR POINTER FOR WORDS IN FILE 1. 2006 2007 20080000 010110101 2009 SPEAK SEAC0001 010011000 2010 SPEAK+1 LDX 10003 001000001 2011 TCY 80007 001100101 2012 TCMIY 10 INITIALIZE ROM ADDR POINTER000F 001100000 2013 TCMIY 8 INITIALIZE LNK/EDT POINTER001F 001001001 2014 SPKLOP=1 TCY 9003F 000101010 2015 SPKLOOP TMY007F 010011110 2016 LDX 7 GET WORD FROM LNK/EDT007E 000101001 2017 TMA LOAD WORD IN ACC007D 010011000 2018 LDX 1 POINTER007B 001000001 2019 TCY 8 *0077 000101010 2020 TMY *006F 000101111 2021 TAM STORE WORD005F 001000001 2022 TCY 8 BUMP POINTER003E 000110010 2023 IMAC *007C 000101111 2024 TAM *0079 001001001 2025 TCY 9 GET FILE FOR NEXT WORD0073 000101010 2026 TMY0067 000000000 2027 COMX FILE 6004F 000101001 2028 TMA WORD==ACC001E 000000000 2029 COMX FILE 1003D 001000001 2030 TCY 8 POINTER0074 000101010 2031 TMY *0075 000101111 2032 TAM STORE WORD0068 001001001 2033 TCY 9 BUMP LNK/EDT POINTER0057 000110010 2034 IMAC IF > 15, RETURN002E 100100001 2111 2035 BRANCH RETURN005C 000101111 2036 TAM STORE INCREMENT0038 001000001 2037 TCY 8 BUMP ROM AREA POINTER0070 000110010 2038 IMAC *0061 000101110 2039 TAMZA0043 000101010 2040 TMY *0006 001010111 2041 YNEC 14 15 Y = 14?000D 100011111 2014 2042 BRANCH SPKLOP-10018 010111111 2043 RETN0037 001000101 2044 TCY 10 YES, CONTINUE006E 010000111 2045 ADDWDS LDP 14005D 000010101 2046 AMAAC003A 100001010 2057 2047 BRANCH ADDWDS20074 010000111 2048 LDP 140069 000000101 2049 IYC LOOP COUNT0053 001010111 2050 YNFC 14 *0026 101101110 2045 2051 BRANCH ADDWDS *004C 011101000 2052 ALEC 10018 100100001 2111 2053 BRANCH RETURN IF YES, RETURN0031 010001001 2054 LDP 90062 011100100 2055 ALEC 2 ACC==>2?0045 100000000 1299 2056 BRANCH LETTER0004 010000101 2057 ADDWDS2 CALLL MEMADDR0015 111011000 1501 2058 2059 RUM ADDRESSING SUBROUTINE: 2060 ASSUMES X AND Y HAVE BEEN DEFINED PRIOR TO CALLING 2061 2062 2063 LOADS ADDRESS INTO ROM ADDRESS AREA 2064 ALL R LINES, ETC. . . . REMAIN THE SAME AS WHEN 2065 ENTERING SUBROUTINE. 2066 2067 2068 2069 2070 END OF ROUTINE 2071002B 001000011 2072 MEMADDR2 TCY 12 C8, GIVING SYN, COMMANDS0056 000001101 2073 SFTR R12 = 1002C 000000110 2074 CLA005B 001110101 2075 SPKREG ACACC TEM0030 001000101 2076 TCY 100040 000001101 2077 SETR0041 000110110 2078 RSTR *0002 000000110 2079 SPKREG+1 CLA0005 001000011 2080 TCY 12000B 000001101 2081 SETR0017 001000101 2082 TCY 10002F 001110111 2083 ACACC 14005E 000001101 2084 SETR 1ST PDC LOADS COMMAND003C 000110110 2085 RSTR *0078 001001101 2086 TCY 110071 000110110 2087 RSTR0063 001000101 2088 TCY 100047 000001101 2089 SETR 2ND PDC APPLIES TALK TO CTLB000E 000110110 2090 RSTR *001D 001110000 2091 ACACC 00038 000001000 2092 TKA0076 000001101 2093 SETR 3RD PDC RELEASES OUTPUT006D 000110110 2094 RSTR *005B 001001101 2095 TCY 110036 000001101 2096 SETR006C 010011100 2097 LDX 30059 001001111 2098 TCY 150032 000101111 2099 TAM0064 000100000 2100 TBIT 00049 101011010 2125 2101 BRANCH BITSET00012 010011000 2102 LDX 10025 001000001 2103 TCY 8004A 001100101 2104 TCMIY 100014 000010010 2105 CCLA0029 011100000 2106 ALEC ZERO0052 101001000 2109 2107 BRANCH RET50024 100011111 2014 2108 BRANCH SPKLOP-10048 010011000 2109 RET5 IDX 10010 001000001 2110 TCY 80021 000101110 2111 RETURN IAMZA ACC = ZERO0042 001001111 2112 TCY 150004 010010110 2113 RETURN4 LDX SIX0009 000101111 2114 TAM0013 010011110 2115 LDX SEVEN0027 000101100 2116 TAMDYN004E 100000100 2113 2117 BRANCH RETURN4001C 010111111 2118 RETN0039 010110100 2119 BETURN+1 REAC0072 001001111 2120 RETURN+2 TCY 15 TALK BIT0065 010011100 2121 LDX 3 *004B 010100100 2122 RBIT 0 *0016 010000010 2123 BL RETNSBCH002D 101001010 0710 2124005A 010001111 2125 BITSET0 LDP 150034 100101100 2219 2126 BRANCH DISP/KB 2127 2128 END OF SPEECH CONTROL SUBROUTINE 21290068 010011000 2130 LNKPTR LDX 1 POINTER FOR LNK/EDT0051 001001001 2131 TCY 9 *0022 000101010 2132 TMY *0044 010010110 2133 LDX 60008 000101111 2134 TAM STORE WORD0011 010011000 2135 LDX 1 POINTER0023 001001001 2136 TCY 9 *0046 010111111 2137 RETN 2138 *000C 001000110 2139 ADD8 TCY 60019 010010001 2140 LDX 80033 000100011 2141 TBIT 30066 100011010 2144 2142 BRANCH RADD80040 101010101 2147 2143 BRANCH RADD20014 010011000 2144 RADD8 LDX 10035 001001011 2145 TCY 130064 001100001 2146 TCNIY 80055 010111111 2147 RADD2 RETN__________________________________________________________________________
TABLE IX-15 2148 ORGPG 15 2149 2150 POWER UP/CLEAR ROUTINE 2151 2152 THIS ROUTINE SETS UP INITIAL CONDITIONS IN RAM 2153 2154 2155 0000 001001111 2156 START TCY FIFTEEN * RESET ALL R-LINES 0001 000110110 2157 LOOP$ST RSTR ** 0003 000000100 2158 DYN ** 0007 100000001 2157 2159 BRANCH LOOP$ST ** 000F 001001011 2160 TCY 13 001F 000001101 2161 SETR 003F 001001111 2162 TCY 15 007F 010111111 2163 RETN ** 007E 000000110 2164 CLA ** 007D 010010001 2165 LDX 8 007B 110101110 2183 2166 CALL FIL$LOOP ** 0077 010011110 2167 LDX SEVEN ** 006F 110101110 2183 2168 CALL FIL$LOOP ** 005F 010010110 2169 LDX SIX ** 003E 110101110 2183 2170 CALL FIL$LOOP ** 007C 010011010 2171 LDX FIVE ** 0079 110101110 2183 2172 CALL FIL$LOOP ** 0073 010010010 2173 LDX FOUR ** 0067 110101110 2183 2174 CALL FIL$LOOP ** 004F 010011100 2175 LDX THREE ** 001E 110101110 2183 2176 CALL FIL$LOOP ** 003D 010010100 2177 LDX TWO ** 007A 110101110 2183 2178 CALL FIL$LOOP ** 0075 010011000 2179 LDX ONE ** 006B 110101110 2183 2180 CALL FIL$LOOP ** 0057 010010000 2181 LDX ZERO ** 2182 * 002E 000101100 2183 FIL$LOOP TAMDYN * ROUTINE FILLS FILE WITH CONTENTS 005C 100101110 2183 2184 BRANCH FIL$LOOP ** OF ACC. 003B 010111111 2185 RETN ** 2186 * 2187 * 0070 010001000 2188 DSP7 CALLL CLEAR 0061 110111010 0236 2189 2190 * 0043 010000010 2191 CALLL DIFFSLV * DISPLAY DIFF LEVEL A - SPELL MODE 0006 111111110 0629 2192 000D 000000110 2193 CLA 001B 001001101 2194 TCY 11 0037 000110110 2195 RSTR 006E 001000011 2196 TCY 12 005D 000001101 2197 SETR 003A 001000101 2198 TCY 10 0074 000001101 2199 SETR 0069 000110110 2200 RSTR 0053 000001101 2201 SETR 0026 000110110 2202 RSTR 004C 001001101 2203 TCY 11 001B 000001101 2204 SETR 0031 001000101 2205 TCY 10 0062 000001101 2206 SETR 0045 000110110 2207 RSTR 000A 010000101 2208 CALLL MEMDRED 0015 110100100 1534 2209 002B 010001101 2210 BL TONES 0056 101000111 1657 2211 2212 2213 2214 KEYBOARD SCAN/DISPLAY ROUTINE 2215 2216 THIS ROUTINE DISPLAYS THE CONTENTS OF `DISPLAY BUFFER` AND 2217 CHACKS FOR A KEYPRESS. 2218 002C 010011100 2219 DISP/KB LDX 3 005B 001001101 2220 TCY 11 0030 001100000 2221 TCMIY 0 RESET TIMEOUT COUNTER 0060 000110110 2222 RSTR RESET R12 TO ENABLE DISPLAY 0041 001100000 2223 TCMIY 0 0002 000000110 2224 CLA 0005 001000011 2225 DSP1 TCY 12 0008 010010000 2226 LDX 0 0017 000101101 2227 TAMIYC STORE DEBOUNCE COUNTER, SET Y=0 002F 001100000 2228 TCMIY 0 RESET R-LINE POINTER 005E 001001111 2229 TCY 13 003C 000001101 2230 SETR R-15, TURN ON FILAMENT 007B 001000000 2231 TCY 0 0071 010011000 2232 DSP2 LDX 1 * 0063 000101001 2233 TMA * 0047 010110000 2234 TDO * LOAD SEGMENT PLA 000E 010010000 2235 LDX 0 * 001D 000101001 2236 TMA * 003B 000001001 2237 MNEA * 0076 010110000 2238 TDO * 006D 000001101 2239 SETR TURN ON NEW R-LINE 005B 001001111 2240 TCY 15 0036 000110110 2241 RSTR R-15, TURN OFF FILAMENT 006C 010000000 2242 BL TIMEUP * INCREMENT RONDOM NUMBER GENERATOR/ 0059 101000101 0103 2243 2244 * * TIMEOUT COUNTER 0032 001001011 2245 DISP/KB1 TCY 13 0064 000110010 2246 IMAC INCREMENT R-LINE POINTER 0049 000101111 2247 TAM 0012 001001111 2248 TCY 15 0025 000001101 2249 SETR TURN ON FILAMENT 004A 000101000 2250 TAY 0014 000000100 2251 DYN 0029 000110110 2252 RSTR RESET LAST R-LINE 0052 000000101 2253 TYC 0024 001010001 2254 YNEC 8 SCAN COMPLETE? 0048 101110001 2232 2255 BRANCH DSP2 NO 0010 001001111 2256 TCY 15 YES 0021 000110110 2257 RSTR RESET FILAMENT 0042 010000000 2258 CALLL TIMEUP1 INCREMENT RANDOM NUMBER/TIMEOUT COUNTER 0004 110101011 0106 2259 2260 * ONE EXTRA TIME, TOTAL=9 PER DISPLAY SCAN 0009 010020000 2261 LDX 0 0013 001000101 2262 TCY 10 0027 000110010 2263 IMAC INCREMENT DEBOUNCE COUNTER 004E 100111001 2266 2264 BRANCH DSP3 001C 000101111 2265 TAM 0039 001000011 2266 DSP3 TCY 12 0072 000110010 2267 IMAC 0065 011100101 2268 ALEC 10 004B 100000101 2225 2269 BRANCH DSP1 CONTINUE DISPLAY IF<8 0016 010000111 2270 LDP 14 002D 001001111 2271 TCY 15 005A 010011100 2272 LDX 3 0034 000100000 2273 TBIT 0 006B 101011000 2075 2274 BRANCH SPKREG + 1 TEST TALK 0051 010000001 2275 LDP 8 0022 001000111 2276 TCY 14 0044 000101011 2277 TYA SET ACC=14 000B 000100000 2278 TBIT 0 0011 101101100 1241 2279 BRANCH DISPLY+1 0023 010001111 2280 LDP 15 0046 100000101 2225 2281 BRANCH DSP1 BET 000C 010010000 2282 KEY$EVL LDX 0 0019 001000111 2283 TCY 14 * PUT LSD OF KEY CODE 0033 000101001 2284 TMA * IN ACC 0066 001001111 2285 TCY 15 004D 010001011 2286 LOP 13 001A 000100000 2287 TBIT 0 0035 100011011 1896 2288 BRANCH KEY1 006A 100000000 1860 2289 BRANCH KEY00 2290 * 0055 010010001 2291 SETBIT3 LDX 8 002A 001000100 2292 TCY 2 0054 010100011 2293 SBIT 3 SET BIT 3 002B 010111111 2294 RETN 2295 * 2296 END
TABLE X______________________________________I.sub.0 /I.sub.1 COMMANDSI.sub.0 I.sub.1______________________________________0 0 No Operation0 1 Load Address (LA)1 0 Transfer Bit (TB)1 1 Read and Branch (RB)______________________________________
TABLE XI______________________________________Counter 619/PLA 620 Timing Sequence COUNTERSTEP CONTENTS (HEX) SIGNALS GENERATED______________________________________1 0 ##STR5##2 8 ##STR6##3 C ##STR7##4 E ##STR8##5 F6 77 38 1______________________________________
TABLE XII______________________________________TB8 READ SEQUENCE COUNTER 623 CONTENTS COUNTER 624 SIGNALSSTEP (BINARY) CONTENTS (HEX) GENERATED______________________________________1 10 F SAD, INC2 10 E DC, INC3 10 C DC, INC4 10 8 DC, INC5 10 0 DC, INC6 10 1 DC, INC7 10 3 SAM, DC, INC8 10 7 ##STR9##______________________________________
TABLE XIII______________________________________RB READ SEQUENCE COUNTER 623 CONTENTS COUNTER 624 SIGNALSSTEP (BINARY) CONTENTS (HEX) GENERATED______________________________________ 1 11 F SAD, INC 2 11 E DC, INC 3 11 C DC, INC 4 11 8 DC, INC 5 11 0 DC, INC 6 11 1 DC, INC 7 11 3 SAM, DC, INC 8 11 7 PC 9 01 F SAD, TF10 01 E BR, PC11 01 C BR, DC12 01 8 BR, DC13 01 0 BR, DC14 01 1 DC15 01 3 SAM, DC16 01 7 PC17 00 F SAD, TF18 00 E BR19 00 C BR20 00 8 BR21 00 022 00 123 00 324 00 7 PC25 10 F SAD, INC26 10 E DC, INC27 10 C DC, INC28 10 8 DC, INC29 10 0 DC, INC30 10 1 DC, INC31 10 3 SAM, DC, INC32 10 7 ##STR10##______________________________________

Number	Name	Date
3371321	Adams	Feb 1968
3470321	Dersch	Sep 1969
3870818	Barton et al.	Mar 1975
4016540	Hyatt	Apr 1977
4022974	Kohut et al.	May 1977
4059272	Pullman	Nov 1977
4060848	Hyatt	Nov 1977
4179584	Tanimoto et al.	Dec 1979
4215240	Ostrowski	Jul 1980

	Number	Date
Parent	873480	Jun 1986
Parent	187389	Sep 1980
Parent	901395	Apr 1978

Learning aid or game having miniature electronic speech synthesis chip

Information

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Date Filed

Date Issued

Inventors

Original Assignees

Examiners

Agents

CPC

US Classifications

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US

International Classifications

Abstract

Description

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Parent Case Info

US Referenced Citations (9)

Non-Patent Literature Citations (5)

Continuations (3)

Entry
Anonymous, "Talking Board . . . ", Computer Design, vol. 15, No. 7, pp. 46, 48, Jul. 1976.
TSI, "Applications for Speech . . . ", Telesensory Systems, Inc., 1976.
TSI, "Speech Calculator Owner's Manual", Telesensory Systems, Inc., 1976.
Weisbecker, "A Practical, Low-Cost, Home/School Microprocessor System", Computer, Aug. 1974, vol. 7, No. 8, pp. 20-30.
Dingwall et al., "Recording and Duplicating System for Teaching Apparatus", IBM Technical Disclosure Bulletin, Oct. 1977, vol. 20, No. 5, pp. 1865-1866.