Field of Invention
The present invention relates to a LED lighting, and more particularly, the present invention relates to a switching regulator with programmable input.
Description of Related Art
The LED driver is used to control the brightness of the LED in accordance with its characteristics. The LED driver is also utilized to control the current that flows through the LED. The present invention provides a primary-side controlled switching regulator with a programmable input for a LED driver. One object of this invention is to improve the power factor (PF) of the LED driver. The programmable input can also be used for the dimming control. It is another object of the invention.
It is an objective of the present invention to provide a LED drive circuit with programmable input. It can modulate the switching signal to regulate the output current for improving the power factor (PF) of the LED drive circuit.
It is an objective of the present invention to provide a LED drive circuit with programmable input. The programmable input can be used for the dimming control.
The LED drive circuit according to the present invention comprises a controller and a programmable signal. The controller generates a switching signal coupled to switch a magnetic device for generating an output current to drive a plurality of LEDs. The programmable signal is coupled to regulate a current-control signal of the controller. The switching signal is modulated in response to the current-control signal for regulating the output current. The level of the output current is correlated to the current-control signal. Further, the programmable signal is coupled to control a reference signal of the controller. The switching signal is modulated in response to the reference signal. The level of the output current is correlated to the reference signal.
The LED driver according to the present invention comprises a controller and a programmable signal. The controller generates a switching signal coupled to switch a transformer for generating a current input signal coupled to the controller and an output current connected to drive a plurality of LEDs. The programmable signal is coupled to modulate the current input signal. The current input signal is further coupled to generate a current-control signal. The current input signal is correlated to a switching current of the transformer. The switching signal is controlled in response to the current-control signal. The level of the output current is correlated to the current-control signal.
The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the present invention. In the drawings,
A controller 70 comprises a supply terminal VCC, a voltage-detection terminal VDET, a ground terminal GND, a current-sense terminal VS, an input terminal VCNT and an output terminal VPWM. The controller 70 is a primary-side controller that is coupled to control the power transistor 20 for switching the primary winding NP of the magnetic device. The voltage-detection terminal VDET is coupled to the auxiliary winding NA via a resistor 50 to receive a voltage-detection signal VDET for detecting a reflected voltage VAUX. The voltage-detection signal VDET is correlated to the reflected voltage VAUX. The reflected voltage VAUX further charges a capacitor 65 via a rectifier 60 for powering the controller 70. The capacitor 65 is coupled to the supply terminal VCC of the controller 70.
The current-sense terminal VS is coupled to a current-sense resistor 30. The current-sense resistor 30 is coupled from a source terminal of the power transistor 20 to a ground for converting a switching current IP of the magnetic device to a current input signal VIP. The switching current IP flows the power transistor 20. The output terminal VPWM outputs a switching signal VPWM to switch the offline transformer 10. The controller 70 generates the switching signal VPWM to switch the magnetic device through the power transistor 20 for generating an output current IO and controlling the switching current IP. The output current IO is coupled to drive LEDs 101 . . . 109. The input terminal VCNT receives a programmable signal VCNT to control the switching current IP and the output current IO.
A waveform detector 300 detects the witching current IP (as shown in
The integrator 500 is used to generate a current signal VY by integrating an average current signal IAVG (as shown in
A comparator 75 is associated with the PWM circuit 400 for controlling the pulse width of the switching signal VPWM in response to an output of the error amplifier. A positive input and a negative input of the comparator 75 are coupled to receive the output of the error amplifier and a ramp signal RMP respectively. The ramp signal RMP is provided by the oscillator 200. An output of the comparator 75 generates a current-control signal SI for controlling the pulse width of the switching signal VPWM. A current control loop is formed from detecting the switching current IP to modulate the pulse width of the switching signal VPWM. The current control loop controls the magnitude of the switching current IP in response to the reference signal VREF1.
The PWM circuit 400 outputs the switching signal VPWM for switching the offline transformer 10. The PWM circuit 400 according to one embodiment of the present invention comprises a D flip-flop 95, an inverter 93, an AND gate 91 and an AND gate 92. AD input of the D flip-flop 95 is supplied with a supply voltage VCC. An output of the inverter 93 is coupled to a clock input CK of the D flip-flop 95. The pulse signal PLS sets the D flip-flop 95 through the inverter 93. An output Q of the D flip-flop 95 is coupled to a first input of the AND gate 92. A second input of the AND gate 92 is coupled to the output of the inverter 93 and receives the pulse signal PLS through the inverter 93. An output of the AND gate 92 is also an output of the PWM circuit 400 that generates the switching signal VPWM. The D flip-flop 95 is reset by an output of the AND gate 91.
A first input of the AND gate 91 is supplied with a voltage-control signal SV. The voltage-control signal SV is generated by a voltage control loop, in which the voltage control loop is utilized to regulate the output voltage VO. A second input of the AND gate 91 is coupled to receive the current-control signal SI for achieving output current control. A third input of the AND gate 91 is coupled to receive a maximum-duty signal SM. The voltage-control signal SV, the current-control signal SI and the maximum-duty signal SM can reset the D flip-flop 95 for shorten the pulse width of the switching signal VPWM so as to regulate the output voltage VO and the output current IO. The maximum-duty signal SM is generated by a maximum duty circuit (DMAX) 650. The maximum duty circuit 650 can be utilized to limit the maximum-duty of the switching signal VPWM under 50%.
A positive input of a comparator 700 is coupled to receive a detect signal α VIN. A low-voltage threshold VTH is supplied with a negative input of the comparator 700. An enable signal SEN is generated at an output of the comparator 700 by comparing the detect signal α VIN with the low-voltage threshold VTH. The detect signal α VIN is correlated to the input voltage VIN. The output of the comparator 700 generates the enable signal SEN coupled to control an AND gate 710. Two inputs of the AND gate 710 receives the pulse signal PLS and the enable signal SEN respectively. An output of the AND gate 710 generates a sample signal SP coupled to the integrator 500. The detail description for input voltage VIN detection can be found in prior arts “Control method and circuit with indirect input voltage detection by switching current slope detection” U.S. Pat. No. 7,616,461 and “Detection circuit to detect input voltage of transformer and detection method for the same” U.S. 2008/0048633 A1.
The programmable signal VCNT generated at the input terminal VCNT is supplied to a positive input of a buffer amplifier 720. A negative input of the buffer amplifier 720 is connected to its output. A resistor 730 is coupled between the output of the buffer amplifier 720 and a reference voltage device 750. The reference voltage device 750 is connected to the reference signal VREF1 to clamp the maximum voltage of the reference signal VREF1. The reference voltage device 750 can be implemented by a zener diode. The programmable signal VCNT is coupled to regulate the current-control signal SI of the controller 70 through controlling the reference signal VREF1 of a current-loop. Furthermore, the programmable signal VCNT is coupled to control the reference signal VREF1 of the current-loop of the controller 70. The switching signal VPWM is modulated in response to the current-control signal SI for regulating the output current IO, and the level of the output current IO is correlated to the current-control signal SI. In other words, the switching signal VPWM is modulated in response to the reference signal VREF1, and the level of the output current IO is correlated to the reference signal VREF1.
Transistors 514, 515 and 519 form a first current mirror for producing a current I515 and a current I519 by mirroring the first current I512. Source terminals of the transistors 514, 515 and 519 of the first current mirror are coupled to the supply voltage VCC. Gate terminals of the transistors 514, 515, 519 and drain terminals of the transistors 512, 514 are connected together. Drain terminals of the transistors 515 and 519 generate the current I515 and I519 respectively. Transistors 516 and 517 form a second current mirror for generating a current I517 by mirroring the current I515. Source terminals of the transistors 516 and 517 of the second current mirror are coupled to the ground. Gate terminals of the transistors 516, 517 and drain terminals of the transistors 516, 515 are connected together. A drain terminal of the transistor 517 generates the current I517.
An amplifier 530, a resistor 531 and a transistor 532 form a second V-to-I converter for generating a second current I532 in response to the current-waveform signal VA. A positive input of the amplifier 530 is supplied with the current-waveform signal VA. A negative input of the amplifier 530 is coupled to a source terminal of the transistor 532 and one terminal of the resistor 531. The other terminal of the resistor 531 is coupled to the ground. An output of the amplifier 530 is coupled to a gate terminal of the transistor 532. A drain terminal of the transistor 532 generates the second current I532. Transistors 534 and 535 form a third current mirror for producing a current I535 by mirroring the second current I532. Source terminals of the transistors 534 and 535 of the third current mirror are coupled to the supply voltage VCC. Gate terminals of the transistors 534, 535 and drain terminals of the transistors 532, 534 are connected together. A drain terminal of the transistor 535 generates the current I535.
Transistors 536 and 537 develop a fourth current mirror for producing a current I537 in response to the current I535 and the current I517. Source terminals of the transistors 536 and 537 of the fourth current mirror are coupled to the ground. Gate terminals of the transistors 536, 537 and drain terminals of the transistors 536, 535 are connected together. The drain terminal of the transistor 536 and a drain terminal of the transistor 537 generate a current I536 and the current I537 respectively. The current I536 can be expressed by I536=I535−I517. The geometric size of the transistor 536 is twice the size of the transistor 537. Therefore the current I537 is the current I536 divided by 2. Transistors 538 and 539 form a fifth current mirror for generating a current I539 by mirroring the current I537. Source terminals of the transistors 538 and 539 of the fifth current mirror are coupled to the supply voltage VCC. Gate terminals of the transistors 538, 539 and drain terminals of the transistors 538, 537 are connected together. A drain terminal of the transistor 539 generates the current I539. The drains of the transistor 519 and the transistor 539 are coupled together for generating the average current signal IAVG by summing the current I519 and the current I539. A current feedback signal VX is therefore generated at the drain terminals of the transistor 519 and the transistor 539. The resistor 511, the resistor 531 and a capacitor 570 determine the time constant of the integrator 500, and the resistor 531 is correlated to the resistor 511.
A switch 550 is coupled between the drain terminal of the transistor 519 and the capacitor 570. The switch 550 is controlled by the discharge-time signal SDS and turned on only during the period of the discharge-time of the secondary side switching current IS. A transistor 560 is coupled to the capacitor 570 in parallel to discharge the capacitor 570. The transistor 560 is turned on by the clear signal CLR. The integrator 500 further includes a sample-and-hold circuit formed by a sample switch 551 and an output capacitor 571. The sample switch 551 is coupled between the capacitor 570 and the output capacitor 571. The switch 551 controlled by the sample signal SP serves to periodically sample the voltage across the capacitor 570 to the output capacitor 571. The current signal VY is therefore generated across the output capacitor 571. The sample-and-hold circuit is coupled to sample the current feedback signal VX for generating the current-control signal SI (as shown in
The first current mirror generates a current I831 by mirroring the current I820. Source terminals of the transistors 830 and 831 of the first current mirror are coupled to the supply voltage VCC. Gate terminals of the transistors 830, 831 and drain terminals of the transistors 830, 820 are connected together. A drain terminal of the transistor 831 generates the current I831. The second current mirror is coupled to the drain terminal of the transistor 831 to generate a current I833 by mirroring the current I831. Source terminals of the transistors 832 and 833 of the second current mirror are coupled to the ground. Gate terminals of the transistors 832, 833 and drain terminals of the transistors 832, 831 are connected together. A drain terminal of the transistor 833 generates the current I833. The current source 850 is coupled from the supply voltage VCC to the drain terminal of the transistor 833. The drain terminal of the transistor 833 further outputs the programmable current ICNT. As shown in
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
This reference is being filed as a Continuation Application of patent application Ser. No. 14/261,613, filed 25 Apr. 2014, currently pending, which is based on patent application Ser. No. 12/978,836, filed 27 Dec. 2010, issued as U.S. Pat. No. 8,742,677, which was based on Provisional Application No. 61,335,749, filed 11 Jan. 2010.
Number | Name | Date | Kind |
---|---|---|---|
4916530 | Nielson et al. | Apr 1990 | A |
6091614 | Malenfant | Jul 2000 | A |
6144222 | Ho | Nov 2000 | A |
6344981 | Norton et al. | Feb 2002 | B1 |
6538908 | Balakrishnan et al. | Mar 2003 | B2 |
6842350 | Yamada | Jan 2005 | B2 |
6853563 | Yang et al. | Feb 2005 | B1 |
6977824 | Yang et al. | Dec 2005 | B1 |
7038399 | Lys et al. | May 2006 | B2 |
7045973 | Schallmoser | May 2006 | B2 |
7245089 | Yang | Jul 2007 | B2 |
7502235 | Huang et al. | Mar 2009 | B2 |
7616461 | Yang et al. | Nov 2009 | B2 |
7888881 | Shteynberg et al. | Feb 2011 | B2 |
8098506 | Saint-Pierre | Jan 2012 | B2 |
8222832 | Zheng et al. | Jul 2012 | B2 |
8344657 | Zhan et al. | Jan 2013 | B2 |
8466628 | Shearer et al. | Jun 2013 | B2 |
8742677 | Yang et al. | Jun 2014 | B2 |
20080048633 | Li et al. | Feb 2008 | A1 |
20080170420 | Yang et al. | Jul 2008 | A1 |
20080278092 | Lys et al. | Nov 2008 | A1 |
20100013409 | Quek | Jan 2010 | A1 |
20100141178 | Negrete et al. | Jun 2010 | A1 |
20100308733 | Shao | Dec 2010 | A1 |
20110012530 | Zheng | Jan 2011 | A1 |
20110037414 | Wang | Feb 2011 | A1 |
20110175543 | Sun et al. | Jul 2011 | A1 |
20110266969 | Ludorf | Nov 2011 | A1 |
20110279044 | Maiw | Nov 2011 | A1 |
20120025736 | Singh | Feb 2012 | A1 |
20120319621 | Sutardja | Dec 2012 | A1 |
20130134894 | Kuang | May 2013 | A1 |
20130249440 | Doshi | Sep 2013 | A1 |
20140062333 | Sonobe | Mar 2014 | A1 |
20160088697 | Yan | Mar 2016 | A1 |
Number | Date | Country |
---|---|---|
101159416 | Apr 2008 | CN |
201131071 | Oct 2008 | CN |
2005-11739 | Jan 2005 | JP |
M292840 | Jun 2006 | TW |
I277852 | Apr 2007 | TW |
Entry |
---|
Supertex HV9903 White LED Driver, Initial Release, date made available to the public unknown (p. 11 is dated Oct. 7, 2003) pp. 1-12. (C) Supertex Inc., 1235 Bordeaux Drive, Sunnyvale, CA 94089. |
Petition for inter partes review of U.S. Pat. No. 9,049,764, Patent Trial and Appeal Board, filed Apr. 28, 2017. |
The United States District Court for the Northern District of California, San Francisco Division, Case 3:15-cv-04854-MMC, Document 52, Filed Apr. 29, 2016, Power Integrations, Inc., Plaintiff, Versus Fairchild Semiconductor International, Inc., Fairchild Semiconductor Corporation, and Fairchild (Taiwan) Corporation, Defendants, 32 pages. |
Curriculum Vitae of William K. Bohannon, 6 pages. |
Declaration of William Bohannon, IPR of U.S. Pat. No. 9,049,764, Apr. 28, 2017, 86 pages. |
“Process Dynamics and Control,” Dale E. Seborg, et al., 3rd Edition, p.cm., Library of Congress Cataloging-in-Publication Data, ISBN 978-0-470-12867-1, Excerpt pp. 274-275, Fig 15.1-15.2, 4 pages. |
American Heritage College Dictionary, 3rd Edition, p.cm., Library of Congress Cataloging-in-Publication Data, ISBN 0-395-66917-0, Excerpts p. 877, p. 1150, p. 303, 6 pages. |
The United States Patent and Trademark Office; Preliminary Amendment in Re-Issue Application; Semiconductor Components Industries, LLC; Filed Oct. 24, 2017; 7 pages. |
The United States Patent and Trademark Office; Disclaimer in Re-Issue Application; Semiconductor Components Industries, LLC; Filed Oct. 24, 2017; 1 page. |
Final Written Decision in inter partes review; 35 U.S.C. §318(a) and 37C.F.R. §42.73; IPR2017-01329; U.S. Pat. No. 9,049,764 B2; Paper No. 33; Nov. 7, 2018; 37 pages. |
Ta-Yung Yang, et al.; Petition for Inter Partes Review of U.S. Pat. No. 9,049,764; “LED Drive Circuit With a Programmable Input for LED Lighting”; Trial No. IPR2017-01329; Apr. 28, 2017; 81 pages. |
Decision.Institution of Inter Partes Review; Case IPR2017-0I329; U.S. Pat. No. 9,049,764; “LED Drive Circuit With a Programmable Input for LED Lighting”; Nov. 8, 2017; 28 pages. |
Ta-Yung Yang, et al.; Petition for Inter Partes Review of U.S. Pat. No. 9,049,764; “LED Drive Circuit With a Programmable Input for LED Lighting”; Trial No. IPR2017-01330; Apr. 28, 2017; 79 pages. |
Decision.Institution of Inter Partes Review; Case IPR2017-0I330; U.S. Pat. No. 9,049,764; “LED Drive Circuit With a Programmable Input for LED Lighting”; Nov. 8, 2017; 20 pages. |
Ta-Yung Yang, et al.; Petition for Inter Partes Review of U.S. Pat. No. 9,049,764; “LED Drive Circuit With a Programmable Input for LED Lighting”; Trial No. IPR2017-01331; Apr. 28, 2017; 66 pages. |
Decision.Institution of Inter Partes Review; Case IPR2017-0I331; U.S. Pat. No. 9,049,764; “LED Drive Circuit With a Programmable Input for LED Lighting”; Nov. 8, 2017; 19 pages. |
Actions on the Merits in copending U.S. Appl. No. 15/455,272. |
Number | Date | Country | |
---|---|---|---|
20150264761 A1 | Sep 2015 | US |
Number | Date | Country | |
---|---|---|---|
61335749 | Jan 2010 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 14261613 | Apr 2014 | US |
Child | 14725459 | US | |
Parent | 12978836 | Dec 2010 | US |
Child | 14261613 | US |