Claims
- 1. A semiconductor integrated circuit device comprising:a first circuit supplied with a first power supply voltage which outputs a first pair of complementary signals and receives a first signal, each of the first pair of complementary signals and the first signal having a first amplitude corresponding to the first power supply voltage; a second circuit supplied with a second power supply voltage higher than the first power supply voltage which outputs a second pair of complementary signals and receives a second signal, each of the second pair of complementary signals and the second signal having a second amplitude corresponding to the second power supply voltage; a level-up level conversion circuit which receives the first pair of complementary signals and outputs the second signal; and a level-down level conversion circuit which receives the second pair of complementary signals and outputs the first signal.
- 2. The semiconductor integrated circuit according to claim 1, further comprising:first and second potential points, defining the first power supply voltage; wherein the level-down level conversion circuit comprises: a first insulated-gate field-effect transistor of first conductivity type, which source is connected to the second potential point and which receives one of the second pair of complementary signals; a second insulated-gate field-effect transistor of first conductivity type, which source is connected to the second potential point and which receives another of the second pair of complementary signals; a third insulated-gate field-effect transistor of second conductivity type, which source is connected to the first potential point, which drain is connected to a drain of the first insulated-gate field-effect transistor and which gate is connected to a drain of the second insulated-gate field-effect transistor; and a fourth insulated-gate field-effect transistor of the second conductivity type, which source is connected to the first potential point, which drain is connected to the drain of the second insulated-gate field effect transistor and which gate is connected to the drain of the first insulated-gate field-effect transistor; wherein a gate insulation film of the third insulated-gate field-effect transistor or the fourth insulated-gate field-effect transistor is thinner than a gate insulation film of the first insulated-gate field-effect transistor or the second insulated-gate field-effect transistor.
- 3. The semiconductor integrated circuit according to claim 1, further comprising:third and fourth potential points, defining the second power supply voltage, wherein the level-up level conversion circuit comprising: a fifth insulated-gate field-effect transistor of first conductivity type, which source is connected to the fourth potential point and which receives one of the first pair of complementary signals; a sixth insulated-gate field-effect transistor of first conductivity type, which source is connected to the fourth potential point and which receives another of the first pair of complementary signals; a seventh insulated-gate field-effect transistor of the second conductivity type, which source is connected to the third potential point, which drain is connected to a drain of the fifth insulated-gate field-effect transistor and which gate is connected to a drain of the sixth insulated-gate field-effect transistor; and an eighth insulated-gate field-effect transistor of second conductivity type, which source is connected to the third potential point, which drain is connected to the drain of the sixth insulated-gate field-effect transistor and which gate is connected to the drain of the fifth insulated-gate field-effect transistor.
- 4. The semiconductor integrated circuit according to claim 3, further comprising:a ninth insulated-gate field-effect transistor of second conductivity type connected to the fifth insulated-gate field-effect transistor in series, which receives the one of the first pair of complementary signals; and a tenth insulated-gate field-effect transistor of second conductivity type connected to the sixth insulated-gate field-effect transistor in series, which receives the other of the first pair of complementary signals.
- 5. The semiconductor integrated circuit according to claim 1, wherein the level-up level conversion circuit includes a current source.
- 6. The semiconductor integrated circuit according to claim 5, wherein the current source comprises an eleventh insulated-gate field-effect transistor which gate is connected to a predetermined potential point.
- 7. The semiconductor integrated circuit according to claim 1, wherein the level-up level conversion circuit includes an inverter circuit which outputs the second signal.
Priority Claims (1)
Number |
Date |
Country |
Kind |
9-359273 |
Dec 1997 |
JP |
|
Parent Case Info
This is a continuation application of U.S. Ser. No. 10/122,178, filed Apr. 16, 2002, now U.S. Pat. No. 6,504,400 now allowed; which is a continuation application of U.S. Ser. No. 09/833,627, filed Apr. 13, 2001, now U.S. Pat. No. 6,392,439; which is a continuation application of U.S. Ser. No. 09/209,755, filed Dec. 11, 1998, now U.S. Pat. No. 6,249,145.
US Referenced Citations (18)
Foreign Referenced Citations (3)
Number |
Date |
Country |
0 334 050 |
Sep 1989 |
EP |
4-150222 |
May 1992 |
JP |
4-268818 |
Sep 1992 |
JP |
Continuations (3)
|
Number |
Date |
Country |
Parent |
10/122178 |
Apr 2002 |
US |
Child |
10/303841 |
|
US |
Parent |
09/833627 |
Apr 2001 |
US |
Child |
10/122178 |
|
US |
Parent |
09/209755 |
Dec 1998 |
US |
Child |
09/833627 |
|
US |