Level conversion circuit

BACKGROUND OF THE INVENTION
This invention relates to a level conversion circuit such as one used as the interface between the output of an ECL circuit and the input of a TTL circuit or an N-MOS circuit, for example.
Since the ECL (emitter coupled logic) circuit makes use of a negative power source voltage V.sub.EE, the signal level of the ECL circuit varies between ground potential (GND) and the negative power source voltage V.sub.EE. On the other hand, the TTL (transistor-transistor logic) circuit or the N-MOS (N channel insulated gate field effect transistor) circuit makes use of a positive power source voltage V.sub.CC and hence, the signal level of the TTL circuit or of the N-MOS circuit varies between the positive power source voltage V.sub.CC and ground potential (GND).
As the interface between the output of the first circuit operating on the negative power source voltage V.sub.EE and the input of the second circuit operating on the positive power source voltage V.sub.CC, a signal level conversion circuit is necessary. In an IC.sub.1 encompassed by the two-dot chain line in FIG. 1, a circuit indicated by l.sub.2 is a heretofore known semiconductor integrated circuit, forming a signal level conversion circuit. A first power terminal of the ECL circuit l.sub.1 is connected to the ground potential (GND) and a negative power source voltage V.sub.EE (e.g., -5.2 V) is impressed upon a second power terminal P.sub.2. Accordingly, the signal level of an output signal y obtained from an output terminal P.sub.7 of the ECL circuit l.sub.1 varies between the ground potential (GND) and the negative power source voltage V.sub.EE. A positive power source voltage V.sub.CC (e.g., +5.0 V) is impressed upon a first power terminal P.sub.10 of the TTL circuit l.sub.3 and its second power terminal P.sub.16 is connected to the ground potential (GND). Hence, the signal level of the TTL circuit l.sub.3 varies between the positive power source voltage V.sub.CC and ground potential (GND). The heretofore known level conversion circuit l.sub.2 is disposed between the output terminal P.sub.7 of the ECL circuit l.sub.1 and the input terminal P.sub.15 of the TTL circuit l.sub.3.
The signal level conversion circuit l.sub.2 includes a first input transistor Q.sub.18 having its base connected to the first input terminal P.sub.11, a second input transistor Q.sub.17 having its base connected to the second input terminal P.sub.12, a reference transistor Q.sub.16 the base of which receives a negative second reference voltage V.sub.b2 generated by a reference voltage generation circuit 1 and a current source transistor Q.sub.19 the base of which receives a negative first reference voltage V.sub.b1 generated by the reference voltage generation circuit 1. The reference voltage generation circuit 1 operates on the difference voltage between the negative power source voltage V.sub.EE and the ground potential (GND) and includes transistors Q.sub.9 and Q.sub.10, diodes D.sub.3 -D.sub.6 and resistors R.sub.7, R.sub.9 and R.sub.25. The emitter of the transistor Q.sub.9 of the reference voltage generation circuit 1 is connected to a terminal P.sub.13 and a negative third reference voltage V.sub.BB is obtained from this terminal P.sub.13.
The collector of the first input transistor Q.sub.18 and that of the reference transistor Q.sub.16 are connected to a first load resistor R.sub.32 at a first node N.sub.1 and the collector of the second input transistor Q.sub.17 is connected to a second load resistor R.sub.35 at a second node N.sub.2. When the first node N.sub.1 becomes high level, the first output transistor Q.sub.32 becomes conductive and an output signal of high level approximate to the positive power source voltage V.sub.CC is obtained at the output terminal P.sub.14. On the other hand, when the second node N.sub.2 becomes high level, the second output transistor Q.sub.33 becomes conductive and an output signal of low level approximate to the ground potential (GND) is produced at the output terminal P.sub.14. In this manner, the conversion output signal Y at the output terminal P.sub.14 of the signal level conversion circuit l.sub.2 varies substantially between the positive power source voltage V.sub.CC and the ground potential (GND) and is transmitted to the input terminal P.sub.15 of the TTL circuit l.sub.3.
By means of the connection arrangement outside the semiconductor integrated circuit, the output signal y of the ECL circuit l.sub.1 is applied to the first input terminal P.sub.11 of the signal level conversion circuit l.sub.2 while the third reference voltage V.sub.BB is applied to the second input terminal P.sub.12. In consequence, the phase of the conversion output signal Y at the output terminal P.sub.14 of the signal level conversion circuit l.sub.2 is opposite to the phase of the output signal y at the output terminal P.sub.7 of the ECL circuit l.sub.1.
Meanwhile, the negative power source voltage V.sub.EE for the first circuit such as the ECL circuit l.sub.1 and the positive power source voltage V.sub.CC for the second circuit such as the TTL circuit involve the possibility of inducing the fluctuation of the power source voltages, respectively.
Further, the switching speed of the output signal Y at the output terminal P.sub.14 of the signal level conversion circuit l.sub.2 is determined by the switching characteristics of the first and second input transistors Q.sub.18 and Q.sub.17.
In order to keep the switching speed of the signal level conversion circuit l.sub.2 at a high speed, therefore, the first and second input transistors Q.sub.18 and Q.sub.17 must be operated in the non-saturation mode. That is to say, when a bipolar transistor is driven into the saturation region, the base-collector junction is biased in the forward direction. Hence, the base layer and the collector layer cause minority carrier injection with each other and accumulation of this minority carrier markedly extends the switching time.
On the other hand, the reference voltage generation circuit 1 in the heretofore known signal level conversion circuit l.sub.2 shown in FIG. 1 generates a first reference voltage V.sub.b1 which depends upon the negative power source voltage V.sub.EE but not upon the positive power source voltage V.sub.CC, and by this first reference voltage V.sub.b1 is determined the value of a current I.sub.o flowing through the current source transistor Q.sub.19. Hence, the value of this current I.sub.o depends upon the value of the negative power source voltage V.sub.EE but not upon that of the positive power source voltage V.sub.CC.
Assume now that the output signal y at the output terminal P.sub.7 of the ECL circuit l.sub.1 is at a level which is approximate to the ground potential (GND). In this case, the second and third negative reference voltages V.sub.b2 and V.sub.BB are impressed upon the base of the reference transistor Q.sub.16 and upon that of the second input transistor Q.sub.17, respectively. Hence, the first input transistor Q.sub.18 becomes conductive while the reference transistor Q.sub.16 and the second input transistor Q.sub.17 remain non-conductive. Accordingly, the voltage V.sub.N1 at the first node N.sub.1 is given by the following equation;
V.sub.N1 =V.sub.CC -R.sub.32.I.sub.o ( 1)
When the negative power source voltage V.sub.EE is kept at a predetermined power source voltage (e.g., -5.2 V) while the positive power source voltage V.sub.CC drastically decreases from its predetermined power source voltage (e.g., +5.0 V) down to +3.0 V, for example, the first item on the right side of the above-mentioned equation (1) becomes smaller than the second item and hence, the voltage V.sub.N1 at the first node N.sub.1 becomes a negative voltage.
On the other hand, when the positive power source voltage V.sub.CC is kept at a predetermined power source voltage (e.g., 5.0 V) while the negative power source voltage V.sub.EE drastically increases from its predetermined power source voltage (e.g., -5.2 V) up to -7.0 V, for example, the value of the current I.sub.o flowing through the current source transistor Q.sub.19 increases. Due to the increase of the current, therefore, the second item of the equation (1) becomes greater than the first item. Thus, the voltage at the first node N.sub.1 becomes likewise a negative voltage.
Thus, the voltage V.sub.N1 at the first node N.sub.1 becomes a negative value due to the decrease of the positive power source voltage V.sub.CC or to the increase of the negative power source voltage V.sub.EE. At this time, since the output signal y, which is impressed upon the base of the first input transistor Q.sub.18, is at a level of the ground potential (GND), the collector-base junction of the first input transistor Q.sub.18 is biased in the forward direction and the first input transistor Q.sub.18 is driven into the saturation region.
On the other hand, when the third reference voltage V.sub.BB is impressed upon the base of the first input transistor Q.sub.18 and the output signal y of the ECL circuit l.sub.1 is impressed upon the base of the second input transistor Q.sub.17 in accordance with logic design of a data processing system, the voltage of the second node N.sub.2 becomes negative owing to the decrease of the positive power source voltage V.sub.CC or to the increase of the negative power source voltage V.sub.EE and the second input transistor Q.sub.17 is likewise driven into the saturation region.
In this manner, the saturation of the first input transistor Q.sub.18 or that of the second input transistor Q.sub.17, due to the fluctuation in the source voltage of the positive power source voltage V.sub.CC or the negative power source voltage V.sub.EE, markedly retards the switching speed of the output signal Y at the output terminal P.sub.14 of the signal level conversion circuit l.sub.2.
To cope with the problem, a method has conventionally been proposed which prevents the saturation of the input transistor by connecting a clamping element such as a Shottky barrier diode to the collector of the input transistors of the signal level conversion circuit, as disclosed in Japanese Patent Laid-Open No. 51-120143, for example.
Though the clamping element such as the Shottky barrier diode is capable of preventing the saturation of the input transistors, the switching speed of the output signal of the signal level conversion circuit is retarded due to the parasitic capacity inherent to the clamping element.
Referring again to the heretofore known signal level conversion circuit shown in FIG. 1, it has been clarified that when the absolute value .vertline.V.sub.EE .vertline. of the negative power source voltage -V.sub.EE becomes below about 4 V, the reference transistor Q.sub.16 as well as the current source transistor Q.sub.19 are brought into the OFF state. It has also been clarified that the collector outputs V.sub.N2, V.sub.N1 of the transistors Q.sub.17, Q.sub.18 are at high levels irrespective of the input conditions as represented by the power source voltage characteristic l.sub.71 in FIG. 7 whereby degradation of the characteristics of the output transistors Q.sub.32 and Q.sub.33 and their break-down occur.
This is because when the absolute value .vertline.V.sub.EE .vertline. of the negative power source voltage is not higher than about 4 V due to the base-emitter voltage of the transistor Q.sub.9, to the voltages of the diodes D.sub.3 and D.sub.4 in the forward direction, to the collector-base voltage of the current source transistor Q.sub.19 and to the voltage drop across the resistors R.sub.7 and R.sub.21, no current flows through them any longer.
SUMMARY OF THE INVENTION
It is therefore a first object of the present invention to provide a signal level conversion circuit having an expanded range of allowance for the fluctuation of power source voltages which is capable of high speed switching action to follow up the fluctuation of a negative power source voltage for a first circuit or that of a positive power source voltage for a second circuit.
It is a second object of the present invention to provide a level conversion circuit which improves a characteristic of a reduced power source voltage.
In a signal level conversion circuit l.sub.2 (shown in FIG. 2) in accordance with the fundamental principle of the present invention to accomplish the above-described first object, the value of a current I.sub.o flowing through a current source transistor Q.sub.19 connected to input transistors Q.sub.17 and Q.sub.18 depends upon both negative power source voltage V.sub.EE and positive power source voltage V.sub.CC. The value of the current I.sub.o flowing through the current source transistor Q.sub.19 is proportional to the difference of voltages between the negative power source voltage V.sub.EE and the positive power source voltage V.sub.CC. Accordingly, when the value of the positive power source voltage V.sub.CC decreases, for example, the voltage drop across load resistors R.sub.18 and R.sub.19 connected between the positive power source voltage V.sub.CC and collectors of input transistors Q.sub.17 and Q.sub.18 is reduced due to the decrease of the current flowing through the current source transistor Q.sub.19. Hence, the drop of the collector potentials of the input transistors Q.sub.17 and Q.sub.18 resulting from the decrease of the positive power source V.sub.CC is offset by the decrease of the voltage drop across the load resistors R.sub.18 and R.sub.19.
In the level conversion circuit (FIG. 8) in accordance with the fundamental principle of the present invention to accomplish the above-described second object, a bias voltage V.sub.N4 for a protection transistor Q.sub.12 and a bias voltage V.sub.N7 for a constant current transistor Q.sub.15 are formed on the basis of a voltage division output of a voltage division circuit 2 disposed between the positive power source voltage V.sub.CC and the negative power source voltage V.sub.EE.

BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram of the heretofore known circuit;
FIG. 2 is a circuit diagram of an embodiment of the present invention;
FIG. 3 is a block diagram of a MOS memory;
FIG. 4 is a circuit diagram of a memory cell and preamplifier;
FIG. 5 is a characteristic curve of the circuit of FIG. 2;
FIG. 6 is a waveform chart of the MOS memory circuit of FIG. 3;
FIG. 7 is a characteristic curve of the circuit of FIGS. 1 and 8; and
FIG. 8 is a circuit diagram of another embodiment of the present invention;

DESCRIPTION OF THE PREFERRED EMBODIMENT
Hereinafter, the preferred embodiments of the present invention will be explained in detail.
FIG. 2 is a circuit diagram showing the signal level conversion circuit l.sub.2 of an embodiment of the present invention together with the ECL circuit l.sub.1 and the N-MOS memory l.sub.3.
Though not limited in particular, the abovementioned ECL circuit l.sub.1 comprises a bias circuit consisting of resistors R.sub.1 -R.sub.3, diodes D.sub.1 and D.sub.2 and a transistor Q.sub.1 and a logic circuit consisting of resistors R.sub.4 -R.sub.6 and transistors Q.sub.2 -Q.sub.7 as shown in the drawing.
Input signals a-c from terminals P.sub.3 -P.sub.5 are impressed upon the bases of the transistors Q.sub.3 -Q.sub.5, respectively. At the emitter (output terminal P.sub.7) of the transistor Q.sub.7 is produced an output signal of the NOR logic y of the signals a-c.
One of power terminals P.sub.1 of the abovementioned ECL circuit l.sub.1 is connected to a ground potential point (GND) of the circuit and the other P.sub.2 is connected to a negative power terminal V.sub.EE of -5.2 V, for example. The input and outputs signals of the ECL circuit l.sub.1 are set to a high level of -0.89 V, for example, and to a low level of -1.69 V, for example, respectively.
The signal level conversion circuit l.sub.2 in accordance with the embodiment of the present invention is formed on one semiconductor substrate by a known monolithic semiconductor integrated circuit technique.
One of power terminals P.sub.8 of this signal level conversion circuit is connected to a positive power terminal V.sub.CC of 5 V, for example, the second P.sub.9, to the negative power terminal V.sub.EE and the third P.sub.10, to the ground potential point (GND).
The bias circuit 2 is especially connected between the positive power terminal V.sub.CC and the negative power terminal V.sub.EE in accordance with the principle of the present invention as shown in the drawing and operates on the voltage difference between the positive power source and the negative power source. The bias circuit 2 produces a bias voltage V.sub.BB which is at an almost intermediate level of the ECL signal level, e.g., -1.29 V, at the junction between the emitter of the transistor Q.sub.9 and the anode of the diode D.sub.3 and also produces a bias voltage V.sub.b2 which is lower than the low level of the ECL signal level, e.g., -1.69 V, at the junction between the cathode of the diode D.sub.4 and the collector of the transistor Q.sub.10. It also produces a bias voltage V.sub.b1 for a current source transistor Q.sub.19 at the junction between the emitter of the transistor Q.sub.10 and the resistor R.sub.6, and a bias voltage V.sub.b3 for the transistor Q.sub.11 at the junction between the resistor R.sub.9 and the resistor R.sub.10.
In the level conversion circuit l.sub.2, the transistor Q.sub.19 forms a current source transistor, the transistor Q.sub.18 forms a first input transistor and the transistor Q.sub.17 forms a second input transistor.
At its base, the abovementioned second input transistor Q.sub.17 receives the reference bias voltage V.sub.BB of the intermediate level of the ECL signal level from the constant voltage bias circuit 2 via terminals P.sub.13 and P.sub.12 while the transistor Q.sub.18 receives the output signal y from the abovementioned ECL circuit l.sub.l via the terminals P.sub.7 and P.sub.11. To these first and second input transistors Q.sub.18 and Q.sub.17 is connected a reference transistor Q.sub.16 so as to be capable of operating differentially. The bias voltage V.sub.b2 from the bias circuit 2 is applied to the base of this reference transistor Q.sub.16. Accordingly, when the output signal y of the abovementioned ECL circuit l.sub.1 is at high level, the transistor Q.sub.17 is in the OFF state while the transistor Q.sub.18 is in the ON state. On the contrary, when the output signal y of the ECL circuit l.sub.1 is at low level, the state of each transistor Q.sub.17, Q.sub.18 is reversed.
The collector of the first input transistor Q.sub.18 is connected to the positive power terminal V.sub.CC via a first load resistor R.sub.19 and the collector of the second input transistor Q.sub.17 is also connected to the positive power terminal V.sub.CC via a second load resistor R.sub.18.
When the transistor Q.sub.17 or Q.sub.18 is turned on, a current I.sub.o of the current source transistor Q.sub.19 flows through the resistor R.sub.18 or R.sub.19, thus generating a voltage drop at the resistor R.sub.18 or R.sub.19. As a result, a signal of the opposite phase is produced at the collector of each transistor Q.sub.17, Q.sub.18 in accordance with the input signal of the ECL level. In this case, it is possible to render the low level of the collector output signal of each transistor Q.sub.17, Q.sub.18 substantially equal to the ground potential (GND) such as +0.3 V, for example, by selecting suitable values for the resistors R.sub.18 and R.sub.19.
The collector output signals of the transistors Q.sub.17 and Q.sub.18 are respectively applied to the bases of cascaded output transistors Q.sub.21 and Q.sub.23 via emitter follower transistors Q.sub.20 and Q.sub.22. The output transistors Q.sub.21 and Q.sub.23 are operated in the opposite phases to one another by the collector outputs of the differential pair transistors Q.sub.17 and Q.sub.18. As a result, at the output terminal P.sub.14, there is produced an output signal Y which is converted into a positive voltage system in response to the input signal of the ECL level and is capable of sufficiently driving a heavy load such as a capacitive load.
The output signal Y of the signal level conversion circuit l.sub.2 substantially changes between the positive power source voltage V.sub.CC and the ground potential point (GND) and is impressed upon the input terminal P.sub.15 of the N channel MOS circuit l.sub.3. The N-MOS circuit l.sub.3 includes N-channel insulated gate field effect transistors Q.sub.23, Q.sub.24, Q.sub.25, Q.sub.26 and Q.sub.27. One of its power terminals P.sub.10 is connected to the positive power terminal of +5.0 V, for example, while the other power terminal P.sub.16 is connected to the ground potential point (GND).
In the bias circuit 2 in accordance with the principle of the present invention, resistors R.sub.25 and R.sub.13 are connected in series between the positive power terminal V.sub.CC and the negative power terminal V.sub.EE. The voltage produced at the junction of these resistors R.sub.25 and R.sub.13 is proportional to the difference of the voltage between the positive power voltage V.sub.CC and the negative power voltage V.sub.EE and determines the bias voltage V.sub.b1 to be impressed upon the base of the current source transistor Q.sub.19. Though the junction between the resistors R.sub.25 and R.sub.13 may be directly connected to the base of the current source transistor Q.sub.19, it is preferably connected to the base of the current source transistor Q.sub.19 via the base-emitter junction of the emitter follower transistor Q.sub.10. In a further preferred embodiment of the present invention, the diodes D.sub.5 and D.sub.6 are connected in series to the resistor R.sub.13 for the compensation of the temperature characteristic of the base-emitter junctions of the transistors Q.sub.10 and Q.sub.19.
In the preferred embodiment of the present invention, resistors R.sub.11 and R.sub.27 are cascaded between the ground potential point (GND) and the negative power terminal V.sub.EE in the bias circuit 2. The voltage produced at the junction between these resistors R.sub.11 and R.sub.27 is proportional to the power source voltage of the negative power voltage V.sub.EE and determines the reference bias voltage V.sub.BB as well as the bias voltage V.sub.b2.
Assume now that the output signal y at the output terminal P.sub.7 of the ECL circuit l.sub.1 is at a level approximate to the ground potential (GND). Since the bias voltage V.sub.b2 and the bias voltage V.sub.BB are impressed upon the base of the reference transistor Q.sub.16 and upon that of the second input transistor Q.sub.17, respectively, the first input transistor Q.sub.18 becomes conductive whereas the reference transistor Q.sub.16 and the second input transistor Q.sub.17 become non-conductive. Accordingly, the potential V.sub.N1 at the first node N.sub.1 where the first load resistor R.sub.19 is connected to the collector of the first input transistor Q.sub.18 is given by the following equation;
V.sub.N1 =V.sub.CC -R.sub.19 .multidot.I.sub.o (2)
On the other hand, the value of the current I.sub.o flowing through the current source transistor Q.sub.19 is especially rendered proportional to the voltage difference between the positive power source voltage V.sub.CC and the negative power source voltage V.sub.EE in accordance with the principle of the present invention.
Accordingly, when the negative power source voltage V.sub.EE is kept at a predetermined power source voltage value (e.g., -5.2 V) while the positive power source voltage V.sub.CC drops drastically from a predetermined power source voltage (e.g., +5.0 V) down to +3.0 V, for example, the value of the current I.sub.o flowing through the current source transistor Q.sub.19 drops drastically. For this reason, even when the power source voltage value of the positive power source voltage V.sub.CC drops drastically from the predetermined value, the first and second items of the right side of the abovementioned equation (2) become small values.
Assume now the case where the positive power source voltage V.sub.CC is kept at a predetermined power source voltage value (e.g., 5.0 V) while the negative power source voltage V.sub.EE changes drastically (from -5.2 V, for example) to -7.0 V, for example. In this case, in the heretofore known signal level conversion circuit l.sub.2 (in FIG. 1), the value of the current I.sub.o flowing through the current source transistor Q.sub.19 changes drastically depending exclusively upon the voltage value of the negative power source voltage V.sub.EE, whereas in the signal level conversion circuit l.sub.2 of the present invention (in FIG. 2), the value of the current I.sub.o flowing through the current source transistor Q.sub.19 is determined by the voltage difference between the positive power source voltage V.sub.CC and the negative power source voltage V.sub.EE. Accordingly, the change of the current I.sub.o due to the change of the negative power source voltage V.sub.EE becomes smaller than that in the prior art.
As described above, since the value of the current I.sub.o flowing through the current source transistor Q.sub.19 changes in proportion to the voltage difference between the positive power source voltage V.sub.CC and the negative power source voltage V.sub.EE in the present invention, the potential V.sub.N1 at the first node N.sub.1 does not much change with the change of the positive power source voltage V.sub.CC or that of the negative power source voltage V.sub.EE and is kept substantially at a constant level.
On the other hand, it has become obvious that when the positive power source voltage and the negative power source voltage to be used change or when the sequence of the feed changes in making use of the signal level conversion circuit, signals of undesirable levels are applied to the N-MOS memory so that the memory tends to operate erroneously.
As will be explained next, the signal level conversion circuit l.sub.2 (in FIG. 2) in accordance with the embodiment of the present invention operates in such a manner as to keep the output signal Y of the push-pull output circuit (Q.sub.21, Q.sub.23) at a preferable high level even in such cases where the power source voltages V.sub.CC and V.sub.EE fluctuate, the feed sequence of the voltages V.sub.CC and V.sub.EE changes at the start of the feed of power and the input terminals P.sub.11 and P.sub.12 undesirably open.
The reason why the signals of undesirable levels are applied to the N-MOS memory due to the change in the negative power source voltage V.sub.EE in the signal level conversion circuit l.sub.2 (in FIG. 2) will be discussed. The reason resides in the fact that the negative power source voltage has such a critical value V.sub.EE (crit) that when the power source voltage decreases, the bias current flowing through the series current path consisting of the transistor Q.sub.9, the diodes D.sub.3 and D.sub.4, the transistor Q.sub.10 and the resistors R.sub.9 and R.sub.10 of the constant voltage bias circuit 2 becomes substantially zero. When the absolute value of the negative power source voltage V.sub.EE becomes lower than this critical value V.sub.EE (crit), the bias voltage V.sub.b1 obtained from the emitter of the transistor Q.sub.10 becomes substantially zero and the current source transistor Q.sub.19 is eventually cut off.
The cut-off state of the constant current transistor Q.sub.19 brings both differential pair transistors Q.sub.17 and Q.sub.18 into the OFF state.
When the switching transistor Q.sub.15 is not disposed in the V.sub.EE detection circuit 3 and in the switching circuit 4, both collector outputs of the differential pair transistors Q.sub.17 and Q.sub.18 become simultaneously high level upon turn-off of both transistors whereby all of the emitter follower transistors Q.sub.20, Q.sub.22 and the output transistors Q.sub.23, Q.sub.21 of the push-pull circuit of the signal level conversion circuit l.sub.2 (in FIG. 2) are turned on. This state not only produces, as the output signal Y, the low level (ground potential) causing the erroneous operation of the N-MOS memory from the output terminal P.sub.14 but also allows a large current to simultaneously flow through the output transistors Q.sub.23 and Q.sub.21 and to eventually break down these transistors.
By contrast, in accordance with the embodiment of the present invention, there are provided the V.sub.EE detection control circuit 3 and the switching circuit 4. More particularly, the base of the detection transistor Q.sub.11 in the V.sub.EE detection circuit 3 is connected to the junction between the resistors R.sub.9 and R.sub.10 and is supplied with a bias voltage V.sub.b3 which is smaller than the bias voltage V.sub.b1 obtained from the emitter of the transistor Q.sub.10. Accordingly, the transistor Q.sub.11 of the V.sub.EE detection control circuit 3 is cut off before the current source transistor Q.sub.19 is cut off when the absolute value of the negative power source voltage V.sub.EE becomes smaller than the abovementioned critical value V.sub.EE (crit). Hence, the collector output of the transistor Q.sub.11 becomes high level (positive power source voltage V.sub.CC) and the transistor Q.sub.15 of the switching circuit 4 is in the ON state. Since the collector of the transistor Q.sub.15 is connected to the base of the emitter follower transistor Q.sub.20 of the push-pull output circuit, the emitter follower transistor Q.sub.20 as well as the output transistor Q.sub.21 become in the OFF state as soon as the transistor Q.sub.15 is turned on. As the output transistor Q.sub.21 is in the OFF state, both emitter follower transistor Q.sub.22 and output transistor Q.sub.23 become ON whereby the output signal Y of the high level is obtained from the output terminal P.sub.14 and the output transistors Q.sub.21 and Q.sub.23 can be protected from the break-down.
Accordingly, in the V.sub.EE detection control circuit 3 and in the switching circuit 4, the negative power source voltage V.sub.EE changes from the right-hand portion to the left as viewed from the line l.sub.51 in FIG. 5 and when it exceeds the line l.sub.51, it changes compulsively the output signal Y of the output terminal P.sub.14 to the high level. The value of the positive power source voltage V.sub.CC required for the V.sub.EE detection control circuit 3 and the switching circuit 4 to accomplish this compulsive circuit operation is a minimum value required for the transistor Q.sub.15 to be brought into the ON state by means of the current flowing through the base of the transistor Q.sub.15 of the switching circuit 4 through the resistor R.sub.26.
On the other hand, voltages of suitable values are applied to the positive power source voltage V.sub.CC and to the negative power source voltage V.sub.EE, respectively. When the output signal y of the ECL circuit l.sub.1 is at low level, one transistor Q.sub.17 of the differential pair transistors Q.sub.17 and Q.sub.18 is in the ON state and its collector output is at low level while the other transistor Q.sub.18 is in the OFF state. In this case, the low level collector output of the transistor Q.sub.17 brings the transistors Q.sub.20 and Q.sub.21 of the push-pull output circuit into the OFF state while the high level collector output of the transistor Q.sub.18 brings the transistors Q.sub.22 and Q.sub.23 of the push-pull output circuit into the ON state.
However, there is a possibility that even when the output signal y of the ECL circuit l.sub.1 is at low level and the transistor Q.sub.18 is in the OFF state with the transistor Q.sub.17 in the ON state, the low level collector output of the transistor Q.sub.17 changes to follow up the change in the positive power source voltage V.sub.CC or in the negative power source voltage V.sub.EE.
In other words, if the V.sub.CC .multidot.V.sub.EE detector circuit 1 and the switching circuit 4 are not provided, the voltage level of the low level collector output of the transistor Q.sub.17, which is in the ON state, becomes (V.sub.N2 =V.sub.CC -R.sub.18 .multidot.I.sub.o) with I.sub.o being a constant current flowing through the current source transistor Q.sub.19. Accordingly, the voltage level of the collector output of the transistor Q.sub.17 changes from the low level towards the high level in accordance with the rise of the absolute value of the positive power source voltage V.sub.CC or with the decrease of the constant current I.sub.o. The decrease of the constant current I.sub.o flowing through the current source transistor Q.sub.19 is generated by the decrease of the absolute value of the negative power source voltage V.sub.EE. When the voltage level of the low level collector output of the transistor Q.sub.17 expressed by (V.sub.N2 =V.sub.CC -R.sub.18 .multidot.I.sub.o) changes towards the high level due to the rise of the absolute value of the positive power source voltage V.sub.CC or to the decrease of the absolute value of the negative power source voltage V.sub.EE, the transistors Q.sub.20 and Q.sub.21 of the output push-pull circuit become in the ON state. At this time, the other Q.sub.18 of the differential pair transistors Q.sub.17 and Q.sub.18 is in the OFF state and the transistors Q.sub.22 and Q.sub.23 of the output push-pull circuit have already been in the ON state. Hence, there occurs a possibility that the output transistors Q.sub.23 and Q.sub.21 are broken down due to a penetrating current flowing their series circuit and a low level output signal Y is undesirably generated at the output terminal P.sub.14 as the output transistor Q.sub.21 is in the ON state.
By contrast, in accordance with the embodiment l.sub.2 (in FIG. 2) of the present invention, there are provided the V.sub.CC .multidot.V.sub.EE detection circuit 1 and the switching circuit 4. Especially, the base of the detection transistor Q.sub.8 in the V.sub.CC .multidot.V.sub.EE detection circuit 1 is connected to the positive power source voltage V.sub.CC via the resistor R.sub.14 and the emitter is connected to a common junction of the two cascaded resistors R.sub.7 and R.sub.25 between the positive power source voltage V.sub.CC and the negative power source voltage V.sub.EE with the collector connected to the base of the emitter follower transistor Q.sub.12. The emitter of this transistor Q.sub.12 is connected to a circuit network consisting of the resistors R.sub.16, R.sub.17 and the transistor Q.sub.13 and further to the base of the switching transistor Q.sub.14.
Accordingly, when the rise of the absolute value of the positive power source voltage V.sub.CC or the drop of the absolute value of the negative power source voltage V.sub.EE exceeds a detection level that is determined by the resistors R.sub.7, R.sub.25, R.sub.13, the diodes D.sub.5, D.sub.6 and so forth, the emitter voltage of this detection transistor Q.sub.8 rises. As a result, a sufficient base current is fed to the emitter follower transistor Q.sub.12 via a Shottky diode interposed between the collector and base of the detection transistor Q.sub.8, whereby the switching transistor Q.sub.14 is turned ON. As the transistor Q.sub.14 is thus in the ON state, it protects the output transistors Q.sub.21 and Q.sub.23 from break-down in the same way as the switching transistor Q.sub.15 and changes the output signal Y at the output terminal P.sub.14 to the high level.
In FIG. 5, the range above the line l.sub.52 represents a range of the power source voltage in which the transistor Q.sub.14 of the abovementioned switching circuit 4 is in the ON state. In other words, when the absolute value of the positive power source voltage rises or the absolute value of the negative power source voltage drops, the power source voltage value approaches from the range below the line l.sub.52 towards the upper range so that when the power source voltage exceeds the line l.sub.52 before the transistors Q.sub.20 and Q.sub.21 change undesirably from the OFF state to the ON state, the transistor Q.sub.14 of the switching circuit 4 becomes ON. It is thus possible to keep the transistors Q.sub.20 and Q.sub.21 of the output push-pull circuit in the OFF state.
The reference transistor Q.sub.16 is employed in order to compulsively keep the signal of the output terminal P.sub.14 at the high level when the terminals P.sub.11 and P.sub.12 are undesirably opened. Namely, when the terminals P.sub.11 and P.sub.12 are opened, the transistors Q.sub.17 and Q.sub.18 become OFF since the base current becomes zero (O). The emitter of the transistor Q.sub.16 is commonly connected to those of the transistors Q.sub.17 and Q.sub.18 and forms a current switch together with these transistors Q.sub.17 and Q.sub.18. Hence, when the transistors Q.sub.17 and Q.sub.18 become OFF, the reference transistor Q.sub.16 becomes ON. As a result, the constant current I.sub.o of the current source transistor Q.sub.19 flows through the resistor R.sub.18 via the transistor Q.sub.16. Due to the voltage drop of the resistor R.sub.18, the transistors Q.sub.20 and Q.sub.21 become OFF with the consequence that the signal of the output terminal P.sub.14 becomes high level.
As described above, the transistor Q.sub.16 is arranged in such a manner that its base receives from the constant voltage bias circuit a bias voltage of a lower voltage level than the ECL signal level. Consequently, the transistor Q.sub.16 is in the OFF state while the ECL level signal and the signal of the aforementioned intermediate level are applied to the terminals P.sub.11 and P.sub.12.
Heretofore known N-MOS memories may be used in the present invention without any restriction in particular. As shown in the block diagram of FIG. 3, for example, the N-MOS memory consists of a clock signal generation circuit 6 which receives a row address strobe signal RAS and generates a clock signal for a row address data input; a clock signal generation circuit 8 which receives the row address strobe signal RAS and a column address strobe signal CAS through a gate circuit 7 and generates a clock signal for the column address data input; a control circuit 9 which receives the clock signals from the clock signal generating circuits 6 and 8 and controls an address buffer circuit 13 and an address decoder circuit 14; a buffer circuit 10 which receives a chip selection signal CS; a gate circuit 12 which receives the output signals of the clock signal generation circuit 8 and the buffer circuit 10 and produces enable signals to the address decoder circuit 14 and to a data buffer circuit 17; a gate circuit 11 which receives a write control signal WRITE and the output signal of the gate circuit 7 and controls a write clock signal generation circuit 15; a data input buffer circuit 16 which is controlled by the output signal of the write clock signal generation circuit 15; memory arrays 18 and 18'; preamplifier groups 19; and an input-output data selection circuit 20.
FIG. 4 shows an example of the memory cell and preamplifier. As shown in the drawing, the memory cell comprises, for example, an N channel insulated gate field effect transistor (hereinafter called "MOSFET") Q.sub.100 having its gate connected to the word line W.sub.o of the address decoder circuit 14, and a data storage capacitor C.sub.100. The preamplifier comprises MOSFETs Q.sub.102 and Q.sub.103 for receiving the clock signal .phi..sub.1 and MOSFET Q.sub.104 for receiving the clock signal .phi..sub.0 and MOSFETs Q.sub.105 and Q.sub.106 having their gates and drains mutually connected crosswise. To the data line D.sub.1 of the preamplifier is connected a dummy cell (Q.sub.107, C.sub.107) for providing a reference potential to the data line D.sub.1, said reference potential determined when a memory to be connected to the data line D.sub.1 is selected. To the data line D.sub.1 is likewise connected a dummy cell (Q.sub.101, C.sub.101).
Generally, the N-MOS memory is equipped at its input terminals with an inverter having a bootstrap function as a buffer circuit and receives the low level of the input signal as a data signal, for the reason to be later explained.
Though not restrictive, the input buffer circuit 5 of FIG. 3 comprises the MOSFETs Q.sub.23 -Q.sub.27 and the capacitor C.sub.1 like the circuit 5 of FIG. 2, for example. The MOSFETs Q.sub.23 -Q.sub.25 and the capacitor C.sub.1 together form the inverter circuit while the MOSFETs Q.sub.26 and Q.sub.27 together form the push-pull circuit.
When the signal of the terminal P.sub.15 is at high level, the MOSFET Q.sub.23 is turned on and hence, the output of the inverter circuit is at low level substantially equal to the ground potential. At this time, the capacitor C.sub.1 is charged to a value [V.sub.CC -V.sub.th ] which is the balance obtained by subtracting the threshold voltage V.sub.th of the diode-connected MOSFET Q.sub.24 from the approximate power source voltage V.sub.CC.
When the signal of the terminal P.sub.15 changes from the abovementioned high level to low level, the MOSFET Q.sub.23 is in the OFF state so that the output signal level of the inverter circuit starts rising. In this case, since the capacitor C.sub.1 has in advance been charged near the above-mentioned value [V.sub.CC -V.sub.th ], the gate voltage of the MOSFET Q.sub.25 becomes sufficiently high. As a result, the ON-resistance of the MOSFET Q.sub.25 becomes sufficiently small. As the ON-resistance of the MOSFET Q.sub.25 becomes sufficiently low, the stray capacitance (not shown) at the output side of the inverter circuit is rapidly charged and the output signal of the inverter circuit rises at a high speed. When the gate voltage of the MOSFET Q.sub.25 becomes higher than the power source voltage V.sub.CC owing to the bootstrap effect of the capacitor C.sub.1, the output signal level of the inverter circuit rises close to the power source voltage V.sub.CC, although the MOSFET Q.sub.25 has the threshold voltage.
While a steady low level signal is being applied to the terminal P.sub.15, the stored charge of the capacitor C.sub.1 is reduced by a leakage current and the output voltage of the inverter circuit rises only to a value [V.sub.CC -2V.sub.th ] which is the difference obtained by subtracting the threshold voltage V.sub.th of the MOSFET Q.sub.24 and that of the Q.sub.25 from the power source voltage V.sub.CC. When the signal of the terminal P.sub.15 is changed from the low level to the high level, therefore, the amplitude of the output signal of the inverter circuit becomes small so that the amplitude and the changing speed of the output circuit (Q.sub.26, Q.sub.27) become small correspondingly.
In order to increase the operation speed, the MOS memory is allowed to receive such signals that are at high level H at the time of non-operation and are at low level L at the time of operation as represented by A and B in FIG. 6.
In FIG. 6, A represents the change of the row address strobe signal RAS and B represents the change of the column address strobe signal CAS. Symbol C represents the change of the output signal of the inverter circuit (in FIG. 2) to receive the abovementioned signal RAS. Dash line a represents the change of the gate potential of the MOSFET Q.sub.25 at this time.
As described above, the MOS memory driving circuit l.sub.2 of the embodiment of the invention shown in FIG. 2 is so constructed as to generate the high level signal when it is not expected to operate normally due to the fluctuation of the power source voltage V.sub.CC .multidot.V.sub.EE, change of the mode of feeding the power source voltages V.sub.CC and V.sub.EE, the state of opening of the input terminals P.sub.11 and P.sub.12, and so forth. Hence, the MOS memory is prevented from operating erroneously.
FIG. 8 shows the signal level conversion circuit in accordance with the embodiment of the present invention, which accomplishes the second object of the invention. This circuit is constructed in the monolithic semiconductor integrated circuit (IC) by the known technique and P.sub.1 through P.sub.7 are employed as external terminals of the IC.
To the terminal P.sub.1 is applied a positive power source voltage V.sub.CC of +5 V, for example, while a negative power source voltage of -5.2 V, for example, is applied to the terminal P.sub.7. The terminal P.sub.3 is kept at the ground potential (GND) of the circuit.
In the drawing, the portion encompassed by two-dot chain line 1 forms a level conversion portion and the portions encompassed by two-dot chain lines 2 and 3 form bias portions, respectively.
The bias portion 2 consists of resistors R.sub.7 -R.sub.10, a transistor Q.sub.4 and diodes D.sub.11 -D.sub.13, and is interposed between the abovementioned terminals P.sub.1 and P.sub.7. Upon receiving the positive power source voltage V.sub.CC and the negative power source voltage V.sub.EE, the bias portion 2 generates bias voltages at nodes N.sub.3 -N.sub.5, respectively.
The bias voltage V.sub.N3 at the node N.sub.3 is utilized as a bias voltage for a power source voltage detection portion 5. The voltage value of this bias voltage V.sub.N3 is set such that it is lower than 2 V.sub.BE, the sum of the base-emitter voltage V.sub.BE in the forward direction of a transistor Q.sub.6 and that of a transistor Q.sub.8 of the power source voltage detection portion 5 when the power source voltages V.sub.CC and V.sub.EE are within the normal ranges. On the other hand, the bias voltage V.sub.N3 is set such that it becomes higher than 2 V.sub.BE when the positive power source voltage V.sub.CC increases from the normal value and when the absolute value of the negative power source voltage V.sub.EE decreases from the normal value.
The bias voltage V.sub.N4 is utilized as a bias voltage for a transistor Q.sub.12 of the level conversion portion 1. This bias voltage V.sub.N4 is set such that it is at a lower level than the level of the ECL signal applied to the external terminal P.sub.4 or P.sub.5 of the IC.
The bias voltage V.sub.N5 at the node N.sub.5 is utilized as a bias voltage for a transistor Q.sub.10 of the bias portion 3.
The bias portion 3 consists of resistors R.sub.15 through R.sub.17, diodes D.sub.14 and D.sub.15 and transistors Q.sub.9 and Q.sub.10 and is interposed between the ground (GND) and the negative power source terminal P.sub.7 of the circuit. This bias portion 3 produces bias voltages V.sub.B and V.sub.N7 at the nodes N.sub.6 and N.sub.7, respectively.
The bias voltage V.sub.B at the node N.sub.6 is set to the intermediate level of the level of the ECL signal. When the high level of the ECL signal is -0.89 V with the low level being -1.69 V, the reference bias voltage V.sub.B at the node N.sub.6 is set to -1.29 V by selecting suitable values for the resistors R.sub.15 and R.sub.16.
The bias voltage V.sub.N7 at the node N.sub.7 is utilized as a bias voltage for a current source transistor Q.sub.15 of the level conversion portion 1.
The level conversion portion 1 consists of the above-mentioned current source transistor Q.sub.15 having an emitter resistor R.sub.24, differential pair transistors Q.sub.13 and Q.sub.14 with their respective collector load resistors R.sub.19 and R.sub.20, transistors Q.sub.16 -Q.sub.19 of a single end push-pull construction in the Darlington arrangement and resistors R.sub.21 -R.sub.23, and is interposed between the power terminals P.sub.1 and P.sub.7.
Though not restrictive, the output signal A from an ECL circuit (not shown) is applied to the terminal P.sub.4 while the reference bias voltage V.sub.B is fed to the terminal P.sub.5 from the bias portion P.sub.3 via the terminal P.sub.6 by the connection of the terminals P.sub.5 and P.sub.6 outside the IC as shown in the drawing.
Consequently, the abovementioned differential pair transistors Q.sub.13 and Q.sub.14 perform the differential operation in accordance with the ECL signal A supplied to the terminal P.sub.4.
Namely, when the ECL signal A is at low level, the transistor Q.sub.13 becomes conductive and the transistor Q.sub.14, non-conductive. At this time a current flows from the resistor R.sub.19 via the transistor Q.sub.13 to the current source transistor Q.sub.15. The potential V.sub.N2 at the node N.sub.2 is substantially at the ground potential (GND) e.g., +0.3 V, and the level of the potential at the node N.sub.2 is at low level as the resistance of the resistor R.sub.19 and the current value of the current flowing through the current source transistor Q.sub.15 are suitably selected. On the other hand, as one Q.sub.14 of the differential pair transistors Q.sub.13 and Q.sub.14 becomes non-conductive, the potential V.sub.N1 at the node N.sub.1 is substantially equal to the positive power source voltage V.sub.CC and the level of the potential at the node N.sub.1 is at high level.
When the level of the potential at the node N.sub.2 becomes low level, the Darlington-connected transistors Q.sub.18 and Q.sub.19 become non-conductive. When the level of the potential at the node N.sub.1 becomes high level, the Darlington-connected transistors Q.sub.16 and Q.sub.17 become conductive. As a result, a high level signal having a voltage value approximate to [V.sub.CC -2.multidot.V.sub.EE ] is generated at the output terminal P.sub.2.
On the contrary, when the ECL signal A is at high level, the state of operation of the differential pair transistors Q.sub.13 and Q.sub.14 is reversed to the above. In other words, the potential V.sub.N1 at the node N.sub.1 is made substantially equal to the ground potential (GND) by suitably selecting in advance the resistance of the resistor R.sub.20 and the current value of the current flowing through the current source transistor Q.sub.15. At this time, since the level of the potential at the node N.sub.2 is at high level, the Darlington-connected transistors Q.sub.18 and Q.sub.19 become conductive, while the Darlington-connected transistors Q.sub.16 and Q.sub.17 become non-conductive as the level of the potential at the node N.sub.1 is at low level. In consequence, a low level signal substantially equal to the ground potential (GND) is produced at the output terminal P.sub.2.
The abovementioned level conversion portion 1 drives the transistors Q.sub.16, Q.sub.17, Q.sub.18 and Q.sub.19 of the push-pull construction by means of the differential outputs at the nodes N.sub.1 and N.sub.2, thereby ensuring the high speed operation even if considerable stray capacitance (not shown) exists at each circuit point. Unlike the abovementioned circuit construction, there is a method which employs a phase split transistor such as one used in the heretofore known TTL circuit and derives signals of opposite phases to each other from the collector and emitter of the phase split transistor. In accordance with this method, however, the resistance values of the collector- and emitter-load resistors must be made relatively small in order to enable the high speed operation. For this reason, the power consumption increases especially at the time of the low level signal. In the level conversion portion 1 shown in FIG. 8, on the other hand, it is possible circuit-wise to eliminate such increase of the power consumption.
In the circuit of this embodiment (FIG. 8), the bias portion 2 is interposed electrically between the positive power source voltage V.sub.CC and the negative power source voltage -V.sub.EE. The bias portion 2 comprises a voltage division circuit consisting of the resistors R.sub.7 and R.sub.8, the diodes D.sub.11 -D.sub.13 and the resistor R.sub.9, and an emitter follower circuit consisting of the transistor Q.sub.4 and the resistor R.sub.10. The bias portion 2 generates a bias voltage V.sub.N4 for the protection transistor Q.sub.12 and a bias voltage V.sub.N5 for the transistor Q.sub.10 that drives the current source transistor Q.sub.15. Accordingly, even when the absolute value .vertline.V.sub.EE .vertline. of the negative power source voltage -V.sub.EE decreases below about 4 V, it never happens that the protection transistor Q.sub.12 and the constant current transistor Q.sub.15 are turned off. As represented by characteristics l.sub.72 in FIG. 7, for example, even when the negative power source voltage -V.sub.EE approaches the ground potential (GND), both transistors Q.sub.12 and Q.sub.15 are never turned off. In consequence, the margin of a reduced voltage of the protection circuit with respect to the power source voltage -V.sub.EE can be expanded and circuit design can be markedly simplified.
However, even when the protection transistor Q.sub.12 and the differential transistor Q.sub.14 are in the ON state, the output voltage V.sub.N1 at the node N.sub.1 rises as represented by the characteristic l.sub.72 in FIG. 7 if the absolute value .vertline.V.sub.EE .vertline. of the power source voltage -V.sub.EE drops and approaches the ground potential (GND). If the power source voltage detection portion 5 is not connected at this time, the transistors Q.sub.16 and Q.sub.17 are sometimes turned on.
For, in the circuit shown in FIG. 8, when the absolute value .vertline.V.sub.EE .vertline. of the negative power source voltage -V.sub.EE becomes a small voltage value, a sufficient bias voltage is no longer fed to the transistor Q.sub.10 of the bias portion 3 with the consequence that the emitter output current of the abovementioned transistor Q.sub.10 decreases and the collector current of the current source transistor Q.sub.15 of the level conversion portion 1 decreases in the corresponding manner.
Assume, for example, that one Q.sub.13 of the differential pair transistors Q.sub.13 and Q.sub.14 of the level conversion portion 1 is in the ON state in response to the low level signal of the ECL level of the input A. In this case, the voltage drop through the resistor R.sub.19 decreases to correspond to the decrease in the collector current of the current source transistor Q.sub.15. As a result, the potential of the low level signal V.sub.N2 at the node N.sub.2 rises and the transistors Q.sub.18 and Q.sub.19 become conductive correspondingly. Hence, the potential level at the output terminal P.sub.2 is caused to lower towards an undesirably low level.
On the contrary, if the other transistor Q.sub.14 of the differential pair transistors Q.sub.13 and Q.sub.14 is brought into the ON state by the high level signal of the input A or if the protection transistor Q.sub.12 is in the ON state due to the opening of the input terminals P.sub.4 and P.sub.5, the voltage drop through the resistor R.sub.20 decreases in response to the decrease in the collector current of the current source transistor Q.sub.15 with the consequence that the potential V.sub.N1 of the low level signal at the node N.sub.1 rises and the transistors Q.sub.16 and Q.sub.17 become conductive correspondingly. As a result, the level of the potential at the output terminal P.sub.2 is caused to rise towards an undesirably high level.
Further, in the circuit of this embodiment (FIG. 8), if the positive power source voltage V.sub.CC rises beyond a predetermined normal range while the power source voltage detection portion 5 is not connected, the circuits such as the TTL circuit and the N-MOS circuit do not operate, or operate erroneously, at times. In other words, if the positive power source voltage V.sub.CC rises while deviating from the predetermined normal range, the potential level at both nodes N.sub.1 and N.sub.2 become high levels at times. This is because the value of the voltage drop at the resistor R.sub.19 or R.sub.20 is substantially set to a predetermined value that is determined by the constant current of the current source transistor Q.sub.15. Namely, when the input signal to the input A is at low level, the low level signal potential V.sub.N2 at the node N.sub.2 increases with the increase of the power source voltage V.sub.CC for the abovementioned reason. As a result, the transistors Q.sub.18 and Q.sub.19, that should be in the OFF state, start becoming conductive along with the increase of the potential V.sub.N2 at the node N.sub.2. Hence, the potential level at the output terminal P.sub.2 is caused to lower towards an undesirably low level.
On the other hand, the high level signal potential produced at the output terminal P.sub.2 is determined in accordance with the positive power source voltage V.sub.CC. If the positive power source voltage V.sub.CC drops from the predetermined normal range, the high level of the signal produced at the terminal P.sub.2 can not be regarded as a definitely high level with respect to the TTL circuit and to the N-MOS circuit.
When the signal at the terminal P.sub.2 is at an undesirable level due to the rise or fall of the positive power source voltage V.sub.CC as described above, the TTL circuit and the N-MOS circuit that receive the signal at the terminal P.sub.2 do not operate or operate erroneously.
Further, in the embodiment of the invention (FIG. 8), if the power source voltage detection portion 5 is not connected, the level of the signals at the nodes N.sub.1 and N.sub.2 become simultaneously high level at times when the positive power source voltage V.sub.CC and the negative power source voltage -V.sub.EE are applied. In other words, the time required for a voltage to reach a normal value from making of the positive power source is different from that of the negative power source depending upon the circuit constructions of the two circuits receiving the positive and negative power source voltages, respectively. If making of the negative power source voltage is delayed substantially as compared with that of the positive power source voltage, the signal levels of the nodes N.sub.1 and N.sub.2 become high level substantially simultaneously within this delay time.
As described above, in the circuit of this embodiment (FIG. 8), if the power source detection portion 5 is not connected, the signal levels at the nodes N.sub.1 and N.sub.2 sometimes become high level substantially simultaneously owing to the difficiency of the negative power source voltage V.sub.EE or to the excess of the positive power source or in accordance with the sequence of the feed of the two power sources. In consequence, the signal level at the output terminal P.sub.2 is changed undesirably and the push-pull output transistors Q.sub.17 and Q.sub.19 cascaded between the positive power terminal P.sub.1 and the ground terminal P.sub.3 are simultaneously turned on. When both output transistors Q.sub.17 and Q.sub.19 are simultaneously turned on, a penetrating current flows from the power source V.sub.CC to the output transistors Q.sub.17 and Q.sub.19, which penetrating current causes degradation or break-down of these transistors Q.sub.17 and Q.sub.19.
In order to prevent the degradation or break-down of the output transistors Q.sub.17 and Q.sub.19, it is theoretically possible to reduce the penetrating current by interposing a current limiting resistor between the cascade line of the output transistors Q.sub.17 and Q.sub.19. In accordance with this method, however, the output current at the output terminal P.sub.2 is restricted by the current limiting resistor even when the circuit operates normally. Hence, when the capacitive load is connected to the output terminal P.sub.2, for example, it is difficult to supply the capacitive load with signals that vary at a high speed.
In accordance with the embodiment of the invention (FIG. 8), however, it is possible to prevent the undesirable change of the output signal level at the output terminal P.sub.2 as well as the occurrence of the penetrating current without using the current limiting resistor that would otherwise cause the abovementioned problem, by means of its power source voltage detection portion 5.
As shown in FIG. 8, this power source voltage detection portion 5 consists of resistors R.sub.11 -R.sub.13 and transistors Q.sub.5 -Q.sub.8. As the power source voltage detection portion 5 is connected as shown in the drawing, the transistors Q.sub.6 and Q.sub.8 are turned on when the value of the bias voltage V.sub.N3 at the node N.sub.3 of the aforementioned bias portion 2 becomes greater than the sum 2V.sub.BE of the base-emitter voltages of the transistors Q.sub.6 and Q.sub.8 in the forward directon, and are turned off when the former is smaller than the latter.
As described above, the value of the bias voltage V.sub.N3 at the node N.sub.3 is smaller than 2V.sub.BE when both positive and negative power source voltages are within suitable ranges, respectively. Under this state the transistor Q.sub.8 is in the OFF state and does not perform any function to restrict the signals that appear at the node N.sub.1 of the level conversion portion 1.
When the positive power source voltage V.sub.CC becomes excessively great or when the absolute value .vertline.V.sub.EE .vertline. of the negative power source voltage -V.sub.EE becomes excessively small, the bias voltage V.sub.N3 at the node N.sub.3 becomes greater than 2V.sub.BE, and the transistor Q.sub.8 is turned on in response thereto.
The potential of the level at the node N.sub.1 of the level conversion portion 1 is rendered substantially equal to the low level of the ground potential (GND) by the transistor Q.sub.8 which is in the ON state as described above. As a result, the potential levels at the nodes N.sub.1 and N.sub.2 are prevented from becoming high levels simultaneously.
The present invention is not particularly restricted to the above-mentioned embodiment (FIG. 8), and the definite construction of the bias circuits for the protection transistor Q.sub.12 and the current source transistor Q.sub.15 may be modified variously. Other protection circuits such as the power source voltage detection circuit may also be optional.
The present invention can be widely used for the circuit which converts a signal of one polarity to a signal of the other polarity.

Number	Date	Country	Kind
54-81350	Jun 1979	JPX
54-111776	Sep 1979	JPX

Number	Name	Date
3590274	Marley	Jun 1971
3766406	Bryant et al.	Oct 1973
4249091	Yamagiwa	Feb 1981

Level conversion circuit

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Non-Patent Literature Citations (2)

Entry
J. C. Froment et al., "ECL to TTL Translator Driver", IBM Technical Disclosure Bulletin, vol. 21, No. 10, Mar. 1979, pp. 4074-4075.
Patents Abstracts of Japan, vol. 2, No. 104, 26.08.78, p. 5430e78.