Patent Grant
12033582
This application claims the benefit of priority to the Korean Patent Application No. 10-2021-0194725, filed in the Republic of Korea on Dec. 31, 2021, the entire contents of which are hereby expressly incorporated by reference into the present application.
The present invention relates to a level shifter and a display device including the same.
With the development of information technology, the market for display devices, which are connection media between users and information, is growing. Accordingly, display devices, such as a light emitting display (LED) device, a quantum dot display (QDD) device, and a liquid crystal display (LCD) device, are increasingly being used.
The display devices described above include a display panel including sub-pixels, drivers that output driving signals for driving the display panel, a power supply that generates power to be supplied to the display panel or the driver, and the like.
In the aforementioned display devices, when driving signals, for example, a scan signal and a data signal, are supplied to the sub-pixels formed in the display panel, selected sub-pixels transmit light or directly emit light, thereby displaying an image.
However, as display devices become larger and have higher resolution and as smaller and smaller bezel areas are desired by users, input terminals and signal lines of various components (e.g., a level shifter) become more numerous and take up space, which limits design freedom and increases manufacturing costs.
An object of the present invention is to increase a degree of freedom in design at the time of manufacturing a display device by reducing the number of input terminals and signal lines required for a circuit configuration based on a level shifter capable of self-generating mode signals internally for converting or adjusted driving modes of the level shifter by itself.
An aspect of the present invention is to provide a display device include a timing controller configured to output a first clock signal and a second clock signal; a level shifter including a signal input circuit configured to receive the first clock signal and the second clock signal from the timing controller, a driving mode conversion circuit configured to self-generate one or more mode signals based on the first clock signal and the second clock signal for adjusting a driving mode of the level shifter, and a signal output circuit configured to generate a plurality of scan clock signals based on the one or more mode signals, the first clock signal and the second clock signal; a shift register configured to generate a scan signal based on the plurality of scan clock signals output from the level shifter; and a display panel configured to display an image based on the scan signal output from the shift register, in which the level shifter is configured to in response to a width of a pulse of the first clock signal being greater than a threshold value, sequentially output a pulse for each of the plurality of scan clock signals.
According to an aspect of the present invention, the one or more mode signals are not generated based on any other signal externally input to the level shifter other than the first clock signal and the second clock signal.
According to another aspect of the present invention, the plurality of scan clock signals are shifted and do not overlap with each other.
According to an aspect of the present invention, the level shifter is configured to in response to a width of a pulse of the first clock signal being less than a threshold value, output two successive pulses for one of the plurality of scan clock signals.
According to another aspect of the present invention, other scan clock signals among the plurality of scan clock signals, which are different than the one of the plurality of scan clock signals, do not include any pulse generated between the two successive pulses.
According to an aspect of the present invention, the level shifter is configured to in response to a pulse of the first clock signal overlapping with a pulse of the second clock signal, perform a mute operation for one of the plurality of scan clock signals so that no pulse is output for the one of the plurality of scan clock signals when the pulse of the first clock signal overlaps with the pulse of the second clock signal.
According to another aspect of the present invention, the level shifter is configured to in response to the pulse of the first clock signal not overlapping with the pulse of the second clock signal, omit the mute operation and output a pulse for one of the plurality of scan clock signals that overlaps with both of the pulse of the first clock signal and the pulse of the second clock signal.
According to an aspect of the present invention, the level shifter is configured to output a pulse for one of the plurality of scan clock signals, in which a rising edge of the pulse for the one of the plurality of scan clock signals is based on a rising edge of the first clock signal, and a falling edge of the pulse for the one of the plurality of scan clock signals is based on a rising edge of the second clock signal.
According to yet another aspect of the present invention, pulses of the plurality of scan clock signals do not overlap with each other.
According to an aspect of the present invention, the driving mode conversion circuit includes a counter configured to measure a time period of a pulse of the first clock signal, and in response to the time period being less than a threshold value, output a first mode signal to the signal output circuit, and the signal output circuit is configured to in response to receiving the first mode signal from the driving mode conversion circuit, output two successive pulses for one of the plurality of scan clock signals based on the first clock signal and the second clock signal.
According to another aspect of the present invention, the driving mode conversion circuit includes a logical AND gate configured to receive the first clock signal and the second clock signal, and in response to receiving a pulse of the first clock signal and a pulse of the second clock signal at a same time, output a second mode signal to the signal output circuit, and the signal output circuit is configured to in response to receiving the second mode signal from the driving mode conversion circuit, perform a mute operation for one of the plurality of scan clock signals so that no pulse is output for the one of the plurality of scan clock signals when the pulse of the first clock signal and the pulse of the second clock signal are received by the logical AND gate at the same time.
According to an aspect of the present invention, a pulse of each of the plurality of scan clock signals has a gate pulse modulation period at a falling edge of the pulse and including a decreasing slope, a start of the gate pulse modulation period is based on a rising edge of the second clock signal, and an end of the gate pulse modulation period is based on a falling edge of the second clock signal.
According to another aspect of the present invention, a pulse of each of the plurality of scan clock signals is synchronized with a rising edge of the first clock signal and a falling edge of the second clock signal.
Another aspect of the present invention, is to provide level shifter including an internal circuit configured to receive a first clock signal and a second clock signal; in response to a width of a pulse of the first clock signal being greater than a threshold value, sequentially output a pulse for each of a plurality of scan clock signals; in response to the width of the pulse of the first clock signal being less than the threshold value, output two successive pulses for one of the plurality of scan clock signals; and in response to the pulse of the first clock signal overlapping with the pulse of the second clock signal, perform a mute operation for the one of the plurality of scan clock signals so that no pulse is output for the one of the plurality of scan clock signals when the pulse of the first clock signal overlaps with the pulse of the second clock signal.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a display device includes a timing controller, a level shifter including a driving mode conversion circuit configured to generate a mode signal for converting a driving mode based on first and second clock signals output from the timing controller, and a signal output circuit configured to generate and output a plurality of scan clock signals based on the first and second clock signals and the mode signal, a shift register configured to generate a scan signal based on the plurality of scan clock signals output from the level shifter, and a display panel configured to display an image based on the scan signal output from the shift register, in which the driving mode conversion circuit controls generation of high periods of the plurality of scan clock signals based on the first clock signal or the second clock signal.
The level shifter can control clock shift so that one high period or at least two high periods are included in at least one scan clock signal based on the first clock signal.
The level shifter can execute clock shift so that one high period is included in the at least one scan clock signal or may not execute clock shift so that at least two high periods are included in the at least one scan clock signal based on a pulse width of a high period of the first clock signal and an internally determined threshold value.
The level shifter can count a time period during which the high period of the first clock signal is maintained, can execute clock shift so that one high period is included in the at least one scan clock signal if the duration of the high period of the first clock signal is greater than the threshold value, and may not execute clock shift so that at least two high periods are included in the at least one scan clock signal if the duration of the high period of the first clock signal is less than the threshold value.
The level shifter can perform control so that one high period is omitted instead of being included in at least one of the plurality of scan clock signals according to whether a high period of the first clock signal and a high period of the second clock signal overlap.
The level shifter can perform control so that one high period is omitted instead of being included in at least one of the plurality of scan clock signals if a high period of the first clock signal and a high period of the second clock signal overlap.
The driving mode conversion circuit includes a counter configured to generate a first mode signal for controlling clock shift so that one high period or at least two high periods are included in at least one of the scan clock signals based on a result of counting a time period during which a high period is maintained in the first clock signal, and an AND gate configured to generate a second mode signal for controlling one high period to be omitted instead of being included in at least one of the plurality of scan clock signals based on a result of an AND operation performed on the first clock signal and the second clock signal.
In another aspect of the present invention, a level shifter includes a signal input circuit configured to receive first and second clock signals from the outside, a driving mode conversion circuit configured to generate a mode signal for converting a driving mode based on the first and second clock signals transmitted from the signal input circuit, and a signal output circuit configured to generate and output a plurality of scan clock signals based on the first and second clock signals transmitted from the signal input circuit and the mode signal output from the driving mode conversion circuit, in which generation of a high period in at least one of the plurality of scan clock signals is controlled by the mode signal.
The driving mode conversion circuit can include a counter configured to generate a first mode signal for controlling clock shift so that one high period or at least two high periods are included in the at least one scan clock signal based on a result of counting a time period during which a high period is maintained in the first clock signal.
The driving mode conversion circuit can include an AND gate configured to generate a second mode signal for controlling one high period to be omitted instead of being included in at least one of the plurality of scan clock signals based on a result of an AND operation performed on the first clock signal and the second clock signal.
The present invention has an effect of reducing the number of input terminals and signal lines required for a circuit configuration based on a level shifter capable of generating mode signals for converting driving modes by itself. In addition, the present invention can reduce the number of input terminals and signal lines of the level shifter, thereby increasing a degree of freedom in design at the time of manufacturing a display device.
The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention.
A display device according to embodiments of the present invention can be implemented as a television, a video player, a personal computer (PC), a home theater, an automobile electric device, a smartphone, and the like, but is not limited thereto. The display device according to embodiments of the present invention can be implemented as a light emitting display (LED) device, a quantum dot display (QDD) device, a liquid crystal display (LCD) device, or the like. However, hereinafter, a light emitting display device that directly emits light based on inorganic light emitting diodes or organic light emitting diodes will be used as an example for convenience of description.
As shown in
The image provider (set or host system) 110 can output various driving signals along with an image data signal supplied from the outside or an image data signal stored in an internal memory. The image provider 110 can supply a data signal and various driving signals to the timing controller 120.
The timing controller 120 can output a gate timing control signal GDC for controlling the operation timing of the scan driver 130, a data timing control signal DDC for controlling the operation timing of the data driver 140, and various synchronization signals (a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync). The timing controller 120 can supply a data signal DATA supplied from the image provider 110 along with the data timing control signal DDC to the data driver 140. The timing controller 120 can take the form of an integrated circuit (IC) and be mounted on a printed circuit board, but is not limited thereto.
The scan driver 130 can output a scan signal (or a scan voltage) in response to the gate timing control signal GDC supplied from the timing controller 120. The scan driver 130 can supply scan signals to sub-pixels included in the display panel 150 through gate lines GL1 to GLm. Here, m can be a positive number such as an integer greater than 1. The scan driver 130 can take the form of an IC or can be directly formed on the display panel 150 in a gate-in-panel structure, but is not limited thereto.
The data driver 140 can sample and latch the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 120, convert the digital data signal into an analog data voltage based on a gamma reference voltage, and output the analog data voltage. The data driver 140 can supply a data voltage to the sub-pixels included in the display panel 150 through data lines DL1 to DLn. Here, n can be a positive number such as an integer greater than 1. The data driver 140 can take form of an IC and be mounted on the display panel 150 or mounted on a printed circuit board, but is not limited thereto.
The power supply 180 can generate a first voltage at a high level and a second voltage at a low level based on external input voltage supplied from the outside, and output the same through a first power line EVDD and a second power line EVSS, respectively. The power supply 180 can generate and output voltages for driving the scan driver 130 (e.g., gate voltages including a gate high voltage and a gate low voltage), and voltages for driving the data driver 140 (e.g., drain voltages including a drain voltage and a half drain voltage) as well as the first voltage and the second voltage.
The display panel 150 can display an image in response to driving signals including a scan signal and a data voltage, the first voltage, and the second voltage. The sub-pixels of the display panel 150 directly emit light, e.g., via organic light emitting diodes (OLEDs). The display panel 150 can be manufactured based on a substrate having rigidity or flexibility, such as glass, silicon, polyimide, or the like. In addition, the sub-pixels that emit light can include red, green, and blue sub-pixels (e.g., RGB) or include red, green, blue, and white sub-pixels (e.g., RGBW).
For example, one sub-pixel SP can be connected to the first data line DL1, the first gate line GL1, the first power line EVDD, and the second power line EVSS and can include a pixel circuit including a switching transistor, a driving transistor, a capacitor, an organic light emitting diode, and the like. Since the sub-pixel SP used in the light emitting display device directly emits light, the circuit configuration is complicated. In addition, there are various compensation circuits for compensating for deterioration of a driving transistor for supplying a driving current necessary to drive organic light emitting diodes emitting light as well as for deterioration of the organic light emitting diodes. Accordingly, it is noted that the sub-pixel SP is simply illustrated in the form of a block.
Meanwhile, in the above description, the timing controller 120, the scan driver 130, the data driver 140, and the like are described as individual components. However, depending on the implementation method of the light emitting display device, one or more of the timing controller 120, the scan driver 130, and the data driver 140 can be integrated into one IC.
As shown in
The shift register 131 operates based on the signals Clks and Vst output from the level shifter 135 and can output scan signals Scan[1] to Scan[m] for turning on or off transistors formed in the display panel (m being a positive integer greater than one). The shift register 131 can be formed as a thin film on the display panel in a gate-in-panel structure.
As shown in
As shown in
As shown in
The signal input unit 132 can serve to receive first and second clock signals Gclk and Mclk from the outside (e.g., the timing controller) through first and second input terminals IN1 and IN2 and to transmit the received signals to an internal device (e.g., internal circuit) of the level shifter 135.
The driving mode conversion unit 133 can serve to generate and output first and second mode signals Csp and Mute for converting a driving mode of the level shifter 135 based on the first and second clock signals Gclk and Mclk output from the signal input unit 132.
The signal output unit 134 can generate driving clock signal Clks such as a scan clock signal based on the first and second clock signals Gclk and Mclk output from the signal input unit 132 and the first and second mode signals Csp and Mute output from the driving mode conversion unit 133 and output the driving clock signals Clks through first to N-th output terminals OUT1 to OUTn. Here, n is an integer equal to or greater than 3.
As shown in
The first clock signal Gclk can serve to control a rising edge of a high period in the first to i-th scan clock signals Scclk[1] to Scclk[i], and the second clock signal Mclk can serve to control a falling edge of the high period in the first to i-th scan clock signals Scclk[1] to Scclk[i].
The first to i-th scan clock signals Scclk[1] to Scclk[i] can be sequentially generated so that their corresponding high periods do not overlap with each other. The first to i-th scan clock signals Scclk[1] to Scclk[i] can include a gate pulse modulation (GPM) period for modulating a signal waveform after the high period.
Each pulse in the first to i-th scan clock signals Scclk[1] to Scclk[i] can include a rising edge, a gate pulse modulation period, and a falling edge. A generation process of the rising edge, the gate pulse modulation period, and the falling edge will be described below based on the first scan clock signal Scclk[1].
A rising edge of a high period in the first scan clock signal Scclk[1] can occur in response to a rising edge CLK Rising of a high period H in the first clock signal Gclk (e.g., a rising edge of the first scan clock signal Scclk[1] can be synchronized with a rising edge of the first clock signal Gclk, see
As mentioned above, the level shifter 135 according to the first embodiment of the present invention can change driving modes so that the first to i-th scan clock signals Scclk[1] to Scclk[i] can be generated in a variable manner, which will be discussed in more detail below.
As shown in
In addition, as shown in
As can be ascertained with reference to
The level shifter according to the first embodiment of the present invention may or may not execute clock shift on the first to i-th scan clock signals Scclk[1] to Scclk[i] based on a pulse width WH of a high period of the first clock signal Gclk and a threshold value TH set therein.
When clock shift is executed, a high period pulse is generated for the next scan clock signal following an earlier high period pulse of another scan clock signal (e.g., see
To this end, the level shifter can detect the pulse width WH of the high period of the first clock signal Gclk by counting or measuring a time period during which the high period H is maintained in the first clock signal Gclk. In addition, the level shifter can compare the detected pulse width WH of the high period of the first clock signal Gclk with the threshold value TH. If the detected pulse width WH of the high period of the first clock signal Gclk is greater than the threshold value TH (e.g., WH>TH), then clock shift can be performed so that one high period is included in the next scan clock signal, as shown in
As shown in
The level shifter can generate a rising edge (Scclk Rising edge) of a high period of a scan clock signal in response to a rising edge (Gclk Rising edge) of the first clock signal Gclk (S110). The level shifter can detect a pulse width (Gclk pulse width) of a high period of the first clock signal Gclk to determine whether to execute clock shift for the first to i-th scan clock signals Scclk[1] to Scclk[i] (S140). The step of detecting the pulse width (Gclk pulse width) of the high period of the first clock signal Gclk can be defined as a step of checking (CSP Check) whether to operate the level shifter in the first driving mode.
The level shifter can compare the pulse width WH of the high period of the first clock signal Gclk with a threshold value TH (S150). When the pulse width WH of the high period of the first clock signal Gclk is greater than the threshold value TH (WH<TH=N), the level shifter can be normally driven and provide clock shift for the first to i-th scan clock signals Scclk[1] to Scclk[i]. In this situation, the level shifter can perform clock shift (CLK shift) so that one high period is included in the scan clock signal and then sequentially generated in the next scan clock signal, as shown in
On the other hand, if the pulse width WH of the high period of the first clock signal Gclk is less than the threshold value TH (WH<TH=Y), then the level shifter can generate the first mode signal Csp in order to operate in the first driving mode. In this situation, the level shifter may not execute clock shift (No CLK Shift) so that two high periods are included in the scan clock signal in close succession, as shown in
The level shifter can start gate pulse modulation period for the high period of the scan clock signal in response to a rising edge of the second clock signal Mclk (Mclk Rising edge) (Scclk GPM generation) (S170). The level shifter can maintain a gate pulse modulation period of the scan clock signal (Scclk GPM) in response to the pulse width (Mclk pulse width) of the high period of the second clock signal (S180). For example, a period for the start gate pulse modulation for the high period the scan clock signal can be set equal to or approximately equal to a width of a pulse of the second clock signal Mclk (e.g., the gate pulse modulation period can be synchronized with a rising edge and a falling edge of the second clock signal Mclk).
The level shifter can end the high period and the gate pulse modulation period of the scan clock signal in response to a falling edge of the second clock signal (Mclk Falling edge) and generate a low period of the scan clock signal (Scclk Falling generation) (S190).
As shown in
In addition, the level shifter according to the first embodiment of the present invention can omit a high period so that the high period is not included in the first scan clock signal Scclk[1] and then generate a high period of the second scan clock signal Scclk[2], as shown in
As can be ascertained with reference to
The level shifter according to the first embodiment of the present invention can execute clock mute for omitting high periods included in the first to i-th scan clock signals Scclk [1] to Scclk[i] based on high periods H of the first clock signal Gclk and high periods of the second clock signal Mclk. In other words, when the first clock signal Gclk and the second clock signal Mclk are both in a high state, a function in which a rising edge of the first clock signal Gclk occurs is masked, and a pulse of one of the clock signals can be muted or prevented from being generated
To this end, the level shifter can detect the first clock signal Gclk and the second clock signal Mclk. In addition, the level shifter can determine whether a high period of the second clock signal Mclk overlaps with a high period of the first clock signal Gclk. If the high period H of the first clock signal Gclk and the high period of the second clock signal Mclk do not overlap, clock shift can be executed normally so that one high period is included in the current scan clock signal, as shown in
As shown in
The level shifter can generate a rising edge (Scclk Rising edge) of a high period of a scan clock signal in response to a rising edge (Gclk Rising edge) of the first clock signal Gclk (S110). The level shifter can determine whether a high period of the second clock signal Mclk that occurs is overlapping with a high period of the first clock signal Gclk to determine whether to execute clock mute (S120). The step of detecting whether a high period of the second clock signal Mclk occurs while the first clock signal Gclk has a high period can be defined as a step of checking whether the level shifter is operated in the second driving mode (Mclk Check).
If the high period of the first clock signal Gclk and the high period of the second clock signal Mclk do not overlap with each (N: Mclk—>L), then the level shifter determines whether to execute clock shift (S140). If the high period of the first clock signal Gclk and the high period of the second clock signal Mclk overlap (Y: Mclk—>H), the level shifter can execute clock mute to cancel scan clock signal rising so that a high period is not included in the current scan clock signal (e.g., Scclk[1]) (S130), as shown in
The level shifter can detect a pulse width (Gclk pulse width) of the high period of the first clock signal Gclk to determine whether to execute clock shift (S140). The step of detecting the pulse width (Gclk pulse width) of the high period of the first clock signal Gclk can be defined as a step of checking whether to operate the level shifter in the first driving mode (CSP Check).
The level shifter can compare the pulse width WH of the high period of the first clock signal Gclk with a threshold value TH (S150). When the pulse width WH of the high period of the first clock signal Gclk is greater than the threshold value TH (WH<TH=N), the level shifter can be normally driven. In this situation, the level shifter can execute clock shift so that one high period is included in the scan clock signal, as shown in
On the other hand, if the pulse width WH of the high period of the first clock signal Gclk is less than the threshold value TH (WH<TH=Y), the level shifter can generate the first mode signal Csp in order to operate a no clock shift function in the first driving mode. In this situation, the level shifter may not execute clock shift (No CLK Shift) so that two high periods are included in the scan clock signal, as shown in
The level shifter can start gate pulse modulation for the high period of the scan clock signal in response to a rising edge (Mclk Rising edge) of the second clock signal (Scclk GPM generation) (S170). The level shifter can maintain a gate pulse modulation period of the scan clock signal in response to the pulse width (Mclk pulse width) of the high period of the second clock signal (S180).
The level shifter can end the high period and the gate pulse modulation period of the scan clock signal in response to a falling edge of the second clock signal (Mclk Falling edge) and generate a low period of the scan clock signal (S190).
As shown in
The driving mode conversion unit 133 can include a counter CNT and an AND gate AND in order to output mode signals for converting or adjusting the driving mode of the level shifter. The counter CNT can serve to output the first mode signal Csp related to the first driving mode of the level shifter 135. The AND gate AND can serve to output the second mode signal Mute related to the second driving mode of the level shifter 135.
As shown in
If the pulse width WH of the first clock signal Gclk is greater than the internally determined threshold TH (e.g., 200 ns), then the counter CNT can output a first mode off signal Csp_off Operation for executing clock shift so that one high period is included in the next scan clock signal (e.g., see
If the pulse width WH of the first clock signal Gclk is less than the internally determined threshold TH (e.g., 200 ns), then the counter CNT can output a first mode on signal Csp_on Operation for not executing clock shift so that at least two high periods are included in the current scan clock signal (e.g.,
As shown in
The AND gate AND can output a logic low signal L that is a second mode off signal CLK Mute Off for not executing clock mute when a high period H of the first clock signal Gclk and a high period of the second clock signal Mclk do not overlap (e.g., one of the first clock signal Gclk and the second clock signal Mclk is high, while the other is low).
However, when the high period H of the first clock signal Gclk and the high period of the second clock signal Mclk do overlap with each other, the AND gate AND can output a logic high signal H that is a second mode on signal CLK Mute on for executing clock mute (e.g., both of the first clock signal Gclk and the second clock signal Mclk are high at the same time).
The level shifter 135 according to the embodiment of the present invention shown in
On the other hand, a level shifter 135 according to a comparative example shown in
Accordingly, since the level shifter 135 according to the embodiment of the present invention can generate mode signals capable of converting a driving mode by itself (e.g., the mode signals can be self-generated internally, inside the level shifter without required an additional external input), the number of input terminals and signal lines for receiving an additional signal from the timing controller can be reduced.
As described above, the present invention has an effect of reducing the number of input terminals and signal lines required for a circuit configuration based on the level shifter capable of self-generating mode signals for converting driving modes by itself. In addition, the present invention can reduce the number of input terminals and signal lines of the level shifter, thereby increasing a degree of freedom in design (increasing PCB layout efficiency or IC packaging efficiency) at the time of manufacturing a display device.
The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2021-0194725 | Dec 2021 | KR | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 20200143752 | Jung | May 2020 | A1 |
| 20210183318 | Kim | Jun 2021 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20230215376 A1 | Jul 2023 | US |
