Patent Application
20230299762
The disclosure relates in general to a level shifter and an electronic device, and more particularly to a level shifter and an electronic device suitable for high-speed applications.
Level shifter transforms an input signal IN having a first voltage value to an output signal OUT having a second voltage value. As the level shifter improves the compatibility between integrated circuits with different voltage requirements, the level shifter is widely used in electronic devices such as memory devices, memory controllers, high-speed input/output (I/O) circuits, and so forth. With the speed/frequency increment of electronic devices, the precision of the output signal OUT generated by the level shifter should be concerned.
The disclosure is directed to a level shifter and an electronic device. The electronic device includes a digital circuit and the level shifter, and the digital circuit receives an output signal from the level shifter. In response to a rising transition of an input signal, a pull-down current of the level shifter can be cut off immediately. Accordingly, the precision of the duty cycle of the output signal can be improved. The level shifter having such a switching mechanism can be applied to high-speed applications.
According to one embodiment, a level shifter is provided. The level shifter converts a first input signal and a second input signal to an output signal. The first input signal and the second input signal have opposite phases. The level shifter includes a cross-coupled circuit, a protection circuit, and a pull-down module. The cross-coupled circuit includes a first pull-up transistor and a second pull-up transistor. The first pull-up transistor and the second pull-up transistor are electrically connected to a first supply voltage terminal having a first supply voltage. The second pull-up transistor selectively conducts the first supply voltage to the output signal in response to the first input signal. The protection circuit includes a first protection transistor and a second protection transistor. The first protection transistor and the second protection transistor are respectively electrically connected to the first pull-up transistor and the second pull-up transistor. The pull-down module includes a first pull-down circuit, a second pull-down circuit, a first switching circuit, and a second switching circuit. The first pull-down circuit is electrically connected to the first protection transistor and a ground terminal having a ground voltage.
The first pull-down circuit receives the first input signal. The second pull-down circuit is electrically connected to the second protection transistor and the ground terminal. The second pull-down circuit receives the second input signal. The second pull-down circuit selectively conducts the output signal to the ground voltage in response to the second input signal. The first switching circuit is electrically connected to the first pull-down circuit. The first pull-down circuit and the first switching circuit are alternatively switched on. The second switching circuit is electrically connected to the second pull-down circuit. The second pull-down circuit and the second switching circuit are alternatively switched on, and the first switching circuit and the second switching circuit are alternatively switched on.
According to another embodiment, an electronic device is provided. The electronic device includes the level shifter and a digital circuit. The digital circuit is electrically connected to the level shifter. The digital circuit receives the output signal from the level shifter.
In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, it will be apparent that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing.
As illustrated above, the precision of the output signal OUT of the level shifter affects the subsequent operation in the electronic device. According to the present disclosure, the embodiments of the level shifter provide the output signal OUT with a precise duty cycle to an digital circuit.
In the specification, supply voltages HVdd, LVdd, and a ground voltage Gnd are defined. The terminal corresponding to the supply voltage HVdd is defined as a supply voltage terminal v1N, the terminal corresponding to the supply voltage LVdd is defined as a supply voltage terminal v2N, and the terminal corresponding to the ground voltage Gnd is defined as a ground terminal g1N. The supply voltage HVdd is higher than the supply voltage LVdd (for example, HVdd=0.945V˜1.65V, and LVdd=0.72V˜0.88V), and the supply voltage LVdd is higher than the ground voltage Gnd. Besides, the transistors adopted in the level shifters may be high voltage transistors, low voltage transistor, or their combination.
The level shifter receives an input signal IN and an inverted input signal INb. The input signal IN and the inverted input signal INb have opposite phases and transit between the ground voltage Gnd and the supply voltage LVdd. The output signal OUT transits between the ground voltage Gnd and the supply voltage HVdd. In the drawings, the high voltage transistors are represented in thick solid lines, and the low voltage transistors are represented in thin solid lines.
The pull-up module 11 includes a cross-coupled circuit (cpCKT) 111 and auxiliary input circuits (auxCKT1) 113, (auxCKT2) 115. The auxiliary input circuits (auxCKT1) 113, (auxCKT2) 115 are optional.
The cross-coupled circuit (cpCKT) 111 includes pull-up circuits 111a, 111b. The pull-up circuit 111a is electrically connected to the auxiliary input circuit (auxCKT1) 113 and the protection circuit (protCKT) 13. The pull-up circuit 111b is electrically connected to the auxiliary input circuit (auxCKT2) 115 and the protection circuit (protCKT) 13. The auxiliary input circuit (auxCKT1) 113 receives the inverted input signal INb, and the auxiliary input circuit (auxCKT2) 115 receives the input signal IN.
The pull-down module 15 includes pull-down circuits (pdCKT1) 151, (pdCKT2) 153. The pull-down circuit (pdCKT1) 151 receives the input signal IN, and the pull-down circuit (pdCKT2) 153 receives the inverted input signal INb.
The components in the cross-coupled circuit (cpCKT) 111 are introduced. The pull-up circuit 111a is a pull-up transistor PTcp1, and the pull-up circuit 111b is a pull-up transistor PTcp2. The pull-up transistors PTcp1, PTcp2 are PMOS transistors. The source terminals of pull-up transistors PTcp1, PTcp2 are electrically connected to the supply voltage terminal v1N. The drain terminal of pull-up transistor PTcp1 and the gate terminal of pull-up transistor PTcp2 are electrically connected to a conduction terminal c1N. The drain terminal of pull-up transistor PTcp2 and the gate terminal of pull-up transistor PTcp1 are electrically connected to a conduction terminal c2N. The signal at the conduction terminal c2N is defined as an output signal OUT of the level shifter 1.
The auxiliary input circuit (auxCKT1) 113 can be, for example, an auxiliary input transistor NTa1, and the auxiliary input circuit (auxCKT2) 115 can be, for example, an auxiliary input transistor NTa2. The auxiliary input transistors NTa1, NTa2 are NMOS transistors. The drain terminals of auxiliary input transistors NTa1, NTa2 are electrically connected to the supply voltage terminal v1N. The gate terminal of auxiliary input transistor NTa1 receives the inverted input signal INb, and the gate terminal of auxiliary input transistor NTa2 receives the input signal IN. The source terminal of the auxiliary input transistor NTa1 is electrically connected to the conduction terminal c1N, and the source terminal of the auxiliary input transistor NTa2 is electrically connected to the conduction terminal c2N.
The protection circuit (protCKT) 13 includes protection transistors NTp1, NTp2. The protection transistors are NMOS transistors. The gate terminals of protection transistors NTp1, NTp2 are electrically connected to the supply voltage terminal v1N. The drain terminal of protection transistor NTp1 is electrically connected to the conduction terminal c1N, and the drain terminal of protection transistor NTp2 is electrically connected to the conduction terminal c2N.
The pull-down circuit (pdCKT1) 151 includes pull-down transistors NTd1a, NTd1b, and the pull-down circuit (pdCKT2) 153 includes pull-down transistors NTd2a, NTd2b. The pull-down transistors NTd1a, NTd1b, NTd2a, NTd2b are NMOS transistors. The gate terminals of pull-down transistors NTd1a, NTd2a are electrically connected to the supply voltage terminal v2N. The source terminals of pull-down transistors NTd1b, NTd2b are electrically connected to the ground terminal gN.
The drain terminal of pull-down transistor NTd1a is electrically connected to the source terminal of the protection transistor NTp1. The source terminal of pull-down transistor NTd1a is electrically connected to the drain terminal of pull-down transistor NTd1b. The gate terminal of pull-down transistor NTd1b receives the input signal IN.
The drain terminal of pull-down transistor NTd2a is electrically connected to the source terminal of protection transistor NTp2. The source terminal of pull-down transistor NTd2a is electrically connected to the drain terminal of the pull-down transistor NTd2b. The gate terminal of pull-down transistor NTd2b receives the inverted input signal INb.
In
In
As the protection transistor NTp1 is switched off, the signal at the conduction terminal c1N is determined by the pull-up transistor PTcp1 and the auxiliary input transistor NTa1.
As the protection transistor NTp2 and the pull-down transistors NTd2a, NTd2b are all switched on, the conduction terminal c2N is conducted to the ground voltage Gnd through the protection transistor NTp2 and pull-down transistors NTd2a, NTd2b. Thus, the output signal OUT (the signal at the conduction terminal c2N) is set to the ground voltage Gnd.
In the cross-coupled circuit (cpCKT) 111, the pull-up transistor PTcp1 is switched on as its gate terminal receives the ground voltage Gnd (c2N=Gnd). In the auxiliary input circuit (auxCKT1) 113, the auxiliary input transistor NTa1 is switched on as its gate terminal receives the supply voltage LVdd (INb=LVdd).
Since the pull-up transistor PTcp1 and the auxiliary input transistor NTa1 are both switched on, two parallel conduction paths are formed between the supply voltage terminal v1N and the conduction terminal c1N. Thus, the conduction terminal c1N is set to the supply voltage HVdd.
In the cross-coupled circuit (cpCKT) 111, the pull-up transistor PTcp2 is switched off because its gate terminal receives the supply voltage HVdd (c1N=HVdd). In the auxiliary input circuit (auxCKT2) 115, the auxiliary input transistor NTa2 is switched off as its gate terminal receives the ground voltage Gnd (IN=Gnd). Since the pull-up transistor PTcp2 and the auxiliary input transistor NTa2 are both switched off, they do not involve the voltage level of the conduction terminal c2N.
In
The conduction of the auxiliary input transistor NTa1 accelerates the rising speed of the conduction terminal c1N. Even if there is no auxiliary input transistor NTa1, the conduction terminal c1N can still rise to the supply voltage HVdd via the pull-up transistor PTcp1. Therefore, the use of the auxiliary input transistor NTa1 is optional.
The operations of the components and the signals in
In
Compared with
In the switching circuit (swCKT1) 251a, the source terminals of switching transistors PTs1a, PTs1b are electrically connected to the supply voltage terminal v2N. The gate terminals of switching transistors PTs1a, PTs1b receive the input signal IN. The drain terminals of switching transistor PTs1a, PTs1b are respectively electrically connected to the conduction terminal c3N and a pull-down terminal d1N.
When the switching transistor PTs1a is switched on, the supply voltage LVdd is conducted to the conduction terminal c3N. Similarly, when the switching transistor PTs1b is switched on, the supply voltage LVdd is conducted to the pull-down terminal d1N. On the other hand, the conduction terminal c3N is disconnected to the supply voltage LVdd when the switching transistor PTs1a is switched off, and the pull-down terminal d1N is disconnected to the supply voltage LVdd when the switching transistor PTs1b is switched off.
Please note that the gate terminals of switching transistors PTs1a, PTs1b, and the gate terminal of pull-down transistor NTd1 b all receive the input signal IN. However, the switching transistors PTs1a, PTs1b are PMOS transistors, and the pull-down transistor NTd1b is an NMOS transistor. This implies that switching statuses of switching transistors PTs1a, PTs1b, and the switching status of pull-down transistor NTd1b are opposite. That is, when the switching transistors PTs1a, PTs1b are switched on, the pull-down transistor NTd1b is switched off, and vice versa.
In the switching circuit (swCKT2) 253a, the source terminals of the switching transistors PTs2a, PTs2b are electrically connected to the supply voltage terminal v2N. The gate terminals of the switching transistors PTs2a, PTs2b receive the inverted input signal INb. The drain terminals of the switching transistor PTs2a, PTs2b are respectively electrically connected to the conduction terminal c4N and a pull-down terminal d2N.
When the switching transistor PTs2a is switched on, the supply voltage LVdd is conducted to the conduction terminal c4N. Similarly, when the switching transistor PTs2b is switched on, the supply voltage LVdd is conducted to the pull-down terminal d2N. On the other hand, the conduction terminal c4N is disconnected to the supply voltage LVdd when the switching transistor PTs2a is switched off, and the pull-down terminal d2N is disconnected to the supply voltage LVdd when the switching transistor PTs2b is switched off.
Please note that the gate terminals of the switching transistors PTs2a, PTs2b, and the gate terminal of pull-down transistor NTd2b all receive the inverted input signal INb. Moreover, the switching transistors PTs2a, PTs2b are PMOS transistors, and the pull-down transistor NTd2b is an NMOS transistor. This implies that switching statuses of the switching transistors PTs2a, PTs2b and the pull-down transistor NTd2b are opposite. That is, when the switching transistors PTs2a, PTs2b are switched on, the pull-down transistor NTd2b is switched off, and vice versa.
The transistors in level shifter 2 can be classified into different conduction paths, according to their conduction statuses in response to the changes of the input signal IN and the inverted input signal INb. In
In
The upper-left conduction path 31a includes the auxiliary input transistor NTa1 and the pull-up transistor PTcp1. The upper-right conduction path 31b includes the auxiliary input transistor NTa2 and the pull-up transistor PTcp2. The lower-left conduction path 33a includes protection transistor NTp1 and the pull-down transistors NTd1a, NTd1b. The lower-right conduction path 33b includes the protection transistor NTp2 and the pull-down transistors NTd2a, NTd2b.
Please refer to
Therefore, in
As the conduction terminal c3N and the pull-down terminal d1N are both conducted to the supply voltage LVdd, the transistors (NTp1, NTd1a, NTd1b) in the lower-left conduction path 33a are switched off more completely, and the leakage current is prevented from generation. Alternatively speaking, the switching transistors PTs1a, PTs1b can be considered as being utilized to cut off the leakage current along the lower-left conduction path 33a.
Please refer to
Therefore, in
As the conduction terminal c4N and the pull-down terminal d2N are both conducted to the supply voltage LVdd, the protection transistor NTp2 and the pull-down transistors NTd2a, NTd2b are switched off more completely, and the leakage current is prevented from generation. Alternatively speaking, through the conduction of the switching transistors PTs2a, PTs2b, the conduction terminal c4N and the pull-down terminal d2N transit to the supply voltage LVdd immediately after the input signal IN transits from the ground voltage Gnd to the supply voltage LVdd. This feature is further utilized to cut off the leakage current flowing through the lower-right conduction path 33b.
Please refer to
In
Compared with the current value I1, the current value I2 is much lower. This implies that when the input signal IN transits from the ground voltage Gnd to the supply voltage LVdd, the pull-down current Id=I2 corresponding to the level shifter 2 in
The variation of the output signal OUT is related to the pull-down current Id. When the pull-down current Id is greater, the output signal OUT is lower. Therefore, the voltage value V1 is much lower than the voltage value V2 because the current value of the pull-down current Id in
The above embodiments demonstrate that the output signal OUT could have a more precise duty cycle when the switching circuits swCKT1, swCKT2 are adopted. In practical applications, switching transistors are not limited to the PMOS transistors in FIG.3, but can be replaced with different types of transistors.
In
In
In
The switching statuses of switching transistors in the switching circuits (swCKT1), (swCKT2) in
For the switching transistors (Ts1a, Ts1b) in the switching circuit swCKT1, their gate terminals are connected to the input signal IN if they are PMOS transistors or connected to the inverted input signal INb if they are NMOS transistors. For the switching transistors (Ts2a, Ts2b) in the switching circuit swCKT2, their gate terminals are connected to the inverted input signal INb if they are PMOS transistors or connected to the input signal IN if they are NMOS transistors.
In
When IN=Gnd and INb=LVdd are satisfied, the switching transistor Ts1b and the pull-down transistors NTd2a, NTd2b are switched on, and the switching transistor Ts2b and the pull-down transistors NTd1a, NTd1b are switched off. When IN=Vdd and INb=Gnd are satisfied, the switching transistor Ts1b and the pull-down transistors NTd2a, NTd2b are switched off, and the switching transistor Ts2b and the pull-down transistors NTd1a, NTd1b are switched on. Detailed descriptions about the operations of the pull-down module 50a are omitted.
In
When IN=Gnd and INb=LVdd are satisfied, the switching transistor Ts1a and the pull-down transistors NTd2a, NTd2b are switched on, and the switching transistor Ts2a and the pull-down transistors NTd1a, NTd1b are switched off. When IN=Vdd and INb=Gnd are satisfied, the switching transistor Ts1a and the pull-down transistors NTd2a, NTd2b are switched off, and the switching transistor Ts2a and the pull-down transistors NTd1a, NTd1b are switched on. Detailed descriptions about the operations of the pull-down module 50b are omitted.
In
When IN=Gnd and INb=LVdd are satisfied, the switching transistor Ts1 and the pull-down transistor NTd2 are switched on, and the switching transistor Ts2 and the pull-down transistor NTd1 are switched off. When IN=Vdd and INb=Gnd are satisfied, the switching transistor Ts1 and the pull-down transistor NTd2 are switched off, and the switching transistor Ts2 and the pull-down transistor NTd1 are switched on. Detailed descriptions about the operations of the pull-down module 50c are omitted.
In
The circuit designs of the pull-up module 211, the protection circuit 73, and the pull-down module 25 in the level shifter 70 in
The enablement circuit (enCKT1) 77a is an enablement transistor NTen, and the enablement circuit (enCKT2) 77b is an enablement transistor PTen. The enablement transistor NTen is an NMOS transistors, and the enablement transistor PTen is a PMOS transistor. The drain terminal and the source terminal of enablement transistor NTen are respectively electrically connected to the conduction terminal c1N and the ground terminal gN. The source terminal and the drain terminal of enablement transistor PTen are respectively electrically connected to the supply voltage terminal v1N and the conduction terminal c2N. The gate terminals of enablement transistors NTen, PTen respectively receive the inverted power-down signal PDb and the power-down signal PD. The changes of the enablement transistors NTen, PTen, and the output signal OUT corresponding to the power-down signal PD and the inverted power-down signal PDb are summarized in Table 3.
When the control circuit 76 selects the level shifter 70, the control circuit 76 sets the power-down signal PD to the supply voltage HVdd (PD=HVdd) and the inverted power-down signal PDb to the ground voltage Gnd (PDb=Gnd). Then, both the enablement transistors PTen, NTen are switched off. Meanwhile, the drain terminals of protection transistors NTp1, NTp2 receive the supply voltage HVdd via the power-down signal PD (PD=HVdd). Accordingly, the operations of the level shifter 70 are identical to other embodiments described before.
When the control circuit 76 deselects the level shifter 70, the control circuit 78 sets the power-down signal PD to the ground voltage Gnd (PD=Gnd) and the inverted power-down signal PDb to the supply voltage HVdd (PDb=HVdd). Meanwhile, the enablement transistor NTen is switched on, and the conduction terminal c1N is fixed at the ground voltage Gnd because PDb=HVdd is satisfied. The enablement transistor PTen is switched on, and the conduction terminal c2N is fixed at the supply voltage HVdd because PD=Gnd is satisfied. Consequentially, the level shifter 70 does not involve the operations of the digital circuit 78. Furthermore, the protection transistors NTp1, NTp2 are switched off as the power-down signal PD is set to the ground voltage Gnd (PD=Gnd). As the protection transistors NTp1, NTp2 are switched off, the crowbar current phenomenon can be prevented.
The embodiments demonstrate that the rise delay of the output signal OUT has been shortened by cutting off the leakage current path with the switching circuits swCKT1, swCKT2. Consequentially, the level shifters in the present disclosure improve the duty cycle precision of the output signal OUT, and become more suitable for high-speed applications having more critical timing restrictions. The adoption of the switching circuits swCKT1, swCKT2 allows the level shifter to support the high-frequency applications. Moreover, the implementations of the switching circuits swCKT1, swCKT2 are flexible.
It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims and their equivalents.
