Level shifter circuit and method thereof

Abstract

A level shifter circuit and method thereof are provided. The example level shifter circuit may include a pull-up drive unit driving an output node from a first voltage to a second voltage in response to an input signal, a target voltage for the second voltage higher than a target voltage for the first voltage and the input signal based on the first voltage and a third voltage and a pull-down drive unit driving the output node to the third voltage in response to the input signal, the pull-up and pull-down drive units adjusting current levels of at least one of a pull-up current flowing through the pull-up drive unit and a pull-down current flowing through the pull-down drive unit based on whether the pull-up drive unit and the pull-down drive unit are operating concurrently. The example method may include pull-up driving an output node from a first voltage to a second voltage in response to an input signal, a target voltage for the second voltage higher than a target voltage for the first voltage and the input signal based on the first voltage and a third voltage, pull-down driving the output node to the third voltage in response to the input signal, determining whether the pull-up and pull-down driving operations are performed concurrently and adjusting current levels of at least one of a pull-up current and a pull-down current based on the determining step.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate example embodiments of the present invention and, together with the description, serve to explain principles of the present invention.

FIG. 1 is a diagram of a conventional semiconductor device including a level shifter circuit.

FIG. 2 is a waveform diagram of an input signal and an output signal of the level shifter circuit of FIG. 1.

FIG. 3 illustrates a quantity of leakage current corresponding to the waveform of FIG. 2.

FIG. 4 is a diagram of another conventional semiconductor device including a level shifter circuit.

FIG. 5 is a graph illustrating a voltage VPP and a voltage VDD applied to the semiconductor device of FIG. 4.

FIG. 6 is a diagram of a semiconductor device including a level shifter circuit according to an example embodiment of the present invention.

FIG. 7 illustrates the waveform of an output signal OUTS1 of a level shifter circuit according to another example embodiment of the present invention.

FIG. 8 illustrates a waveform of the leakage current with respect to time corresponding to FIG. 7 according to another example embodiment of the present invention.

FIG. 9 is a diagram of another semiconductor device including a level shifter circuit according to another example embodiment of the present invention.

FIG. 10 is a diagram of another semiconductor device including a level shifter circuit according to another example embodiment of the present invention.

FIG. 11 illustrates voltage levels of the external voltage VEXT, the first voltage VDD and the second voltage VPP over time within the semiconductor device of FIG. 10 according to another example embodiment of the present invention.

Claims

1. A level shifter circuit, comprising: a pull-up drive unit driving an output node from a first voltage to a second voltage in response to an input signal, a target voltage for the second voltage higher than a target voltage for the first voltage and the input signal based on the first voltage and a third voltage; anda pull-down drive unit driving the output node to the third voltage in response to the input signal, the pull-up and pull-down drive units adjusting current levels of at least one of a pull-up current flowing through the pull-up drive unit and a pull-down current flowing through the pull-down drive unit based on whether the pull-up drive unit and the pull-down drive unit are operating concurrently.

2. The level shifter circuit of claim 1, wherein the third voltage is a ground voltage.

3. The level shifter circuit of claim 1, wherein the pull-up drive unit reduces the pull-up current flowing through the pull-up drive unit if the pull-up drive unit and the pull-down drive unit are determined to be operating concurrently.

4. The level shifter circuit of claim 3, wherein the pull-up drive unit drives a first signal at an internal node, which corresponds to an inverted signal of a second signal at the output node, to the second voltage in response to the input signal, and the pull-down drive unit drives the signal at the internal node to the third voltage in response to the input signal.

5. The level shifter circuit of claim 4, wherein the pull-up drive unit includes: a first PMOS transistor reducing a first pull-up current, which flows to the internal node, in response to the input signal; anda second PMOS transistor reducing a second pull-up current, which flows to the output node, in response to an inverted signal of the input signal.

6. The level shifter circuit of claim 5, wherein the pull-up drive unit further includes: a third PMOS transistor having a source connected to a drain of the first PMOS transistor, a gate connected to the output node and a drain connected to the internal node; anda fourth PMOS transistor having a source connected to a drain of the second PMOS transistor, a gate connected to the drain of the third PMOS transistor and a drain connected to the output node.

7. The level shifter circuit of claim 6, wherein the pull-down drive unit includes: a first NMOS transistor having a drain connected to the drain of the third PMOS transistor, a gate receiving the input signal and a source to which the third voltage is applied;an inverter having an input terminal connected to the gate of the first NMOS transistor and using the first voltage and the third voltage as a power source; anda second NMOS transistor having a drain connected to the drain of the fourth PMOS transistor, a gate connected to an output terminal of the inverter, and a source to which the third voltage is applied.

8. The level shifter circuit of claim 1, wherein the pull-down drive unit increases the pull-down current flowing through the pull-down drive unit if the pull-up drive unit and the pull-down drive unit are determined to be operating concurrently.

9. The level shifter circuit of claim 8, wherein the pull-up drive unit drives a first signal at an internal node, which corresponds to an inverted signal of a second signal at the output node, to the second voltage in response to the input signal, and the pull-down drive unit drives the signal at the internal node to the third voltage in response to the input signal.

10. The level shifter circuit of claim 9, wherein the input signal is obtained by delaying a power-up signal that indicates levels of the first and second voltages to the level shifter circuit.

11. The level shifter circuit of claim 10, wherein the pull-down drive unit includes: a pulse generator generating a pull-down control signal in response to the power-up signal;a first PMOS transistor increasing a first pull-down current, output from the internal node, in response to the pull-down control signal; anda second PMOS transistor increasing a second pull-down current, output from the output node, in response to the pull-down control signal.

12. The level shifter circuit of claim 11, wherein the pull-down drive unit further includes: a first NMOS transistor having a drain connected to a source of the first PMOS transistor and a gate to which the second voltage is applied;a second NMOS transistor having a drain connected to a source of the second PMOS transistor and a gate to which the second voltage is applied;a third NMOS transistor having a drain connected to a source of the first NMOS transistor, a gate receiving the input signal and a source to which the third voltage is applied;an inverter having an input terminal connected to the gate of the third NMOS transistor and using the first voltage and the third voltage as power source; anda fourth NMOS transistor having a drain connected to a source of the second NMOS transistor, a gate connected to an output terminal of the inverter and a source to which the third voltage is applied.

13. The level shifter circuit of claim 12, wherein the pull-up drive unit includes: a third PMOS transistor having a source to which the second voltage is applied, a gate connected to the output node and a drain connected to the internal node; anda fourth PMOS transistor having a source to which the second voltage is applied, a gate connected to the internal node and a drain connected to the output node.

14. The level shifter circuit of claim 9, wherein the pull-down drive unit comprises: a first NMOS transistor increasing a first pull-down current, output from the internal node, in response to an external voltage; anda second NMOS transistor increasing a second pull-down current, output from the output node, in response to the external voltage,wherein the first voltage is generated based on the external voltage and the second voltage is generated based on the first voltage, and the external voltage is higher than each of the first and second voltages during at least a portion of the operation of the pull-down drive unit.

15. The level shifter circuit of claim 14, wherein the pull-down drive unit further includes: a third NMOS transistor having a drain connected to a drain of the first NMOS transistor, a gate to which the second voltage is applied and a source connected to a source of the first NMOS transistor;a fourth NMOS transistor having a drain connected to a drain of the second NMOS transistor, a gate to which the second voltage is applied and a source connected to a source of the second NMOS transistor;a fifth NMOS transistor having a drain connected to the source of the third NMOS transistor, a gate receiving the input signal and a source to which the third voltage is applied;an inverter having an input terminal connected to the gate of the fifth NMOS transistor and using the first voltage and the third voltage as a power source; anda sixth NMOS transistor having a drain connected to the source of the fourth NMOS transistor, a gate connected to an output terminal of the inverter and a source to which the third voltage is applied.

16. The level shifter circuit of claim 15, wherein the pull-up drive unit includes: a first PMOS transistor having a source to which the second voltage is applied, a gate connected to the output node and a drain connected to the internal node; anda second PMOS transistor having a source to which the second voltage is applied, a gate connected to the internal node and a drain connected to the output node.

17. A method of level shifting, comprising: pull-up driving an output node from a first voltage to a second voltage in response to an input signal, a target voltage for the second voltage higher than a target voltage for the first voltage and the input signal based on the first voltage and a third voltage;pull-down driving the output node to the third voltage in response to the input signal;determining whether the pull-up and pull-down driving operations are performed concurrently; andadjusting current levels of at least one of a pull-up current and a pull-down current based on the determining step.

18. The method of claim 17, wherein the third voltage is a ground voltage.

19. The method of claim 17, wherein adjusting the current levels includes reducing the pull-up current if the determining step determines that the pull-up and pull-down driving operations are performed concurrently.

20. The method of claim 17, wherein adjusting the current levels includes increasing the pull-down current if the determining step determines that the pull-up and pull-down driving operations are performed concurrently.