Patent Application
20110193839
This patent application claims priority from German Patent Application No. 10 2010 007 651.2, filed Feb. 9, 2010, which is incorporated herein by reference in its entirety.
The invention relates to a level shifter for use in LCD display applications.
LCD displays need drive voltage levels far above the usual logic high or low levels from a typical application environment. Level shifters are needed to transform the logic levels of the control signals into positive and/or negative drive signals of an appropriate level that depends on a particular LCD display and can reach several tens of volts. Each level shifter channel has low-impedance output stages that achieve fast rise and fall times when driving the capacitive loading typically present in LCD display applications.
Typical level shifters for TVs and monitors may have multiple separate channels, some of which support gate voltage shaping to improve picture quality by reducing image sticking. This is usually implemented by generating flicker clock signals to determine exactly when gate voltage shaping should begin. In LCD displays using Gate-in-Panel technology, one flicker clock is needed for each pair of input signals. Since each pair of input signals is 180° out of phase, one flicker clock can be used for both. For example, a four-phase display requires two flicker clock signals; a six-phase display needs three flicker clock signals and so on.
In practical applications it is not always possible to provide all the flicker clock signals a display requires. This can be because of limited capabilities of the timing controller that generates these signals, or because of the limited number of connections supported by the level shifter IC. Furthermore, the conventional approach described above does not easily allow a system designed for one type of display (e.g. four-phase) also to be used for another (e.g. six-phase). If a dedicated flicker clock signal is not available for each pair of input signals, an additional signal can be generated to synchronize a single flicker clock signal at the start of each picture frame, but at the expense of complexity.
In one aspect of the invention a level shifter for use in LCD display applications is provided which includes a group of separate channels each with a signal input and a signal output and with channel control circuitry supporting gate voltage shaping for improving image quality. The level shifter further has a number of flicker clock inputs. The channel control circuitry of each particular channel in the group comprises logic circuitry combining all of said flicker clock inputs with the signal input of the particular channel and signal inputs form other channels into a gate voltage shaping enable signal for the control circuitry of the particular channel. With this configuration it is possible to use the same level shifter IC with only one flicker clock signal for all phases, regardless of how many, without the need for an additional synchronization signal, or multiple flicker clock signals as is conventional. The inventive level shifter automatically determines which input signal needs to be modified for the gate voltage shaping when the active portion of the flicker clock signal is detected.
In an implementation, the logic circuitry comprises an AND gate with inputs to each of which one of the signal inputs is applied, and an OR gate with inputs to each of which one of the flicker clock inputs is applied. The logic circuitry further comprises a flip-flop with a D input to which an output of the AND gate is applied, a clock input to which an output of the OR gate is applied and an output which provides the gate voltage shaping enable signal. Thus, by logically ORing the flicker clock signals generated by a timing controller, a single flicker clock signal is obtained and the level shifter internally always works with only that single flicker clock signal. Therefore, systems can be developed that can be used with any number of phases and any number of flicker clock signals with only minor changes to the application circuit required.
Further aspects of the invention will appear from the appending claims and from the following detailed description given with reference to the appending drawings.
The level shifter in
It should be understood that in an actual implementation of the level shifter, other functionality is typically incorporated such as further channels or functionality for discharging the display panel during power-down. Such functionality being irrelevant to the invention, it will not be disclosed further.
A pair of complementary transistors Q1 and Q2 is connected in series between supply terminals VGH1 and VGL, the interconnection node being connected to the output OUT1 of the channel. Transistors Q1 and Q2 are driven by channel control circuitry which has inputs for three input signals and inputs for the three flicker clock signals FLK1, FLK2, FLK3. In addition to its associated input IN1, the control circuitry of channel 1 receives two further input signals, IN2 and In3. The output OUT1 of the channel goes to a connected LCD panel. The channel control circuitry also drives a further transistor Q3 which, when ON, ties the output terminal OUT1 to terminal RE to which a discharge resistor is connected.
The diagram in
The diagram in
The invention, as will be explained, allows the level shifter to work with one, two or three flicker clock signals, or even without any of them if gate voltage shaping is not intended.
With reference now to
Each logic circuitry has an AND gate with inputs to which a selection of input signals is applied, an OR gate with inputs to which all of the flicker clock signals are applied (regardless whether active) and a D-type flip-flop with active low clock signal and active low asynchronous clear. The output of the AND gate is applied to the data input D and to the clear input CLR of the flip-flop and the output of the OR gate is applied to the clock input CK of the flip-flop. The output of the flip-flop is an enable signal GPM_ENx for the particular channel x. The enable signal GPM_ENx is used by the channel control circuitry of the corresponding channel x and has the effect of enabling gate voltage shaping in that channel in the manner illustrated in
The AND gate of each channel x receives its associated input signal Inx and two further input signals which are those of different channel pairs. With channel pairs
channel 1 and channel 4;
channel 2 and channel 5;
channel 3 and channel 6;
where the input signals between each pair are 180° out of phase (although the duty cycles may not be 1:1), the input signals to the channels are as follows:
It should be understood that the above scheme is for a six-phase LCD; on principle, it can be adapted to any number of phases.
In operation of the level shifter with three flicker clock signals being available, the timing diagram of signals is as shown in
In operation of the level shifter with only one flicker clock signal FLK being available, the timing diagram of signals is as shown in
Although the present invention has been described in detail, it should be understood that various changes, substitutions and alterations can be made thereto without departing from the spirit and scope of the invention as defined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10 2010 007 651.2 | Feb 2010 | DE | national |
