Patent Application
20220381918
A solid-state Lidar (Light Detection And Ranging) system includes a photodetector, or an array of photodetectors, that is fixed in place relative to a carrier, e.g., a vehicle. The term “solid-state” refers to the concept of the system not having moving components such as spinning mirrors or localized gimbal systems. Light is emitted into the field of view of the photodetector and the photodetector detects light that is reflected by an object in the field of view, conceptually modeled as a packet of photons. For example, a Flash Lidar system emits pulses of light, e.g., laser light, into the entire field of view. The detection of reflected light is used to generate a three-dimensional (3D) environmental map of the surrounding environment. The time of flight of reflected photons detected by the photodetector is used to determine the distance of the object that reflected the light.
The solid-state Lidar system may be mounted on a vehicle to detect objects in the environment surrounding the vehicle and to detect distances of those objects for environmental mapping. The output of the solid-state Lidar system may be used, for example, to autonomously or semi-autonomously control operation of the vehicle, e.g., propulsion, braking, steering, etc. Specifically, the system may be a component of or in communication with an advanced driver-assistance system (ADAS) of the vehicle.
A 3D map is generated a histogram of time of flight of reflected photons. Difficulties can arise in providing sufficient memory for calculating and storing histograms of the time of flights.
The lidar system 20 may be a solid-state lidar system 20. In such an example, the lidar system 20 is stationary relative to the vehicle 28. For example, the lidar system 20 may include a casing that is fixed relative to the vehicle 28, i.e., does not move relative to the component of the vehicle 28 to which the casing is attached, and internal electronic components of the lidar system 20 are supported by the casing.
As a solid-state lidar system, the lidar system 20 may be a flash lidar system. In such an example, the lidar system 20 emits pulses of light into the field of illumination FOI (
With reference to
The controller 26 may be configured to perform operations specified herein. The controller 26 may include a programmable processor and/or a dedicated electronic circuit including or embedded within an Application-Specific Integrated Circuit (ASIC) that is manufactured for a particular operation, e.g., an ASIC for determining gain control signal. In another example, a dedicated electronic circuit may include a Field-Programmable Gate Array (FPGA) which is an integrated circuit manufactured to be configurable by a customer. Typically, a hardware description language such as VHDL (Very High Speed Integrated Circuit Hardware Description Language) is used in electronic design automation to describe digital and mixed-signal systems such as FPGA and ASIC. For example, an ASIC is manufactured based on VHDL programming provided pre-manufacturing, whereas logical components inside an FPGA may be configured based on VHDL programming, e.g. stored in a memory electrically connected to the FPGA circuit. In some examples, a combination of processor(s), ASIC(s), and/or FPGA circuits may be included inside a chip packaging. Alternatively, parts of the controller may also be realized through “custom” design, wherein schematics are used to create the control function, instead of VHDL.
The controller 26 of the lidar system 20 may be a microprocessor-based controller implemented via circuits, chips, or other electronic components. The controller 26 is in electronic communication with the pixels 38 (e.g., with the ROIC 40 and power-supply circuits) and the vehicle 28 (e.g., with the ADAS 30) to receive data and transmit commands. The controller 26 may include a processor and a memory. The controller 26 may be configured to execute operations disclosed herein. Specifically, the memory stores instructions executable by the processor to execute the operations disclosed herein and electronically stores data and/or databases. electronically storing data and/or databases. The memory includes one or more forms of computer-readable media, and stores instructions executable by the controller 26 for performing various operations, including as disclosed herein, for example the method 900 shown in
The light emitter 22 may be a semiconductor light emitter, e.g., laser diodes. In one example, as shown in
The light-receiving system 34 detects light, e.g., emitted by the light emitter 22. The light-receiving system 34 includes a light detector, such as at least one photodetector 24. For example, the light detector may be a focal-plane array (FPA). The FPA can include an array of pixels 104. Each pixel 104 can include at least one photodetector 24 and a read-out integrated circuit (ROIC) 40. A power-supply circuit 42 may power the pixels 104. The FPA detects photons by photo-excitation of electric carriers, e.g., with the photodetectors 24. An output from the FPA indicates a detection of light and may be related to the amount of detected light. The outputs of FPA are collected to generate a 3D environmental map, e.g., 3D location coordinates of objects and surfaces within FOV of the lidar system 20. The FPA may include the photodetectors 24, e.g., that include semiconductor components for detecting reflections from the FOV of the lidar system 20.
Light emitted by the light emitter 22 may be reflected off an object back to the lidar system 20 and detected by the photodetectors 24. An optical signal strength of the returning light may be, at least in part, related exponentially to a time of flight/distance between the lidar system 20 and the object reflecting the light. The optical signal strength may be, for example, an amount of photons that are reflected back to the lidar system 20 from one of the shots of pulsed light. The greater the distance to the object reflecting the light/the greater the flight time of the light, the lower the strength of the optical return signal, e.g., for shots of pulsed light emitted at a common intensity. A time-of-flight determination and/or histogram may be used to generate the 3D environmental map.
The photodetectors 24 may be single photon avalanche diodes (SPADs), such as SPAD diode 116 in
Optical sensor ICs may be used in the ADAS 30 for constructing real-time and 3D awareness of objects in front of or in the periphery of a vehicle 28.
Such SPAD-based optical sensor ICs create opportunity and value to ADAS 30 and other applications in large part because they provide a path to progressively smaller pixels 104 and lower manufacturing cost. Smaller pixels 104 contribute to higher resolution image construction which in turn allows improvements in overall system performance. SPAD based optical sensors also create an opportunity to use high-density digital integrated circuit technology in that such diodes force a time to digital (TDC) conversion immediately in the signal chain. Alternatively, a histogram circuit which could comprise an SRAM with controlling logic could also be used instead of a TDC-based circuit for reconstructing the return signal from SPAD responses to multiple light emitter 22 pulses. Often, the histogram data can be processed by a matched filter processor to further improve the ToF measurement accuracy. The digital-only backend processing of ToF of SPAD receiver diodes creates compelling performance advantages for systems that use them. SPAD-based sensors also can extend the ToF range (i.e. distance to object) within the field of view in that they are sensitive to low return signals, ideally even a single reflected photon.
SPAD diodes in such sensors are typically electrically back-biased, often by 10 to 100 volts, which causes the diodes to form a depletion region wherein ideally no current flows. Such biasing is often referred to as reset or SPAD gating. The concept is that the SPAD diode is activated and ready to receive a photon which will avalanche and generate an electrical output pulse to a circuit which will determine ToF.
When such back-biased junctions are struck by an external photon, then the photon can cause an “avalanche” of hole-electron pairs to be generated, which in turn creates a pulse of current. The gain of this avalanche can be expressed as a number of hole-electron pairs divided by 1 (i.e. one photon), so the number of hole-electron pairs is essentially the gain. Such gains can range from a few hundred to several million.
Under operational conditions of the optical sensor, a light emitter 22 generates a light pulse in a wavelength of interest, and this pulse travels through media (space, air, water, or another fluid) and reflects off of objects of interest. A portion of the incident light pulse energy can be reflected by objects and return to a SPAD-based optical sensor that is related physically and electrically to the light emitter 22 which emitted the pulse. Often, light receiving system 34 includes an optical bandpass filter in series with receiving optics to attenuate out-of-band light to improve the selectivity of the receiving pixels to the wavelength of interest from light emitter 22. In such manner, designers of these systems work to improve the number of captured laser photons and reject unwanted photons. Note that these same filters will also attenuate a small percentage of returned laser energy.
SPAD-based sensors often use a histogram processor to construct a true return ToF to an object. In as much as SPAD diodes are sensitive to as little as a single photon, it makes such sensors vulnerable to stray light sources, including ambient solar radiation. Since the diodes are also semiconductor devices, they are susceptible to spontaneous Generation-Recombination (GR) events wherein thermally activated carriers spontaneously form in the back-biased depletion region of these diodes, and where such GR pairs can trigger an avalanche, which may be referred to as dark counts or dark current. (The term “dark” simply means not-generated by an external photon.) Thus, with the liability and possibility that avalanche diode effects can be triggered by objects that are not physical objects of interest in the field a view and whereas such events are somewhat random in time domain, those skilled in the art of SPAD sensor physics and design will often use a histogram processor, combined with a number of repeated laser shots to accumulate many ToF returns and then filter the histogram, looking for real objects of interest within the field of view (and filtering or eliminating random avalanche events).
If SPAD-based sensors were reset (per pixel 104) and triggered only once per laser firing, their range would be very limited, especially in environments having a high number of photons in the band (wavelength) of interest. Therefore, two SPAD circuit improvements come into play. First, in modern SPAD-based sensors, quench circuits and reset circuits restore each SPAD diode to a reset state, ready to receive another photon. Thus, within a single laser pulse measurement period, a single SPAD diode could receive a plurality of photon events and different points of time. The second effect is that in practical circuits, the ToF is commonly broken up into bins. Bins are intervals of time related to overall distance, and bins are the primary element of histograms. Thus, when a SPAD generates a pulse, it is related to a bin which is part of a histogram (i.e. a histogram bin). When a SPAD generates a pulse, a digital circuit stores the event often by incrementing a count value within a histogram bin. When a SPAD has triggered a pulse and that pulse is recorded in the histogram, the SPAD is quenched and reset, allowing it to trigger again, still within the same laser pulse period. Any further triggers will also be recorded in the histogram.
Histograms can be externally processed by a computer or other electrical device. As another example, histograms may be collocated on the sensor IC to improve power and performance. Histograms can be stored in a Random-Access Memory (RAM) or a Static Random-Access Memory (SRAM). SRAM memories require area and consume power; sometimes the power consumption is also leakage. SRAM dynamic power (the power associated with activity) and leakage power can increase the thermal loading of a sensor IC. If the number of pixels 104 is relatively large, then the amount of SRAM memory required to create the necessary histograms per pixel 104 can also be large and thus the area and power can also be large.
An increase of a die size of a SRAM memory increases increase the cost of a sensor IC and additionally an increased size of a memory die may adversely impact yield. In cases where one or more SRAMs may be associated with and collocated within a pixel 104 area, the size of the SRAM becomes of notable concern in optimization and may limit the smallest attainable size of a pixel 104. Shrinking pixel 104 dimensions is a desirable improvement because it reduces the size of a two dimensional pixel 104 array, allowing for reduction in cost and a shorter camera focal length for given f-number.
As a power consumption of an IC increases, the temperature of the die also increases. If the temperature increases, then the dark current or dark count will increase due to more thermally generated GR pairs, such dark count increasing possibly obscuring ToF for objects of interest in the field of view (i.e. reducing signal to noise [SNR]).
Thus, it is advantageous to reduce the die size and power of a sensor IC and is subsequently advantageous to reduce the size of RAM/SRAM.
Additionally, there is an interest in reducing an effect of ambient and dark counts associated with SPAD devices in pixels 104. A particular concern for ADAS sensors is that in order for the sensor to be truly useful for automotive applications, a sensor must be robust and operational against multiple adverse weather and environmental conditions. One operational condition that adversely impacts SPAD-based lidar receiving imagers (ROICs) is the reflection of sunlight at critical angles off of targets of interest in a field of view (FOV). It is desirable for the laser impulse to reflect off of a target in the FOV, and this is the signal that the SPAD imager is supposed to respond to. However, in-band (laser wavelength) photons are emitted by the sun at various power levels (fluxes) and not correlated to the impulse from the laser of a system, resulting in two deleterious effects. First, as solar photons impinge on the detector diodes of the system and cause avalanche events, the dead time of these events are regions where the desired signal cannot cause diode avalanches. Thus, as solar flux causes numerous dead time intervals per laser impulse, subsequently, the blocked regions that might have detected a target now appear to the system as signal attenuation. Second, the solar events do get recorded into the acquisition histogram of a pixel 104, thus elevating the conceptual noise floor (or noise “pedestal”). In this manner, thus attenuating the signal of interest and elevating the background counts in the histogram, the solar flux reduces signal to noise (SNR) of the system, and this, in turn, reduces operable detectable range of a target, making the sensor less useful under these worst case ambient conditions.
Herein a circuit and method are disclosed for reducing the size of RAM/SRAM that includes histogram memory. Additionally, the disclosed circuit may lead to improvements in range accuracy by better preserving the return impulse shape of a laser pulse return, allowing downstream digital processing to assess the center or peak of the return. The disclosed circuit may further contribute to improved signal-to-noise (SNR) of the return pulses by attenuating non-correlated ambient photons more than attenuating laser induced (signal) photons.
A SPAD control circuit 102 within each pixel 104 of an imaging IC 100 couples to a timing generator circuit 106 for a pixel 104 on the same imaging IC 100. The SPAD control circuit 102 also couples to one or more SPAD subcircuits 108 also located in or associated with the pixel 104. The SPAD control circuit 102 also couples to a histogram memory circuit 110 also located in or associated in some manner with the pixel 104. The controller 26 and the timing generator circuit 106 form at least part of a control system of the lidar system 20.
The pixel 104 timing generator circuit 106 of the imaging IC 100 couples to a laser enable circuit which could be on the same imaging IC 100 or could be located not on the imaging IC 100. The histogram memory circuit 110 couples to a readout circuit 111. The readout circuit can be coupled to other readout circuits in order to network and cause the transmission of data. A video timing generator circuit 112 couples to the readout circuit.
The laser enable circuit 114 transmits a laser enable pulse which can cause a laser such as light emitter 22 to fire. The laser enable pulse is also received by the pixel 104 timing generator circuit 106. In response to the laser enable pulse, the pixel 104 timing generator circuit 106 creates and transmits a sequence of timing pulses to the SPAD control circuit 102 of one or more pixels 104.
The sequence of timing pulses relate to locations in the histogram memory circuit. The sequence of timing pulses have two important properties. A first property is that the phase of the sequence of timing pulses can be varied relative to the laser enable pulse, creating a time offset relative to the laser enable pulse. A second property is the time offset can relate to an integer fraction of the period of the sequence of timing pulses.
Upon receipt of the sequence of timing pulses, the SPAD control circuit 102 causes multiple coordinated actions. A first coordinated action is that the SPAD control circuits 102 realizes a sequence of aperture times in which the SPAD control circuit 102 is sensitive to Pulse Events by one or more SPAD subcircuits 108. Another coordinated action is that the SPAD control circuit 102 in some embodiments can control the enablement of the same one or more SPAD subcircuits 108. Another coordinated action is that the SPAD control circuit 102 can cause bins of the histogram memory circuit to increment as follows: the bins of the histogram memory circuit that increment relate one-to-one with specific pulses within the sequence of timing pulses from the pixel 104 timing generator circuit 106.
The aperture times have two specified properties: A first specific property is that the aperture times are time intervals having a width that is smaller than the period of the sequence of timing pulses, a second property is that the aperture times create effective apertures that relate to an integer fraction of the period of the timing pulses.
In an example embodiment, the pixel 104 timing generator circuit 106 will set the phase of the sequence of timing pulses to a specific value for a specific number of laser enable pulses. After the specific number of laser enable pulses, the timing generator 106 of the pixel 104 allows a video timing generator circuit 112 to send video timing to the readout circuit of pixels 104, allowing the readout circuits to read data out of the histogram memory circuit 110. The histogram memory circuit 110 zeros (resets) bin values during readout. After video readout, the pixel 104 timing generator circuit 106 can change the phase of the sequence of timing pulses. The pixel 104 timing generator circuit 106 can modify the phases of the sequence of timing pulses by an algorithm that relates to allowing each fractional interval of the period of the sequence of timing pulses to be sensitive to pulse events of the SPAD subcircuit 108.
In another example embodiment, the histogram memory circuit has two banks of memory, allowing acquiring data and transmitting data simultaneously. Thus, the laser enable circuit and pixel 104 timing generator circuit 106 may not need to pause for the actions of the video timing generator circuit.
With reference to the Figures, wherein like numerals indicate like parts throughout the several views, a method includes actuating a light emitter 22, e.g., a laser diode, to emit a first series of laser pulses in a first frequency, enabling a single-photon-avalanche diode (SPAD) in a pixel 104 of a focal-plane array to detect a photon during a first series of enable times defined by a first series of enable pulses in a second frequency greater than the first frequency, and updating a histogram memory based on a photon detected during the first series of enable times.
SPAD control circuit 102 within each pixel 104 of an imaging IC 100 couples to a pixel timing generator circuit 106 on the same imaging IC 100. An imaging IC 100 may include a one or two dimensional array of pixels 104, along with supporting circuitry such as bias circuitry, IO circuitry, control and test circuitry, IO (Input Output) pads, and IO drivers and receivers. In one example, the imaging IC 100 may include only a single pixel 104, such pixel 104 possibly having a plurality of SPAD devices or SPAD subcircuits 108. A “subcircuit,” herein, is a portion of a circuit included in the imaging IC 100.
The SPAD control circuit 102 couples to one or more SPAD subcircuits 108 also located in or associated with the pixel 104. A SPAD device is a diode, configured and used as a detector for light waves most typically in the visible spectrum or in the near infrared or shortwave infrared spectrums. A typical SPAD configuration has a quench circuit which might be as simple as a single device, a resistor. The SPAD device, coupled to its support quench circuit can be referred to as a SPAD subcircuit 108.
With continued reference to
The pixel timing generator circuit 106 of the imaging IC 100 couples to a laser enable circuit 114 which could be included in the imaging IC 100 or could be located not on the imaging IC 100. For example, an FPGA, SoC, CPU, or similar sequencer device may include the laser enable circuit 114. However, it could be advantageous that the imaging IC 100 includes the laser enable circuit 114, e.g., for cost reduction or system simplification reasons.
The histogram memory circuit 110 couples to a readout circuit 111 . At regular intervals, after acquiring a number of laser shots (caused by the Laser Enable Signals), the contents of the histogram memory circuit 110 is output to a “host” circuit which could be an FPGA, CPU, SoC, microcontroller, ASIC, or any number of devices or circuits. With reference to
The readout circuit 111 can be coupled to other readout circuits 111 in order to network and cause the transmission of data. A video timing generator circuit 112 couples to the readout circuit 111. Each pixel 104 has a readout circuit 111 which may include a tristate driver, a shift register, a wire-OR network, a daisy-chain gate network, and/or other such circuits. Subject to timing signals from the video timing generator circuit 112, each readout circuit 111 of a pixel 104 responds to pull data from the histogram memory circuit 110 and output (transmit) that data to a common output IO link, allowing the data to be transmitted to another circuit for further processing, e.g., determining an object location.
The laser enable pulse is also received by the pixel timing generator circuit 106. The laser enable pulse is used by the pixel timing generator circuit 106 to establish a “time-0” reference with respect to image acquisition. In an example embodiment, the laser enable circuit 114 may create a number of laser enable pulses for a given Frame of data. A typical number of laser enable pulses for a given Frame could be between 500 and 2500 laser enable pulses. A typical duration of a frame of data could be 30 milliseconds. The importance of establishing time-0 is that it creates a timing reference framework for recording SPAD events in a histogram.
In response to the laser enable pulse, the pixel timing generator circuit 106 creates and transmits a sequence of timing pulses at a second frequency to the SPAD control circuit 102 of one or more pixels 104; the second frequency is higher than the first frequency and corresponds to windows of time represented by histogram bins.
The aperture times have two specific properties valued by the invention. A first property is that the aperture times are time intervals having a width that is smaller than the period of the sequence of timing pulses. A second property is that the aperture times create effective apertures that relate to an integer fraction of the period of the timing pulses. These apertures to have this fundamental set of operational principles. In this manner, correlated events, such as returned laser pulses are fixed with reference to time-0 of the laser unit (i.e. relative to the laser enable pulse). In contrast, background events (background noise) is not correlated. When the apertures are smaller than the period of the sequence of timing pulses, random background signals are attenuated accordingly. In this manner, the sequence of timing pulses being realized as apertures with these properties, can improve signal to noise ratio, thus extending the working range of the lidar unit.
Further, as shown in
The laser enable pulse initiates the sequence of timing pulses. With continuous reference to
The laser unit 134 may be actuated to emit a third series of laser pulses (non-overlapping with the second series of laser pulses) in the first frequency, and at a second time offset, enabling the SPAD to detect a photon during a third series of enable times defined by a third series of enable pulses in the second frequency. Thus, the SPAD control circuit 102 of each pixel 104 can use the logical combination of the two timing pulses of the sequence of timing pulses to synthesize or “realize” a set of apertures (an aperture being a time window). The apertures can be virtual. SPAD enable could allow a SPAD to be operational, that is, to be able to avalanche and latch enable can allow a latch to “see” an avalanche. In this manner, a latch in the SPAD control circuit 102 could capture an event if an avalanche occurs. Alternatively, the latch could be an RS latch (a Reset-Set Latch). In another embodiment, the latch could be replaced with a flipflop wherein the SPAD enable signal can asynchronously clear the flipflop when it is logic ‘1’ (one) and not clear it with logic ‘0’ (zero). The SPAD subcircuit 108 pulse events signal could be the clock on the flipflop and the data input of the flipflop could be a logic ‘1’. In this manner, a SPAD subcircuit 108 pulse event uses its edge to change the state of the flipflop to logic ‘1’. In these embodiments, there is no physical aperture signal per se; it is inferred from the timing. In other embodiments, however, such a signal could be realized if there were an advantage to doing so. Regardless of how the logic is actually realized, the invention claims this technique of creating these apertures.
The sequence of timing pulses relate to locations in the histogram memory circuit 110. The repeated set of laser enable pulses and the synthesized or “realized” sets of apertures have a 1:1 relationship with bins in the histogram memory circuit 110. For example, a plurality of time offsets may be determined, and at each of the plurality of time offsets, the SPAD subcircuit 108 may be enabled to detect a photon during a second series of enable times defined by a second series of enable pulses in the second frequency. The plurality of second series of enable pulses may cover a clock period of the first series of laser pulses.
A notional set of histogram memory circuit values are shown as coarse histogram. The coarse histogram can be realized in the imaging IC 100 as some variation of SRAM circuitry.
It is an advantage of the invention that the required SRAM physical dimensions can be much smaller than the effective final histogram that is able to be constructed on a host CPU or other processor. In this manner, the implementation characteristics of the invention act to reduce the overall size of SRAM on imaging IC 100, relative to prior art.
The sequence of timing pulses have two properties. A first property is that the phase offset of the sequence of timing pulses can be varied relative to the laser enable pulse, creating a time offset relative to the laser enable pulse.
A second property is the phase offset can relate to an integer fraction of the period of the sequence of timing pulses. The importance of the phase offset being an integer fraction of the period is that the related apertures reduce the level of ambient or background signal by that same integer fraction and can lead to improvements in signal to noise ratio.
Upon receipt of the sequence of timing pulses, the SPAD control circuit 102 causes multiple coordinated actions. A first coordinated action is that the SPAD control circuits 102 realizes a sequence of aperture times in which the SPAD control circuit 102 is sensitive to pulse events by one or more SPAD subcircuits 108. Another coordinated action is that the SPAD control circuit 102 in some embodiments can control the enablement of the same one or more SPAD subcircuits 108. Another coordinated action is that the SPAD control circuit 102 can cause bins of the histogram memory circuit 110 to increment as follows: the bins of the histogram memory circuit 110 that increment relate one-to-one with specific pulses within the sequence of timing pulses from the pixel timing generator circuit 106, thus updating a respective bin of the histogram based on a detected photon. A number of bins is defined based on the first and second frequencies. The exact number of histogram bins implemented in a given imaging IC 100 is determined by the following: the desired TOF range (which represents real-world physical range to target) drives the overall depth of the histogram. Second, the desired TOF resolution determines the size of the aperture. Finally, the number of laser shots, acceptable frequencies to operate the imaging IC 100 at are both optimization parameters that determine the period of frequency of the pulses emitted by the pixel timing generator 106 and the number of divisions within that period that determine the number of time offsets to consider. There is no specific rule for favoring one versus the other. As an illustrative example of design optimization of imaging IC 100, assume the desired range is 70 meters and the desired range resolution is 2 cm. Further assume that in as much as an advantage of the invention is recreating the return laser pulse shape, a matched filter could relax the per-virtual-bin capture resolution to 4*resolution, so 4*2 cm in this example equals to 8 cm. Then, then the “virtual” number of histogram bins is 70 m/0.08 m=875. The lapse time that the histogram represents is also called the “gate” time and relates to range as (70 m/1.5e8 m/s)=470 ns. (1.5e8 m/s is ½ of the speed of light and accounts for outbound and return of the light reflected from a target.) If the desired SPAD enable and Latch enable frequency is 100 MHz (for reasons of optimization), then the number of coarse level bins is the gate time*latch enable frequency=(470 ns)*(100e6 Hz)=47 bins. The number of offsets per coarse level bin would then be the virtual bins divided by the coarse level bins=875 virtual bins/47 bins=19 offsets. In real-world practice, 19 offsets is close to perfect-power-of-2 number 16, and thus, a practical design would consider 16 offsets and then increase the SPAD enable/latch enable frequency to approximately 120 MHz (assuming this was possible). Also then, when adjusting the SPAD enable frequency, the number of coarse level bins would increase to 57. So, in this illustrative example, 57 histogram bins would be required and the number of explored offsets would be 16 and the SPAD enable frequency would be 120 MHz. Also, note that if there were 32 laser shots per offset, then the maximum bit width of the 57 histogram bins would be 5 bits (25=32). The total required laser shots would be 32 laser shots per offset*16 offsets=512 total laser shots. Also note that a prior art histogram without the invention would require a histogram to have 9 bits (corresponding to 512 laser shots, i.e. 29=512). The size of memory size created by the invention is (57*5)/(512*9)=6.1% of the size of the prior art memory. In other words, the invention has shrunk hardware memory requirements on imaging IC 100 by 16×.
In an embodiment, the pixel timing generator circuit 106 sets the phase of the sequence of timing pulses to a specific value for a specific number of laser enable pulses. After the specific number of laser enable pulses, the pixel timing generator 106 allows a video timing generator circuit 112 to send video timing to the readout circuit of pixels 104, allowing the readout circuits 111 to read data out of the histogram memory circuit 110. The histogram memory circuit 110 zeros (resets) bin values during readout. After video readout, the pixel timing generator circuit 106 can change the phase of the sequence of timing pulses. The pixel timing generator circuit 106 can modify the phases of the sequence of timing pulses by an algorithm that relates to allowing each fractional interval of the period of the sequence of timing pulses to be sensitive to SPAD subcircuit 108 pulse events.
Timing generator circuit 106 can have multiple embodiments. In one embodiment, there can be one timing generator circuit 106 for each row of an array of pixels such that all pixels of a given row respond to signals by a specific instance of a timing generator 106. Similarly, timing generator 106 instances could also be associated with columns instead of rows, and such an embodiment, each pixel of a column would respond to specific instances of timing generator 106. Timing generator circuits 106 could be associated with multiple rows or multiple columns of pixels. For instance, timing generator circuits 106 could be associated with pairs of rows or 4 rows, and so forth.
When timing generator circuits 106 are associated with rows or columns, the offsets used by the timing generator circuits 106 can be different than one another for a given activation of a laser. Thus, for example, timing generator circuits 106 of rows {0, 8, 16, 24, . . . } could use an offset time of 0 for a given laser flash, while timing generator circuits 106 of rows {1, 9, 17, 25, . . . } could use one unit offset and timing generator circuits 106 of rows {2, 10, 18, 26, . . . } could use two unit offsets, and so on.
In the previous illustrative example, the design point established 120 MHz as the SPAR enable frequency and 16 offsets per period of that waveform. In such a case as this, each unit offset would be 1/(16*120e6)=520 psec. So, in this manner, timing apertures created by timing generators 106, one-per-row, could create row-based acquisitions separated by 520 psec, relative to laser enable.
The primary advantages of creating row-based timing are two-fold. First, since there are logic gates in pixel 104, switching events of these gates create supply transients caused by switching current against non-trivial supply impedance. When timing generator circuits 106 are out of phase, the “spread out” the switching transients on the supply wires and cause the supply transient deflections (a.k.a. “supply noise”) to be “flatter”—overall lower in amplitude. Keeping the digital supply lines quieter leads to improved immunity of SPAD circuits to coupled noise (which in turn could increase dark counts due to digital supply line induced events). A second advantage of implementing different offsets per row relates to potentially shared resources. For example, some aspects of the pixel 104 blocks (for example, parts of the histogram) might be shared between pixels, perhaps across row boundaries. When the timing generator circuits 106 implement offset timing, then interleaved timing is created that could allow for some resources or parts of resources to be shared (physically, logically, or electrically) between pixels. This in turn could create other implementation advantages related to pixel density, etc.
Some elements within pixel 104 can be shared. For example, it's possible for a single histogram circuit which could comprise SRAM elements, could be shared between multiple pixels. In some embodiments, sharing circuits such as the histogram circuit, could enable higher pixel densities due to overhead area associated with such circuits. Thus, some aspects of pixel 104 could be virtualized and physically located either within or outside of the physical pixel area on a given ROIC.
Based on the disclosed embodiments, by electrically controlling the enablement of the SPAD subcircuit 108, it is possible to correctly measure the return energy of the reflected laser pulse in time domain.
In an embodiment, the histogram memory circuit 110 has two banks of memory, allowing it to acquire data and transmit data simultaneously. In this embodiment, the laser enable circuit 114 and pixel 104 timing generator circuit 106 may not need to pause for the actions of the Video timing generator circuit 112.
The disclosure has been described in an illustrative manner, and it is to be understood that the terminology which has been used is intended to be in the nature of words of description rather than of limitation. Many modifications and variations of the present disclosure are possible in light of the above teachings, and the disclosure may be practiced otherwise than as specifically described.
