Patent Application
20250176285
Example embodiments of the present disclosure relate generally to light detection, and more particularly to light detecting pixels.
Light detecting pixels are used in various technologies for example in three-dimensional (3D) and two-dimensional (2D) imaging systems. New developments in the technologies that use light detecting pixels require the pixels to have improved performance. Applicant has identified many technical challenges and difficulties associated with light detecting pixels. Through applied effort, ingenuity, and innovation, Applicant has solved problems related to light detecting pixels by developing solutions embodied in the present disclosure, which are described in detail below.
Various embodiments described herein relate to systems, apparatuses, products, and methods for light detection. In various embodiments, a pixel for detecting light is provided. In various embodiments, the pixel includes a substrate configured to generate one or more carriers in response to an incident light beam; a first vertical gate and a second vertical gate disposed inside the substrate, wherein the first and second vertical gates are configured to direct the one or more carriers to a transfer zone of the substrate; and a first planar gate and a second planar gate disposed on the substrate, wherein the first and second planar gates are configured to direct the one or more carriers from the transfer zone to a first sensing node or a second sensing node.
In various embodiments, the pixel includes a first vertical gate input electronically coupled to the first vertical gate and configured to receive a first vertical gate control signal; a second vertical gate input electronically coupled to the second vertical gate and configured to receive a second vertical gate control signal; a first planar gate input electronically coupled to the first planar gate and configured to receive a first planar gate control signal; and a second planar gate input electronically coupled to the second planar gate and configured to receive a second planar gate control signal, wherein the first and second planar vertical gates are configured to direct the one or more carriers to the first sensing node or the second sensing node using the first and second planar gate control signals.
In various embodiments, the first and second vertical gates are configured to be activated using the first and second vertical gate control signals and direct the one or more carriers to the transfer zone when activated; the first planar gate is configured to be activated using the first planar gate control signal and direct the one or more carriers to the first sensing node when activated; and the second planar gate is configured to be activated using the second planar gate control signal and direct the one or more carriers to the second sensing node when activated.
In various embodiments, the first and second vertical gates are configured to be activated concurrently; the first planar gate is configured to be activated when the second planar gate is deactivated; and the second planar gate is configured to be activated when the first planar gate is deactivated. In various embodiments, the first and second vertical gate control signals are DC voltages, and the first and second planar gate control signals include periodic waveforms and are complements of each other.
In various embodiments, the pixel includes a third vertical gate disposed inside the substrate; a fourth vertical gate disposed inside the substrate, wherein the first, second, third, and fourth vertical gates are configured to direct the one or more carriers to the transfer zone; a third vertical gate input electronically coupled to the third vertical gate and configured to receive a DC third gate control signal; a fourth vertical gate input electronically coupled to the fourth vertical gate and configured to receive a DC fourth vertical gate control signal; a third planar gate disposed on the substrate and configured to direct the one or more carriers to a third sensing node when the third planar gate is activated; a fourth planar gate disposed on the substrate, wherein the fourth planar gate is configured to direct the one or more carriers to a fourth sensing node when the fourth planar gate is activated; a third planar gate input electronically coupled to the third planar gate and configured to receive a third planar gate control signal; and a fourth planar gate input electronically coupled to the fourth planar gate and configured to receive a fourth planar gate control signal, wherein the first, second, third and fourth planar gates control signals include periodic waveforms and are spaced with a 90° phase shift with respect to each other.
In various embodiments, the pixel includes a first deep insulation trench on a first side of the substrate; and a second deep insulation trench on a second side of the substrate, wherein the first and second deep insulation trenches are configured to create a pinning potential at the substrate to deplete the substrate.
In various embodiments, the first planar gate and the second planar gate are configured to be activated alternatively using the first planar gate control signal and the second planar gate control signal, wherein the first planar gate control signal is a complement of the second planar gate control signal at a given time; the first and second vertical gates are configured to be activated using the first and second vertical gate control signals; and the pixel is configured to determine an indirect time of flight (iToF).
In various embodiments, the first vertical gate and the second vertical gate are configured to be deactivated simultaneously, and the first planar gate and the second planar gate are configured to be deactivated simultaneously for a first period of time; the first vertical gate and the second vertical gate are configured to be activated, and the first or the second planar gates are configured to be activated for a second period of time; and the pixel is configured to provide two-dimensional imaging.
In various embodiments, a pixel is provided. The pixel may include a substrate configured to generate one or more carriers in response to an incident light beam; a first vertical gate and a second vertical gate disposed inside the substrate, wherein the first and second vertical gates are configured to direct the one or more carriers towards the first and second vertical gates; a first planar gate input electronically coupled to a first planar gate and configured to receive a first planar gate control signal; and a second planar gate input electronically coupled to a second planar gate and configured to receive a second planar gate control signal, wherein the first and second planar gates are configured to direct the one or more carriers to a first capacitor or a second capacitor using the first and second gate control signals.
In various embodiments, the first planar gate is configured to be activated using the first gate control signal and direct the one or more carriers to the first capacitor when activated; and the second planar gate is configured to be activated using the second planar gate control signal and direct the one or more carriers to the second capacitor when activated, wherein the first and second planar gates and the first and second vertical gates are disposed in proximity of a same surface of the substrate.
In various embodiments, the first planar gate is deactivated when the second planar gate is activated; the second planar gate is deactivated when the first planar gate is activated; and the first and second planar gate control signals include periodic waveforms and are complements of each other.
A method is provided by various embodiments of the present disclosure. The method may include disposing a first vertical gate and a second vertical gate inside a substrate, wherein the first and second vertical gates are configured to direct one or more carriers to a transfer zone of the substrate, wherein the one or more carriers are generated inside the substrate in response to an incident light beam; and disposing a first planar gate and a second planar gate on the substrate, wherein the first and second planar gates are configured to direct the one or more carriers from the transfer zone to a first sensing node or a second sensing node.
The method may include configuring a first vertical gate input to receive a first vertical gate control signal, wherein the first vertical gate input is electronically coupled to the first vertical gate; configuring a second vertical gate input to receive a second vertical gate control signal, wherein the second vertical gate input is electronically coupled to the second vertical gate; configuring a first planar gate input to receive a first planar gate control signal, wherein the first planar gate input is electronically coupled to the first planar gate; configuring a second planar gate input to receive a second planar gate control signal, wherein the second planar gate input is electronically coupled to the second planar gate, wherein the first and second planar gates are configured to direct the one or more carriers to the first sensing node or the second sensing node using the first and second planar gate control signals.
In various embodiments, the method includes configuring the first and second vertical gates to be activated using the first and second vertical gates control signals, wherein the first and second vertical gates direct the one or more carriers to the transfer zone when the first and second vertical gates are activated; configuring the first planar gate to be activated using the first planar gate control signal and direct the one or more carriers to the first sensing node when the first planar gate is activated; and configuring the second planar gate to be activated using the second planar gate control signal and direct the one or more carriers to the second sensing node when the second planar gate is activated.
In various embodiments, the method includes configuring the first planar gate to be deactivated when the second planar gate is activated; configuring the second planar gate to be deactivated when the first planar gate is activated. In various embodiments, the method includes disposing a first deep insulation trench on a first side of the substrate; and disposing a second deep insulation trench on a second side of the substrate, wherein the first and second deep insulation trenches are configured to create a pinning potential at the substrate to deplete the substrate.
In various embodiments, the method includes activating the first vertical gate using the first vertical gate control signal, wherein the first vertical gate control signal is a DC voltage; and activating the second vertical gate using the second vertical gate control signal, wherein the second vertical gate control signal is a DC voltage.
In various embodiments, the method includes electronically coupling the first sensing node with a first supplemental capacitor; electronically coupling the second sensing node with a second supplemental capacitor; and configuring the first and second supplemental capacitors to determine an indirect time of flight or a two-dimensional density image using a first charge values of the first supplemental capacitor and a second charge value of the second supplemental capacitor.
In various embodiments, the method includes disposing a third vertical gate inside the substrate; disposing a fourth vertical gate inside the substrate, wherein the first, second, third and fourth vertical gates are configured to direct the one or more carriers to the transfer zone of the substrate; disposing a third planar gate on the substrate, wherein the third planar gate is configured to direct the one or more carriers to a third sensing node when the third planar gate is activated; disposing a fourth planar gate on the substrate, wherein the fourth planar gate is configured to direct the one or more carriers to a fourth sensing node when the fourth planar gate is activated; electronically coupling a third planar gate input to the third planar gate to receive a third planar gate control signal; and electronically coupling a fourth planar gate input to the fourth planar gate to receive a fourth planar gate control signal, wherein the first, second, third and fourth planar gates control signals include periodic waveforms and are spaced with a 90° phase shift with respect to each other.
The above summary is provided merely for purposes of summarizing some example embodiments to provide a basic understanding of some aspects of the disclosure. Accordingly, it will be appreciated that the above-described embodiments are merely examples and should not be construed to narrow the scope or spirit of the disclosure in any way. It will also be appreciated that the scope of the disclosure encompasses many potential embodiments in addition to those here summarized, some of which will be further described below.
Having thus described certain example embodiments of the present disclosure in general terms, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein:
Embodiments of the present disclosure will now be described more fully herein with reference to the accompanying drawings, in which some, but not all, embodiments of the disclosure are shown. Indeed, various embodiments of the disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Like reference numerals refer to like elements throughout.
The phrases “in one embodiment,” “according to one embodiment,” “in some embodiments,” “In various embodiments” and the like generally mean that the particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present disclosure, and may be included in more than one embodiment of the present disclosure (importantly, such phrases do not necessarily refer to the same embodiment).
The word “example” or “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations.
If the specification states a component or feature “may,” “can,” “could,” “should,” “would,” “preferably,” “possibly,” “typically,” “optionally,” “for example,” “often,” or “might” (or other such language) be included or have a characteristic, that a specific component or feature is not required to be included or to have the characteristic. Such a component or feature may be optionally included in some embodiments, or it may be excluded.
The term “electronically coupled,” “electronically coupling,” “electronically couple,” “in communication with,” “in electronic communication with,” or “connected” in the present disclosure refers to two or more elements or components being connected through wired means and/or wireless means, such that signals, voltage/current, data and/or information may be transmitted to and/or received from these elements or components.
Various embodiments of the present disclosure are directed to improved systems, apparatuses, products, and methods for light detection for example by using improved light detection systems. In various embodiments, the light detection system may be used in 3D imaging, for example using indirect Time of Flight (iToF) measurement.
In 3D imaging, a distance to an object may be determined. An approach to measure a distance to an object is Time of Flight (ToF) measurement. In ToF systems, a time of propagation of a light beam from an emitter to an object and back to a detector is measured. Using, the speed of light and the propagation time, the distance to the object may be measured.
In indirect Time of Flight (iToF) systems, the distance to an object is measured indirectly using a phase shift in the received light beam with respect to the emitted light beam.
Referring now to
To determine a phase shift between the reflected light beam and the emitted light beam, the pixel 112 may reconstruct a sine wave of the reflected light beam 110 after it is detected by the pixel.
To reconstruct the sine wave, the pixel 112 samples the detected light beam. When the light beam is received by the pixel 112, the pixel generates electron carriers (e) and holes (h). The carriers are sampled using the switches S1 and S2 and are directed to a corresponding sensing node SN1 or SN2 for detection.
The detected carriers at the sensing nodes SN1 and SN2 charge a corresponding capacitor. For example, the sensing node SN1 charges first capacitor 122 and the sensing node SN2 charges the second capacitor 124. A controller 114 may compare the charges stored at the capacitors to reconstruct the phase value of the reflected light beam.
The sensing nodes SN1 and SN2 may be floating nodes and a voltage of the sensing nodes may need to be reset after each detection cycle to prepare for another acquisition of charges and measurement. The switches 116 and 118 may reset the voltage to VDC using the Reset signals.
In some examples, emitted light beams may be in the near infrared (NIR) wavelength range having a wavelength in the range of 800-1100 nm, for example 940 nm. In some examples, emitted light beams may be in the short-wave infrared (SWIR) wavelength range having a wavelength in the range of 1100nm-3000 nm. Therefore, a suitable material in pixel 112 may be used to detect light beams in the corresponding wavelength range. For example, silicon has a good absorption in the NIR wavelength range and may be used in pixel 112 used for iToF and other imaging systems. Other materials such as Ge, InGaAs may be used in the SWIR wavelength range.
Referring now to
As the light beam is incident on the substrate 202, carriers are generated in the substrate 202. The P-N junction 208 creates an electrostatic potential gradient that transfers the carriers to the top of the pixel. By toggling between activation of the first planar gate 204 and the second planar gate 206, the charges are driven to the first sensing node 212 or the second sensing node 214. The first and second planar nodes may be activated using an AC signal VAC.
The first and second sensing nodes may be electronically coupled to an N+ region of the semiconductor. The N+ region may have an N type impurity dopant with high concentration. In an example, the N+ region may reduce contact resistance to the sensing node. For example, the N+ region may be an N fuse diffusion made by Arsenic or phosphorus doping.
Referring now to
In various embodiments, the pixel 300 includes a first vertical gate 334 and a second vertical gate 336 disposed inside the substrate 302. The first and second vertical gates may be configured to direct the one or more carriers generated in response to the incident light beam, to a higher zone, for example an integration zone 308 of the substrate. In various embodiments, a higher zone may refer to a zone further away from the surface of the substrate that receives the incident light beam. In various embodiments, the first and second vertical gates are configured to direct the one or more carriers to a transfer zone 309 of the substrate. The transfer zone 309 may be higher than the integration zone 308.
In various embodiments, the pixel 300 includes a first planar gate 304 and a second planar gate 306. In various embodiments, the first planar gate 304 and the second planar gate 306 are disposed on the substrate 302. The first planar gate 304 and the second planar gate 306 may be fabricated by depositing a layer of silicon oxide and a conductive material such as doped poly-silicon or metals like Al, W, Ag, etc.
In example embodiments, when operating in the NIR wavelength range, the height of the substrate may be between 5-12 micrometers. In example embodiments, the depth of the first vertical gate 334 and the second vertical gate 336 may be between 0.3 and 2 micrometers for example 1 micrometer. In example embodiments, if a material other than silicon with higher absorption is used, the height of the substrate may be smaller. In various embodiments, generally the height of the vertical gate may be between around 5% to 30% of the substrate height.
In various embodiments, the first and second vertical gates, and the first and second planar gates are used for an efficient transfer of the carriers from the substrate 302 to a first sensing node 310 and a second sensing node 312.
In various embodiments, the pixel 300 includes a first vertical gate input 344 electronically coupled to the first vertical gate and configured to receive a first vertical gate signal. The pixel 300 may include a second vertical gate input 346 electronically coupled to the second vertical gate and configured to receive a second vertical gate signal. In various embodiments, the first and second vertical gates are configured to be activated using the first and second vertical gate signals and direct the one or more carriers to the transfer zone when activated. In various embodiments, the first and second vertical gates may be activated concurrently. The first and second vertical gate control signals are DC voltages. In various embodiments, the same DC voltage may be applied to all the vertical gates.
In various embodiments, the first planar gate 304 and the second planar gate 306 are activated using a first planar gate control signal applied to a first planar gate input 314 and a second planar gate control signal applied to a second planar gate input 316. In various embodiments, the first and second vertical gates are configured to direct the one or more carriers to the first sensing node 310 or the second sensing node 312 using the first and second planar gate control signals.
For example, by activating the vertical gates, the one or more carriers may be directed to the transfer zone 309. In various embodiments, a potential in zone 309 may also generated due to an adequate doping profile of the substrate and also by potentials applied to deep insulation trenches 324 and 326 as further described below. By alternatively activating the first and second planar gates, an electrical potential is created in the substrate 302 and the one or more carriers are directed from the transfer zone 309 to the corresponding sensing node. For example, when the first planar gate 304 is activated, the carriers are directed in a direction towards the first planar gate and to the first sensing node. When the second planar gate 306 is activated, the carriers are directed in a direction towards the second planar gate and to the second sensing node.
In example embodiments, the pixel 300 directs the carriers to the corresponding sensing node without a need for the P-N junction created by a deep N implantation for example the N-well as described with respect to pixel 200. By not requiring the N-well, various embodiments provide a reduction of process variability in manufacturing the pixel while increasing transfer efficiency of carriers to the sensing nodes. Reducing process variability in manufacturing a pixel may reduce mismatch and/or inconsistencies among various pixels in a pixel array or matrix.
In various embodiments, the first planar gate is deactivated when the second planar gate is activated, and the second planar gate is deactivated when the first planar gate is activated. The planar gates may be activated using periodic signals generated for example by a voltage and/or current source 320. The voltage source 320 may generate the first planar gate control signal and the second planar gate control signal. The first and second planar gate control signals may have periodic waveforms and may be complements of each other. For example, at a given time, the first planar gate control signal applied to the first planar gate input may have a high value and the second planar gate control signal applied to the second planar gate input would have a low value.
In example embodiments, as compared to pixel 200, the pixel 300 provides a more homogenous electrostatic potential in the substrate with a gradient towards the vertical gates and then towards the corresponding sensing node when the corresponding planar gate is activated.
In various embodiments, the first and second sensing nodes are floating junctions, and their resulting signal will vary as carriers are directed to each sensing nodes. This may be because each sensing node has an intrinsic capacitance, and when the carriers are transferred to the corresponding sensing node, a charge of the intrinsic capacitance and its corresponding voltage may change. In various embodiments, the intrinsic capacitance of each sensing node is supplemented for example by using a supplemental capacitance which may be provided using an external capacitor. In various embodiments, when the pixel 300 functions as an iToF pixel, the charges accumulated on each sensing node, and/or the supplemental capacitor electronically coupled in parallel to the sensing node, is measured for the iToF determination as for example described with reference to
In various embodiments, by toggling between the activation of the planar gates, the pixel alternates between charge collection at the first and second sensing nodes. By doing so over a period of time, the controller 114 may integrate the first charge collection on the first sensing node and the second charge collection at the second sensing node. Using the integration values, a reconstruction of the phase shift that the beam has suffered when it was reflected from an object and received by the pixel is determined.
In various embodiments, by alternating faster between charge collections at different sensing nodes, the pixel 300 may provide a more precise measurement of the phase shift of the reflected signal the iToF determination. In example embodiments, pixel 300 enables higher frequency for activation and deactivation of the planar gates and therefore a faster alternation between charge collections at the first and second sensing nodes for a more precise iToF measurement as for example compared with pixel 200.
In various embodiments, by etching the vertical gates deep in the substrate in the pixel 300, a higher driving potential is created in the substrate volume and the carriers are directed to the transfer zone. Therefore, subsequently, the carriers are directed to the sensing node more efficiently with a lower amplitude requirement for the planar gate control signals.
In various embodiments, the pixel 300 includes a first deep insulation trench 324 and a second deep insulation trench 326. The deep insulation trenches may extend as deep as the substrate. In various embodiments, the substrate may be fully surrounded with multiple deep insulation trenches.
In various embodiments, the first deep insulation trench 324 and the second deep insulation trench 326 create a pinning potential at the substrate to deplete the substrate. In various embodiments, DC voltage signals may be applied to the deep insulation trenches to create the pinning potential. For example, a first deep insulation trench DC bias voltage may be applied to the first deep insulation trench 324 and a second deep insulation trench DC bias voltage may be applied to the second deep insulation trench 326.
In example embodiments, using the vertical gates and the deep insulation trenches, a uniform electrostatic field may be generated in the substrate from the bottom to the top, in order to direct the carriers to the transfer zone, and then using the planar gates, to the right direction near the top to the corresponding sensing node depending on which planar gate is activated.
In various embodiments, a lateral gradient of electrostatic field is created by the deep insulation trenches to deplete the substrate volume and a vertical gradient of electrostatic field is created by the vertical gates upwards and to a sensing node corresponding to a vertical gate that is activated at a given time.
In various embodiments, the deep insulation trenches and the vertical gates are made with a dielectric liner (e.g. SiO2 or HK materials, Hf02, Al2O3, etc.) then filled with a conductive material (e.g. doped poly-silicon or metal such as Al, W, Ag, etc.). In various embodiments, the substrate is made from silicon, Ge, or InGaAs, etc., as previously described.
In various embodiments, different arrangements for the vertical gates and the planar gates may be possible. Referring now to
Referring now to
In various embodiments, the pixel 300 may operate in a 3D imaging or iToF mode. When in the iToF mode, the first vertical gate and the second vertical gate of the are configured to be activated to direct the carriers to the transfer zone. In various embodiments, the first planar gate and the second planar gate of the pixel may be configured to be activated alternatively using the first planar gate control signal and the second planar gate control signal. In various embodiments, the first planar control signal is a complement of the second planar control signal at a given time.
In various embodiments, when the first planar gate is deactivated, it creates a low gate acting as a barrier between the carriers in a transfer zone of the substrate (for example transfer zone 309 in
In example embodiments, by not using a P-N junction or an N-well in the integration zone, the activation and/or deactivation of the first and second planar gates in the pixel 300 may be performed at higher frequencies and using lower amplitude. Therefore, the accuracy of the measurement may increase, and a power consumption of the pixel may decrease.
In various embodiments, the pixel 300 may operate in a 2D imaging, for example using light intensity acquisition. When operating in 2D imaging, the first vertical gate and both planar gates may be configured to be deactivated simultaneously for a first period of time which may be referred to as the integration time. During the integration time, the carriers generated in response to the incident light beam may be accumulated in the integration zone of the substrate. In various embodiments, the barrier created during the integration time may be a stronger barrier than the barrier created during the iToF mode, to allow for a larger accumulation of charges for 2D imaging.
In various embodiments, the first and second vertical gates and either the first planar gate or the second planar gate may then be activated for a second period of time which may be referred to as the readout time. During the readout time, an intensity signal for the pixel is generated which may be a representative of a 2D image pixel. In various embodiments, vertical gates are activated and deactivated using the first and second vertical gate control signals and planar gates are activated and deactivated using the first and second planar gate control signals.
During the readout time, any of the first or second vertical carriers may be activated. When a vertical gate is activated, it creates a high gate acting as a potential gradient directing the integrated carriers to the corresponding sensing node for a readout representing the captured 2D image in the pixel.
In example embodiments, by not using P-N junction or an N-well in the integration zone, a larger integration of carriers may be possible in the integration zone. Using the vertical gates that are deeply implanted in the pixel may allow providing gates with a low biasing, therefore creating significant low gate barriers allowing for storing a significant number of carriers in the volume of the pixel.
Therefore, in example embodiments, by simply varying a biasing condition of the vertical gates and planar gates using the vertical and planar gate control signals, the pixel may operate in the 3D or 2D imaging modes.
Referring now to
In various embodiments, the cross section of the vertical gates may have various shapes. For example, one or more vertical gates may have an L-shaped cross section. The L-shaped cross section may provide a strong and/or homogenous electrostatic field in the substrate for directing the carriers to the transfer zone. In various embodiments, the cross section of the vertical gates may have any other geometrical shapes such as square, rectangular, trapezoidal, circular, oval, etc., and/or any combination thereof.
In various embodiments, the pixel 500 includes a first planar gate 504, a second planar gate 506, a third planar gate 508, and a fourth planar gate 510 disposed on the substrate 502. In various embodiments, the first, second, third, and fourth planar gates are configured to direct one or more carriers from the transfer zone to a first sensing node 514, a second sensing node 516, a third sensing node 518, or a fourth sensing node 520. In various embodiments, each planar gate is configured to transfer the carriers to a corresponding sensing node. For example, the first planar gate may be configured to direct the carriers to the first sensing node, the second planar gate may be configured to direct the carriers to the second sensing node, the third planar gate may be configured to direct the carriers to the third sensing node, and the fourth planar gate may be configured to direct the carriers to the fourth sensing node. In various embodiments, the first planar gate may be disposed in proximity of the first sensing node, the second planar gate may be disposed in proximity of the second sensing node, the third planar gate may be disposed in proximity of the third sensing node, and the fourth planar gate may be disposed in proximity of the fourth sensing node. In various embodiments, each sensing node may be disposed on and/or be electronically coupled to a corresponding N+ region.
In various embodiments, the vertical gates, the planar gats, and the sensing nodes may be arranged in various fashion in the substrate 502. For example, the vertical gates and the planar gates (or the sensing nodes) may be generally arranged on a square shape 540. In other examples, the vertical gates and the planar gates (or the sensing nodes) may be arranged on various other shapes such as circular, oval, rectangular, etc. In example embodiments, by arranging the vertical gates and the planar gates (or the sensing nodes) as described herein, an efficiency of the transfer of the carries from the substrate to a corresponding sensing node increases.
In various embodiments, the planar gates may have various cross-sectional shapes. For example, at least one of or all of the first, second, third, or forth planar gates may have various cross section shapes around the corresponding sensing node and may fully or partially surround the corresponding sensing node. In various embodiments, at least one or all of the planar gates may partially surround the sensing node, for example by having a C cross sectional shape, an F cross sectional shape, or an h cross sectional shape. In various embodiments, at least one or all of the planar gates may fully surround the corresponding sensing node for example by having a circular (e.g., an O) cross sectional shape or a b cross sectional shape surrounding the corresponding sensing node. In various embodiments, when more than one planar gate correspond to a sensing node, the planar gates fully or partially surrounding a sensing nodes may be concentric of off-centered with respect to each other.
In various embodiments, each vertical gate is electronically coupled to a vertical gate input and is configured to receive a vertical gate control signal. The vertical gate control signals may be DC voltages.
In various embodiments, each planar gate is electronically coupled to a planar gate input and is configured to receive a corresponding planar gate control signal. Each planar gate control signal may include a periodic waveform to periodically enable and disable the corresponding planar gate. In various embodiments, when using four planar gates and corresponding four sensing nodes, the planar gate control signals may be 90° offset from each other. In example embodiments, doing so provides a more granular of transferring carriers to a corresponding sensing node. Therefore, the pixel 500 may for example provide a 4-tap per period sampling of an incident reflected beam for a more accurate iToF determination.
In various embodiments, the pixel may include more than four vertical, planar, and/or sensing nodes and may be arranged in various forms, for example in a similar fashions described above. When using more sensing nodes, a higher tap per period sampling may be performed in an iToF determination.
In various embodiments, the pixel may include two or more planar gates per sensing nodes. For example, two or more planar gates that correspond to a sensing node may be disposed in proximity of the sensing node and direct the carriers from the transfer zone to the corresponding sensing node. For example, when a first and/or second planar gates is activated using the first and/or second planar gate control signals, the carriers are directed to a first sensing node. And, for example, when a third and/or fourth planar gates are activated using a third and/or fourth planar gate control signals, the carriers are directed to a second sensing node. In various embodiments, all the vertical gates may be activated to direct the carriers to the transfer zone.
In various embodiments, the pixel 500 may include deep insulation trench(es) on various sides of the substrate. The deep insulation trenches may be configured to create a pinning potential at the substrate to deplete the substrate.
In example embodiments, the vertical gates provided herein may have a higher driving capability in the whole volume of the pixel substrate than planar gates. This may reduce the amplitude requirement for the signals applied to the planar gates, because the vertical gates first direct the carriers to the transfer zone closer to the planar gates. Therefore, a small voltage for the planar gate control signals may be sufficient to provide a transfer of carriers to the corresponding sensing node. Hence an efficiency of the pixel may be increased by requiring a lower amplitude for the planar gate control signals.
In example embodiments, using vertical gates and their higher driving capability may make it possible to increase the volume of the substrate without degrading the frequency performance of the of the pixel. For example, using vertical gates increases the quantum efficiency (QE) of the pixel by increasing the thickness of the volume of the substrate silicon without degrading the performance because of the uniform and strong electrostatic field gradient generated by the vertical gates and a strong driving force on carriers caused by it. In example embodiments, the QE may represent a ratio of the total measured carriers by the sensing nodes of the pixel over the total incident photons on the pixel. In example embodiments, using vertical gates and planar gates as described herein also may maintain a high demodulation contrast (DMC) in the pixel. DMC may indicate an estimation of a rate of collection and/or detection of photons by the pixel at the operation frequency.
Referring now to
In various embodiments, at step 602, the method 600 disposes a first vertical gate and a second vertical gate inside a substrate, for example substrate 302. In various embodiments, the first and second vertical gates are configured to direct one or more carriers generated in the substrate to a transfer zone of the substrate. The one or more carriers may be generated inside the substrate in response to an incident light beam.
In various embodiments, at step 604, the method 600 disposes a first planar gate and a second planar gate on the substrate. The first and second planar gates may be configured to direct the one or more carriers from the transfer zone to a first sensing node or a second sensing node.
In various embodiments, at step 606, the method 600 configures a first vertical gate input to receive a first vertical gate control signal. The first vertical gate input may be electronically coupled to the first vertical gate. In various embodiments, at step 608, the method 600 configures a second vertical gate input to receive a second vertical gate control signal. The second vertical gate input may be electronically coupled to the second vertical gate. In various embodiments, the first and second vertical gate control signals may be DC voltages.
In various embodiments, at step 610, the method 600 configures a first planar gate input to receive a first planar gate control signal. The first planar gate input may be electronically coupled to the first planar gate. In various embodiments, at step 612, the method 600 may configure a second planar gate input to receive a second planar gate control signal. The second planar gate input may be electronically coupled to the second planar gate. In various embodiments, the first and second planar gates are configured to direct the one or more carriers to the first sensing node or the second sensing node using the first and second planar gate control signals.
In various embodiments, the first and second planar gates are configured to direct the one or more carriers to a first capacitor or a second capacitor using the first and second planar gate control signals. In example embodiments, the first and second sensing nodes have intrinsic capacitance and are the first and second capacitors. In various embodiments, the capacitance of the first and second sensing node are supplemented with supplemental capacitors, for example capacitor 122 may be a first supplemental capacitor electronically coupled to the first sensing node and the capacitor 124 may be a second supplemental capacitor electronically coupled to the second sensing node as illustrated in
Referring now to
In various embodiments, at step 702, the method 700 configures the first and second vertical gates to be activated using the first and second vertical gates control signals. The first and second vertical gates may direct the one or more carriers to the transfer zone when the first and second vertical gates are activated. In various embodiments, at step 704, the method 700 configures the first planar gate to be activated using the first planar gate control signal and direct the one or more carriers to the first sensing node when the first planar gate is activated.
In various embodiments, at step 706, the method 700 configures the second planar gate to be activated using the second planar gate control signal and direct the one or more carriers to the second sensing node when the second planar gate is activated.
In various embodiments, at step 708, the method 700 configures the first planar gate to be deactivated when the second planar gate is activated. In various embodiments, at step 710, the method 700 configures the second planar gate to be deactivated when the first planar gate is activated.
In various embodiments, a method may dispose a first deep insulation trench on a first side of the substrate, and dispose a second deep insulation trench on a second side of the substrate. The first and second deep insulation trenches may be configured to create a pinning potential at the substrate to deplete the substrate.
In various embodiments, a method may activate the first vertical gate using the first vertical gate control signal. In various embodiments, the method may activate the second vertical gate using the second vertical gate control signal. The first and second vertical gate control signals may be DC voltages.
In various embodiments, a method may electronically couple the first sensing node with a first supplemental capacitor, and electronically couples the second sensing node with a second supplemental capacitor. In various embodiments, the method determines indirect time of flight or a two-dimensional density image using a first charge values of the first supplemental capacitor and a second charge value of the second supplemental capacitor.
In various embodiments, a method may dispose a third vertical gate inside the substrate. The method may dispose a fourth vertical gate inside the substrate. The first, second, third and fourth vertical gates may be configured to direct the one or more carriers to the transfer zone of the substrate.
In various embodiments, a method may dispose a third planar gate on the substrate, wherein the third planar gate is configured to direct the one or more carriers to a third sensing node when the third planar gate is activated. The method may dispose a fourth planar gate on the substrate, wherein the fourth planar gate is configured to direct the one or more carriers to a fourth sensing node when the fourth planar gate is activated.
In various embodiments, a method may electronically couple a third planar gate input to the third planar gate to receive a third planar gate control signal. The method may electronically couple a fourth planar gate input to the fourth planar gate to receive a fourth planar gate control signal. In various embodiments, the first, second, third and fourth planar gates signals may include periodic waveforms and are spaced with a 90° phase shift with respect to each other.
It should be readily appreciated that the embodiments of the systems, apparatus, and methods described herein may be configured in various additional and alternative manners in addition to those expressly described herein.
The light detection system 800 can include a computing apparatus 810 and/or one or more light detection pixels 820 communicatively coupled to the computing apparatus 810 using one or more wired and/or wireless communication techniques. In general, the terms computing apparatus, computer, system, device, entity, and/or similar words used herein interchangeably can refer to, for example, one or more computers, computing entities, desktops, mobile phones, tablets, notebooks, laptops, distributed systems, kiosks, input terminals, servers or server networks, blades, gateways, switches, processing devices, processing entities, controllers, control systems, set-top boxes, relays, routers, network access points, base stations, the like, and/or any combination of devices or entities adapted to perform the functions, operations, and/or processes described herein. Such functions, operations, and/or processes can include, for example, transmitting, receiving, operating on, processing, displaying, storing, determining, creating/generating, monitoring, evaluating, comparing, and/or similar terms used herein interchangeably. In one embodiment, these functions, operations, and/or processes can be performed on data, content, information, and/or similar terms used herein interchangeably. The computing apparatus 810 can include any computing device including, for example, a light detection processing apparatus configured to perform one or more steps/operations of one or more light detection techniques described herein. In some examples, the computing apparatus 810 may determine an indirect time of flight (iToF) as described herein. In some examples, the computing apparatus 810 may detect a 2D image as described herein. In some embodiments, the computing apparatus 810 can include and/or be in association with one or more mobile device(s), desktop computer(s), laptop(s), server(s), cloud computing platform(s), and/or the like. In some example embodiments, the computing apparatus 810 can be configured to receive and/or transmit light detection instructions, data, and/or the like between the one or more light detection pixels 820 to perform one or more steps/operations of one or more light detection techniques described herein.
The computing apparatus 810 can include, or be in communications with, one or more processing elements 802 (also referred to as processors, processing circuitry, digital circuitry, and/or similar terms used herein interchangeably) that communicate with other elements within the computing apparatus 810 via a bus, for example. As will be understood, the processing element 802 can be embodied in a number of different ways.
For example, the processing element 802 can be embodied as one or more complex programmable logic devices (CPLDs), microprocessors, multi-core processors, coprocessing entities, application-specific instruction-set processors (ASIPs), microcontrollers, and/or controllers. Further, the processing element 802 can be embodied as one or more other processing devices or circuitry. The term circuitry can refer to an entirely hardware embodiment or a combination of hardware and computer program products. Thus, the processing element 802 can be embodied as integrated circuits, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic arrays (PLAs), hardware accelerators, digital circuitry, and/or the like.
As will therefore be understood, the processing element 802 can be configured for a particular use or configured to execute instructions stored in volatile or non-volatile media or otherwise accessible to the processing element 802. As such, whether configured by hardware or computer program products, or by a combination thereof, the processing element 802 can be capable of performing steps or operations according to embodiments of the present disclosure when configured accordingly.
In one embodiment, the computing apparatus 810 can further include, or be in communication with, one or more memory elements 804. The one or more memory elements 804 can include non-volatile and/or volatile media. The memory elements 804, for example, can include non-volatile media (also referred to as non-volatile storage, memory, memory storage, memory circuitry and/or similar terms used herein interchangeably). In one embodiment, the non-volatile storage or memory can include one or more non-volatile storage or memory media, including, but not limited to, hard disks, ROM, PROM, EPROM, EEPROM, flash memory, MMCs, SD memory cards, Memory Sticks, CBRAM, PRAM, FeRAM, NVRAM, MRAM, RRAM, SONOS, FJG RAM, Millipede memory, racetrack memory, and/or the like.
As will be recognized, the non-volatile storage or memory media can store databases, database instances, database management systems, data, applications, programs, program modules, scripts, source code, object code, byte code, compiled code, interpreted code, machine code, executable instructions, and/or the like. The term database, database instance, database management system, and/or similar terms used herein interchangeably can refer to a collection of records or data that is stored in a computer-readable storage medium using one or more database models, such as a hierarchical database model, network model, relational model, entity-relationship model, object model, document model, semantic model, graph model, and/or the like.
In addition, or alternatively, the memory elements 804 can include volatile memory. For example, the computing apparatus 810 can further include, or be in communication with, volatile media (also referred to as volatile storage memory, memory storage, memory circuitry and/or similar terms used herein interchangeably). In one embodiment, the volatile storage or memory can also include one or more volatile storage or memory media, including, but not limited to, RAM, DRAM, SRAM, FPM DRAM, EDO DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, RDRAM, TTRAM, T-RAM, Z-RAM, RIMM, DIMM, SIMM, VRAM, cache memory, register memory, and/or the like.
As will be recognized, the volatile storage or memory media can be used to store at least portions of the databases, database instances, database management systems, data, applications, programs, program modules, scripts, source code, object code, byte code, compiled code, interpreted code, machine code, executable instructions, and/or the like being executed by, for example, the processing element 802. Thus, the databases, database instances, database management systems, data, applications, programs, program modules, scripts, source code, object code, byte code, compiled code, interpreted code, machine code, executable instructions, and/or the like can be used to control certain aspects of the operation of the computing apparatus 810 with the assistance of the processing element 802 and operating system.
As indicated, in one embodiment, the computing apparatus 810 can also include one or more communication interfaces 808 for communicating with various computing entities, such as by communicating data, content, information, and/or similar terms used herein interchangeably that can be transmitted, received, operated on, processed, displayed, stored, and/or the like. Such communication can be executed using a wired data transmission protocol, such as fiber distributed data interface (FDDI), digital subscriber line (DSL), Ethernet, asynchronous transfer mode (ATM), frame relay, data over cable service interface specification (DOCSIS), or any other wired transmission protocol. Similarly, the computing apparatus 810 can be configured to communicate via wireless external communication networks using any of a variety of protocols, such as general packet radio service (GPRS), Universal Mobile Telecommunications System (UMTS), Code Division Multiple Access 2000 (CDMA2000), CDMA2000 1X (1xRTT), Wideband Code Division Multiple Access (WCDMA), Global System for Mobile Communications (GSM), Enhanced Data rates for GSM Evolution (EDGE), Time Division-Synchronous Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), Evolved Universal Terrestrial Radio Access Network (E-UTRAN), Evolution-Data Optimized (EVDO), High Speed Packet Access (HSPA), High-Speed Downlink Packet Access (HSDPA), IEEE 802.9 (Wi-Fi), Wi-Fi Direct, 802.16 (WiMAX), ultra-wideband (UWB), infrared (IR) protocols, near field communication (NFC) protocols, Wibree, Bluetooth protocols, wireless universal serial bus (USB) protocols, and/or any other wireless protocol.
The light detection system 800 can include input/output circuitry for communicating with one or more users or other systems or devices. The input/output circuitry, for example, can include one or more interfaces for providing and/or receiving information from one or more users or other systems or devices of the light detection system 800 or otherwise. The input/output circuitry can be configured to receive user input or input from various other systems or devices through one or more of the interfaces of the light detection system 800.
Many modifications and other embodiments of the disclosures set forth herein will come to mind to one skilled in the art to which these disclosures pertain having the benefit of teachings presented in the foregoing descriptions and the associated drawings. Although the figures only show certain components of the apparatus and systems described herein, it is understood that various other components may be used in conjunction with the system. Therefore, it is to be understood that the disclosures are not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Moreover, the steps in the method described above may not necessarily occur in the order depicted in the accompanying diagrams, and in some cases one or more of the steps depicted may occur substantially simultaneously, or additional steps may be involved. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.
While various embodiments in accordance with the principles disclosed herein have been shown and described above, modifications thereof may be made by one skilled in the art without departing from the spirit and the teachings of the disclosure. The embodiments described herein are representative only and are not intended to be limiting. Many variations, combinations, and modifications are possible and are within the scope of the disclosure. Alternative embodiments that result from combining, integrating, and/or omitting features of the embodiment(s) are also within the scope of the disclosure. Accordingly, the scope of protection is not limited by the description set out above.
Additionally, the section headings used herein are provided for consistency with the suggestions under 37 C.F.R. 1.77 or to otherwise provide organizational cues. These headings shall not limit or characterize the disclosure(s) set out in any claims that may issue from this disclosure.
Use of broader terms such as “comprises,” “includes,” and “having” should be understood to provide support for narrower terms such as “consisting of,” “consisting essentially of,” and “comprised substantially of” Use of the terms “optionally,” “may,” “might,” “possibly,” and the like with respect to any element of an embodiment means that the element is not required, or alternatively, the element is required, both alternatives being within the scope of the embodiment(s). Also, references to examples are merely provided for illustrative purposes, and are not intended to be exclusive.
While this detailed description has set forth some embodiments of the present disclosure, the appended claims cover other embodiments of the present disclosure which differ from the described embodiments according to various modifications and improvements.
