This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2020-049455, filed on Mar. 19, 2020; the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a light detector, a light detection system, a lidar device, and a vehicle.
A light detector detects light incident on an element including a semiconductor region of a first conductivity type and a semiconductor region of a second conductivity type. It is desirable to reduce the dead time of the light detector.
According to one embodiment, a first semiconductor region of a first conductivity type, a light detector includes a first element, a second element, an insulating body, a first interconnect, and a second interconnect. The first element includes a second semiconductor region of the first conductivity type, and a third semiconductor region of a second conductivity type. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region, and contacts the second semiconductor region. The second element is arranged with the first element in a direction perpendicular to a first direction. The first direction is from the first semiconductor region toward the first element. The second element includes a fourth semiconductor region of the first conductivity type and a fifth semiconductor region of the second conductivity type. The fourth semiconductor region is provided on the first semiconductor region. An impurity concentration of the first conductivity type in the fourth semiconductor region is less than an impurity concentration of the first conductivity type in the second semiconductor region. The fifth semiconductor region is provided on the fourth semiconductor region, and contacts the fourth semiconductor region. The insulating body is provided between the first element and the second element. The first interconnect is electrically connected to the third semiconductor region. The second interconnect is electrically connected to the fifth semiconductor region.
Various embodiments are described below with reference to the accompanying drawings.
The drawings are schematic and conceptual; and the relationships between the thickness and width of portions, the proportions of sizes among portions, etc., are not necessarily the same as the actual values. The dimensions and proportions may be illustrated differently among drawings, even for identical portions.
In the specification and drawings, components similar to those described previously in an antecedent drawing are marked with like reference numerals, and a detailed description is omitted as appropriate.
In the embodiments described below, each embodiment may be implemented by inverting the p-type and the n-type of each semiconductor region.
As shown in
Here, a direction from the first semiconductor region 1 toward the first element 11 is taken as a first direction D1. Two mutually-orthogonal directions perpendicular to the first direction D1 are taken as a second direction D2 and a third direction D3. A direction that is perpendicular to the first direction D1 and oblique to the second and third directions D2 and D3 is taken as a fourth direction D4. In the description, the direction from the first semiconductor region 1 toward the first element 11 is called “up”, and the reverse direction is called “down”. These directions are based on the relative positional relationship between the first semiconductor region 1 and the first element 11 and are independent of the direction of gravity.
As shown in
The first element 11 includes a second semiconductor region 2 of the first conductivity type and a third semiconductor region 3 of a second conductivity type. The first conductivity type is one of a p-type or an n-type. The second conductivity type is the other of the p-type or the n-type. In the description hereinbelow, the first conductivity type is the p-type, and the second conductivity type is the n-type.
The third semiconductor region 3 is provided on the second semiconductor region 2 and contacts the second semiconductor region 2. A p-n junction is formed between the second semiconductor region 2 and the third semiconductor region 3. For example, the p-n junction surface is parallel to the second and third directions D2 and D3.
The first element 11 may further include a semiconductor region 6. The second semiconductor region 2 and the third semiconductor region 3 are provided on the semiconductor region 6. The second semiconductor region 2 is electrically connected to the electrode 21 via the semiconductor region 6, the first semiconductor region 1, and the conductive layer 22.
As shown in
The impurity concentration of the first conductivity type in the fourth semiconductor region 4 is less than the impurity concentration of the first conductivity type in the second semiconductor region 2. For example, the thickness in the first direction D1 of the second semiconductor region 2 is less than the thickness in the first direction D1 of the fourth semiconductor region 4. For example, the thickness in the first direction D1 of the fourth semiconductor region 4 is equal to the sum of the thickness in the first direction D1 of the second semiconductor region 2 and the thickness in the first direction D1 of the semiconductor region 6.
Voltages are applied between the second semiconductor region 2 and the third semiconductor region 3 and between the fourth semiconductor region 4 and the fifth semiconductor region 5 by controlling the potential of the electrode 21. For example, the first element 11 and the second element 12 function as avalanche photodiodes.
As shown in
For example, when viewed along the first direction D1, the shape of the p-n junction surface between the second semiconductor region 2 and the third semiconductor region 3 is different from the shape of the p-n junction surface between the fourth semiconductor region 4 and the fifth semiconductor region 5. When viewed along the first direction D1, the surface area of the p-n junction surface between the second semiconductor region 2 and the third semiconductor region 3 is greater than the surface area of the p-n junction surface between the fourth semiconductor region 4 and the fifth semiconductor region 5.
A portion of the first semiconductor region 1 is positioned under the first element 11 and the second element 12. Another portion of the first semiconductor region 1 is positioned under the insulating body 30. The p-type impurity concentration in the portion of the first semiconductor region 1 may be different from the p-type impurity concentration in the other portion of the first semiconductor region 1. For example, the p-type impurity concentration in the other portion of the first semiconductor region 1 may be greater than the p-type impurity concentration in the portion of the first semiconductor region 1.
The insulating body 30 is provided between the first elements 11 and between the first element 11 and the second element 12. For example, as shown in
The second semiconductor region 2 and the third semiconductor region 3 may contact the first insulating portion 31 or may be separated from the first insulating portion 31. When the second semiconductor region 2 and the third semiconductor region 3 are separated from the first insulating portion 31, a portion of the semiconductor region 6 is provided between the second semiconductor region 2 and the first insulating portion 31 and between the third semiconductor region 3 and the first insulating portion 31.
The fifth semiconductor region 5 may contact the first insulating portion 31 or may be separated from the first insulating portion 31. When the fifth semiconductor region 5 is separated from the first insulating portion 31, a portion of the fourth semiconductor region 4 is provided between the fifth semiconductor region 5 and the first insulating portion 31.
As shown in
The insulating layer 41 is provided on the first element 11, the second element 12, and the insulating body 30. The insulating layer 42 is provided on the insulating layer 41. The insulating layer 43 is provided on the insulating layer 42. The insulating layer 44 is provided on the insulating layer 43.
As shown in
The fifth semiconductor region 5 is electrically connected to the second interconnect 62. For example, a portion of the multiple fifth semiconductor regions 5 is electrically connected to the second interconnect 62 via a plug 62a and an interconnect 62b. Another portion of the multiple fifth semiconductor regions 5 is electrically connected to the second interconnect 62 via a plug 62c.
The electrical resistance of the first quenching part 51 is greater than the electrical resistances of the plug 61a, the interconnect 61b, the plug 61c, and the plug 61d. It is favorable for the electrical resistance of the first quenching part 51 to be not less than 50 kΩ and not more than 2 MΩ.
For example, at least a portion of the first quenching part 51 is provided on the semiconductor region 7 or the insulating body 30. The first quenching part 51 is not provided on the first element 11. Shielding by the first quenching part 51 of the light traveling toward the first element 11 can be suppressed thereby.
The first quenching part 51 is provided to suppress the continuation of the avalanche breakdown that has occurred due to light entering the first element 11. A voltage drop that corresponds to the electrical resistance of the first quenching part 51 occurs when avalanche breakdown occurs and a current flows in the first quenching part 51. The potential difference between the second semiconductor region 2 and the third semiconductor region 3 is reduced by the voltage drop, and the avalanche breakdown stops. The next light that is incident on the first element 11 can be detected thereby.
For example, the first element 11 operates in a Geiger mode in which a reverse voltage that is greater than the breakdown voltage is applied between the second semiconductor region 2 and the third semiconductor region 3 and between the fourth semiconductor region 4 and the fifth semiconductor region 5. By operating in the Geiger mode, a pulse signal that has a high gain and a short time constant is output.
As described above, a resistor that generates a large voltage drop may be provided as the first quenching part 51; conversely, instead of a resistor, a control circuit that blocks the current may be provided as the first quenching part 51. For example, the control circuit includes a comparator, a control logic part, and two switching elements. A known configuration called an active quenching circuit is applicable to the control circuit.
The first interconnect 61 and the second interconnect 62 extend along the second direction D2. For example, as shown in
The second interconnects 62 are separated from the first interconnects 61 and electrically isolated from the first interconnects 61. Therefore, the signal that is extracted from the first pad 71 can be different from the signal flowing through the second interconnects 62. The signal that is extracted from the second pad 72 can be different from the signal flowing through the first interconnects 61.
Examples of materials of the components will now be described.
The first semiconductor region 1, the second semiconductor region 2, the third semiconductor region 3, the fourth semiconductor region 4, the fifth semiconductor region 5, the semiconductor region 6, and the semiconductor region 7 include at least one semiconductor material selected from the group consisting of silicon, silicon carbide, gallium arsenide, and gallium nitride. Phosphorus, arsenic, or antimony may be used as the n-type impurity when these semiconductor regions include silicon. Boron or boron fluoride may be used as the p-type impurity.
The p-type impurity concentrations in the first semiconductor region 1, the fourth semiconductor region 4, the semiconductor region 6, and the semiconductor region 7 are, for example, not less than 1.0×1013 atoms/cm3 and not more than 1.0×1016 atoms/cm3. The p-type impurity concentration in the second semiconductor region 2 is, for example, not less than 1.0×1016 atoms/cm3 and not more than 1.0×1018 atoms/cm3. The n-type impurity concentrations in the third and fifth semiconductor regions 3 and 5 are, for example, not less than 1.0×1018 atoms/cm3 and not more than 1.0×1021 atoms/cm3.
The conductive layer 22 is, for example, a p-type semiconductor region. The conductive layer 22 includes a semiconductor material described above. The p-type impurity concentration in the conductive layer 22 is not less than 1.0×1017 atoms/cm3 and not more than 1.0×102′ atoms/cm3. Or, the conductive layer 22 may include a metal. For example, the conductive layer 22 includes at least one selected from the group consisting of aluminum, copper, titanium, gold, and nickel.
The insulating body 30 and the insulating layers 41 to 44 include insulating materials. For example, the insulating body 30 and the insulating layers 41 to 44 include silicon and one selected from the group consisting of oxygen and nitrogen. For example, the insulating body 30 and the insulating layers 41 to 44 include silicon oxide or silicon nitride. As shown in
The first quenching part 51 that is used as the resistor includes polysilicon as a semiconductor material. An n-type impurity or a p-type impurity may be added to the first quenching part 51.
The plugs 61a, 61c, 61d, 62a, and 62c include metal materials. For example, the plugs 61a, 61c, 61d, 62a, and 62c include at least one selected from the group consisting of titanium, tungsten, copper, and aluminum. The plugs 61a, 61c, 61d, 62a, and 62c may include a conductor made of a silicon compound or a nitride of at least one selected from the group consisting of titanium, tungsten, copper, and aluminum. As shown in
The electrode 21, the first interconnect 61, the interconnect 61b, the second interconnect 62, the interconnect 62b, the first pad 71, and the second pad 72 include at least one selected from the group consisting of copper and aluminum.
As shown in
As shown in
The resist 105 is stripped away as shown in
As shown in
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An insulating film 114 that has a thickness of 0.5 μm is formed by CVD. An insulating film 118 that has a thickness of 0.3 μm is formed by CVD. As shown in
As shown in
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As shown in
The back electrode 125 of the manufacturing processes described above corresponds to the electrode 21 of the light detector 100. The silicon substrate 100a corresponds to the conductive layer 22. A portion of the silicon epitaxial layer 101 and the implantation region 1062 corresponds to the first semiconductor region 1. Another portion of the silicon epitaxial layer 101 corresponds to the fourth semiconductor region 4, the semiconductor region 6, and the semiconductor region 7. The p-type avalanche layer 109 corresponds to the second semiconductor region 2. The n-type avalanche layers 113a and 113b correspond respectively to the third and fifth semiconductor regions 3 and 5. The silicon oxide film 1061 and the buried oxide film 1063 correspond respectively to the insulating layers 30a and 30b. The silicon oxide film 107 corresponds to the insulating layer 41. The insulating film 114 corresponds to the insulating layer 42. The insulating film 118 corresponds to the insulating layer 43. The passivation film 124 corresponds to the insulating layer 44. The quenching resistance 112 corresponds to the first quenching part 51. The titanium film 120, the titanium nitride film 121, and the tungsten film 122 correspond to the plugs. The aluminum layer 123 corresponds to the first interconnect 61, the interconnect 61b, the second interconnect 62, and the interconnect 62b. The pads 153a and 153b correspond respectively to the first and second pads 71 and 72.
Effects of the first embodiment will now be described.
In the first element 11 as shown in
It is desirable for the depletion layer DL1 to be separated from the conductive layer 22. This is because if the depletion layer DL1 reaches the conductive layer 22, carriers that exist in the conductive layer 22 diffuse into the depletion layer DL1, avalanche breakdown occurs, and noise is caused. On the other hand, if the depletion layer DL1 is separated from the conductive layer 22, when a large amount of light enters the first element 11 and many carriers C are generated, the carriers C are generated not only in the depletion layer DL1 but also below the depletion layer DL1. The carriers C that are generated below the depletion layer DL1 diffuse through the semiconductor region until disappearing.
The carriers C that diffuse into the depletion layer DL1 drift through the depletion layer DL1 and cause avalanche breakdown to occur. For example, avalanche breakdown continuously occurs if the multiple carriers C progressively drift into the depletion layer DL1. Thereby, a saturation phenomenon called pile up occurs in the first element 11. For example, after the pulse signal based on the initial avalanche breakdown is detected, a long tail accompanies the pulse signal due to the avalanche breakdown that continuously occurs. While the tail exists, a sufficient gain cannot be obtained in the first element 11, and the first element 11 is in a dead state.
For this problem, the light detector 100 further includes the second element 12. In the second element 12, a depletion layer DL2 spreads from the interface between the fourth semiconductor region 4 and the fifth semiconductor region 5 when the reverse voltage is applied between the fourth semiconductor region 4 and the fifth semiconductor region 5. The impurity concentration of the first conductivity type in the fourth semiconductor region 4 is less than the impurity concentration of the first conductivity type in the second semiconductor region 2. Therefore, the depletion layer DL2 of the second element 12 spreads downward more easily than the depletion layer DL1 of the first element 11. For example, in the first element 11, the entire second semiconductor region 2 is depleted, and the depletion layer DL1 spreads to the semiconductor region 6. In the second element 12, the entire fourth semiconductor region 4 is depleted, and the depletion layer DL2 spreads to the first semiconductor region 1.
A lateral electric field is generated in the region below the depletion layer DL1 by the spreading of the depletion layer DL2. The carriers C that accumulate below the depletion layer DL1 are pulled into the depletion layer DL2 by the lateral electric field as shown by arrows A, and the carriers C drift through the depletion layer DL2 and flow toward the fifth semiconductor region 5. Due to the ejection of the carriers C by the second element 12, the time that the carriers C accumulate below the depletion layer DL1 can be reduced even when a large amount of light enters the first element 11. As a result, the time in the dead state of the first element 11 can be reduced.
The signal that is generated by the avalanche breakdown in the first element 11 passes through the first interconnect 61 and is extracted from the first pad 71. The signal that is generated in the second element 12 passes through the second interconnect 62 and is ejected from the second pad 72. For example, by using only the signal extracted from the first pad 71, it is possible to reduce the dead time or increase the measurement precision of the light time-of-flight.
Secondary photons also are generated when the light enters the first element 11. A portion of the secondary photons travels toward the adjacent first elements 11. The refractive index of the insulating body 30 (the first insulating portion 31) is different from the refractive index of the first element 11. Therefore, at least a portion of the secondary photons is reflected by the interface of the insulating body 30. By providing the insulating body 30, the crosstalk noise can be reduced.
Favorably, as shown in
For example, the first insulating portion 31 is a five-or-higher-sided polygon when viewed along the first direction D1. In the example shown in
The length in the second direction D2 of the first extension portion 31a is greater than the length in the second direction D2 of the link portion 31c. The length in the third direction D3 of the second extension portion 31b is greater than the length in the third direction D3 of the link portion 31c. For example, the link portion 31c has a straight-line shape when viewed along the first direction D1. It is favorable for an angle θ1 between the first extension portion 31a and the link portion 31c to be 135 degrees or more. It is favorable for an angle θ2 between the second extension portion 31b and the link portion 31c to be 135 degrees or more.
It is favorable for a length L1 in the second direction D2 of the link portion 31c and a length L2 in the third direction D3 of the link portion 31c each to be 1 μm or more.
Or, when viewed along the first direction D1 as shown in
In the light detector 100r according to the reference example shown in
As shown in
Also, if cracks occur in the silicon epitaxial layer 101, the silicon oxide film 1061, or the buried oxide film 1063 when forming the silicon oxide film 1061 and the buried oxide film 1063 corresponding to the first insulating portion 31, there is a possibility that a resist in a subsequent photolithography process may enter the cracks. If the resist enters the cracks, a residue of the resist in the cracks occurs when the resist is stripped away. The residue of the resist causes organic contamination of oxidation ovens in subsequent heating processes such as oxidization. By relaxing the stress on the silicon epitaxial layer 101, the silicon oxide film 1061, and the buried oxide film 1063, the occurrence of cracks can be suppressed, and the yield of the light detector 100 can be increased.
In the structure of the insulating body 30 shown in
In the example shown in
In the example described herein, the first insulating portion 31 includes the pair of first extension portions 31a, the pair of second extension portions 31b, and the multiple link portions 31c. It is sufficient for the first insulating portion 31 to include at least one first extension portion 31a, one second extension portion 31b, and one link portion 31c connected to each other. Thereby, the stress at the vicinity of the region where the one first extension portion 31a, the one second extension portion 31b, and the one link portion 31c are provided can be relaxed.
In the light detector 200 according to the second embodiment as shown in
As shown in
The fifth semiconductor region 5 is electrically connected to the second interconnect 62. For example, the fifth semiconductor region 5 is electrically connected to the second interconnect 62 via a plug 62d, an interconnect 62e, a plug 62f, a second quenching part 52, and a plug 62g.
The electrical resistance of the second quenching part 52 is greater than the electrical resistances of the plug 62d, the interconnect 62e, the plug 62f, the second quenching part 52, and the plug 62g. It is favorable for the electrical resistance of the second quenching part 52 to be not less than 50 kΩ and not more than 2 MΩ. Materials and structures that are similar to those of the plugs 61a, 61c, and 61d are applicable to the plugs 62d, 62f, and 62g.
As shown in
A semiconductor region 8 of the first conductivity type may be provided along the first plane around the second insulating portion 32. The semiconductor region 8 includes the same semiconductor material as the first semiconductor region 1. The p-type impurity concentration in the semiconductor region 8 is, for example, not less than 1.0×1013 atoms/cm3 and not more than 1.0×1016 atoms/cm3. The p-type impurity concentration in the semiconductor region 8 may be equal to the p-type impurity concentration in the first semiconductor region 1.
As shown in
By providing the semiconductor region 8 around the multiple second elements 12, the distance between the multiple second elements 12 and the outer perimeter end portion of the light detector 200 can be increased. Thereby, for example, the likelihood of damage to the second element 12 occurring when dicing the semiconductor substrate in the manufacturing processes of the light detector 200 can be reduced.
It is favorable for the conductivity type of the semiconductor region 8 to be the same conductivity type as the first semiconductor region 1. Thereby, the potential of the semiconductor region 8 can be fixed to the potential of the conductive layer 22 via the first semiconductor region 1. A floating state of the potential of the semiconductor region 8 can be suppressed.
As shown in
When light is incident on the first element 11, the light also may be incident on the semiconductor region 8. At this time, the carriers C accumulate also in the semiconductor region 8 due to photoelectric conversion. When the second element 12 is not provided, there is a possibility that the accumulated carriers C may diffuse into the first element 11 and cause a dead state of the first element 11 to occur. By providing the second element 12 between the first element 11 and the semiconductor region 8, the carriers C that are generated in the semiconductor region 8 can be ejected via the second element 12. The occurrence of the dead state of the first element 11 due to the carriers C of the semiconductor region 8 is suppressed thereby.
The configuration of the light detector 200 according to the second embodiment is combinable as appropriate with the configuration of the light detector 100 according to the first embodiment. For example, one second element 12 may be provided between a pair of first elements 11 adjacent to each other in the fourth direction D4; and other multiple second elements 12 may be provided around the multiple first elements 11. For example, the one second element 12 and the multiple second elements 12 may be electrically connected to the same second pad 72 via the multiple second interconnects 62. According to this combination, the time in the dead state can be reduced for more of the first elements 11.
The embodiment is applicable to a long-distance subject detection system (LIDAR) or the like including a line light source and a lens. The lidar device 5001 includes a light projecting unit T projecting laser light toward an object 411, and a light receiving unit R (also called a light detection system) receiving the laser light from the object 411, measuring the time of the round trip of the laser light to and from the object 411, and converting the time into a distance.
In the light projecting unit T, a laser light oscillator (also called a light source) 404 produces laser light. A drive circuit 403 drives the laser light oscillator 404. An optical system 405 extracts a portion of the laser light as reference light, and irradiates the rest of the laser light on the object 411 via a mirror 406. A mirror controller 402 projects the laser light onto the object 411 by controlling the mirror 406. Herein, “project” means to cause the light to strike.
In the light receiving unit R, a reference light detector 409 detects the reference light extracted by the optical system 405. A light detector 410 receives the reflected light from the object 411. A distance measuring circuit 408 measures the distance to the object 411 based on the reference light detected by the reference light detector 409 and the reflected light detected by the light detector 410. An image recognition system 407 recognizes the object 411 based on the results measured by the distance measuring circuit 408.
The lidar device 5001 employs ToF in which the time of the round trip of the laser light to and from the object 411 is measured and converted into a distance. The lidar device 5001 is applied to an automotive drive-assist system, remote sensing, etc. Good sensitivity is obtained particularly in the near-infrared region when the light detectors of the embodiments described above are used as the light detector 410. Therefore, the lidar device 5001 is applicable to a light source of a wavelength band invisible to humans. For example, the lidar device 5001 can be used for obstacle detection in a vehicle.
A light source 3000 emits light 412 toward an object 600 which is the detection object. A light detector 3001 detects light 413 that passes through the object 600, is reflected by the object 600, or is diffused by the object 600.
For example, the light detector 3001 realizes a highly-sensitive detection when the light detector according to the embodiment described above is used. It is favorable to provide multiple sets of the light detector 410 and the light source 404 and to preset the arrangement relationship in the software (which is replaceable with a circuit). For example, it is favorable for the arrangement relationship of the sets of the light detector 410 and the light source 404 to be provided at uniform spacing. Thereby, an accurate three-dimensional image can be generated by the output signals of each light detector 410 complementing each other.
The vehicle 700 according to the embodiment includes the lidar devices 5001 at four corners of a vehicle body 710. Because the vehicle according to the embodiment includes the lidar devices at the four corners of the vehicle body, the environment in all directions of the vehicle can be detected by the lidar devices.
In each of the embodiments described above, the relative levels of the impurity concentrations between the semiconductor regions can be confirmed using, for example, a SCM (scanning capacitance microscope). The carrier concentration in each semiconductor region can be considered to be equal to the activated impurity concentration in each semiconductor region. Accordingly, the relative levels of the carrier concentrations between the semiconductor regions also can be confirmed using SCM. The impurity concentration in each semiconductor region also can be measured by, for example, SIMS (secondary ion mass spectrometry).
According to the embodiments described above, the dead time of the light detector can be reduced.
In the specification of the application, “perpendicular” and “parallel” refer to not only strictly perpendicular and strictly parallel but also include, for example, the fluctuation due to manufacturing processes, etc. It is sufficient to be substantially perpendicular and substantially parallel.
Hereinabove, exemplary embodiments of the invention are described with reference to specific examples. However, the embodiments of the invention are not limited to these specific examples. For example, one skilled in the art may similarly practice the invention by appropriately selecting specific configurations of components included in light detectors such as electrodes, conductive layers, semiconductor regions, insulating bodies, quenching parts, plugs, interconnects, pads, etc., from known art. Such practice is included in the scope of the invention to the extent that similar effects thereto are obtained.
Further, any two or more components of the specific examples may be combined within the extent of technical feasibility and are included in the scope of the invention to the extent that the purport of the invention is included.
Moreover, all light detectors, light detection systems, lidar devices, and vehicles practicable by an appropriate design modification by one skilled in the art based on the light detectors, the light detection systems, lidar devices, and the vehicles described above as embodiments of the invention also are within the scope of the invention to the extent that the purport of the invention is included.
Various other variations and modifications can be conceived by those skilled in the art within the spirit of the invention, and it is understood that such variations and modifications are also encompassed within the scope of the invention.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention.
Number | Date | Country | Kind |
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2020-049455 | Mar 2020 | JP | national |